EXPERIMENT NO.
8
LATCHES AND FLIP-FLOPS
Learning Outcomes
1. Understanding the operation and constructions of various latches and flip-flops.
2. Simulation of latches and flip-flops in Xilinx ISE.
3. Realization and verification of function table of latches and flip-flops in the digital IC
trainer kit
Components Required
7474-Dual D flip-flop
7486-Quad 2-input XOR 7400-Quad 2-input NAND
I Realization and verification of function tables of Latches and Flip-flops using Digital IC
trainer kit
Run #01: S R-latch using NOR gates: An S R latch is constructed with two cross-coupled
NOR gates. Draw the diagram of a cross-coupled S R latch below. Construct the circuit and
connect the two inputs to toggle switches and the two outputs to LEDs. Note down the function
table of the circuit below.
S R Q Q’
0 0
0 1
1 0
1 1
Run #02: D Latch realization on Digital Trainer Kit
Now construct a D latch with the required number of NAND gates. Draw the diagram below.
Write the function table of a D latch.
1
En D Q Q(t+1)
0 x Q
1 0 0
1 0 1
1 1 0
1 1 1
Run #03: D Flip-flop realization on Digital Trainer Kit
IC 7474 is a dual positive edge triggered D flip-flop IC with preset and clear. The pin assignment
of the IC is given in Appendix A. The preset and clear inputs are asynchronous inputs and are
independent of clock.
INPUTS OUTPUTS
Preset’ Clear’ CLK D Q Q’
0 0 x x
0 1 x x
1 0 x x
1 1 0
1 1 1
1 1 x
2
II. Experiment
Latches and flip-flops are bi-stable storage devices. They are called bi-stable because they can
reside in either of two states using a suitable feedback arrangement. The main difference
between latches and flip-flops is in the method used for changing the state. While latches are
level triggered, flip-flops are edge-triggered.
Run #04: S R Latch
Verilog (Gate-Level) modeling of S R Latch using NOR Gate
module nor_latch(
input s, r,
output q, q_bar );
nor g1(q, r, q_bar);
nor g2(q_bar, s, q);
endmodule
Test bench
module nor_latch_tb;
reg s, r;
wire q, q_bar;
nor_latch int (.s(s),.r(r),.q(q),.q_bar(q_bar));
initial begin
s<=1’b0 ;
r<=1’b0 ;
#10 ;
s<=1’b0 ;
r<=1’b1 ;
#10 ;
s<=1’b1 ;
r<=1’b0 ;
#10 ;
s<=1’b1 ;
r<=1’b1 ;
$finish;
3
end
endmodule
Expected output:
Observation table for Run 4
S R Q Q’
0 0
0 1
1 0
1 1
Run #05: Flip-Flops
Latches respond to change in the levels of clock pulses. On the other hand a flip-flop responds to
only a transition in the clock pulse i.e flip-flops are edge triggered and changes state either at the
positive or negative edges of the clock pulse.
Write Verilog code for D flip-flop using behavioral modeling.
Verilog code D Flip-flop
Testing of D Flip-flop
D Flip-flops need clock is one of the inputs. This section explains the generation of clock and oth
input patterns for D-flip-flop. For the above example of D Flip-flop let us assume the following
waveforms have to be given as inputs D, Clk and Rst.
INPUTS OUTPUTS
Preset’ Clear’ CLK D Q Q’
0 0 x x
0 1 x x
1 0 x x
1 1 0
4
1 1 1
1 1 x
5
Important: Flip-flop based circuits should be initially reset. In the above example Rst is made 0 for 3
time units so that the flip-flop initializes to logic ‘0’. After 3 time units the Rst is given logic 1 to
check the normal operation of D Flip-flop
Here we have to generate three different waveforms. The simplest way of doing that is to have three
different initial blocks in the test bench. The partial code for the test bench is shown below.
Common errors: Before calling the instructor try to debug the errors yourself. Find below some
instructions/precautions that could help while debugging.
1. Syntax errors will be shown in the console window. Check the line number where the syntax
error is and see if you have done something wrong there may be a missing semicolon or an
unexpected symbol etc.
2. If there are no syntax errors and you are not getting the output when you run the testbench,
then the problem might be in the order of module instances or you might be simulating the
design file rather than the testbench file.
3. Always follow the same order in module instance as in the design module.
4. Generate the test bench only when the complete design is ready. If there are any changes made
in the module port definition, you have to generate the testbench again
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Run #06: (Optional Run) D Latch : D Latch simulation on Verilog (Gate Level)
A D-latch circuit with active high enable (i.e. D-latch is positive level sensitive) is shown in the figure
below.
Implementation : Write Verilog code for gate-level design of D-latch using primitive gates. In
this design you require four 2-input NAND gates and one inverter.
NOTE : Testing of D-Latch / flip-flops to be done using Verilog Test fixture only. Follow the
example code given below.
Partial Verilog code D-latch
Expected Output
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Why outputs are unknown for first 5 time units? Find out before next lab.
Testing of D-latch
For testing the latches and flip-flops a particular waveform might have to be generated as inputs. This
section explains about generation of specific waveforms for driving inputs. For the above example of
D-latch let us assume the following waveforms have to be given as inputs D and En.
The simplest way to generate two different waveforms in the test bench is to have two separate initial
blocks. In the wave forms above En is 0 for first 5 time units and then is logic 1 for next 10 time units
and so on. The test bench for the D-latch with above input patterns is shown below. Check the output
for the above test pattern.
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Observation table for Run 6
En D Q Q(t+1)
0 x Q
1 0 0
1 0 1
1 1 0
1 1 1
II Verilog
Reading Assignment
Sections: 5.6; ‘Digital Design’ by Morris Mano.
Sections: 6.5.3; ‘Verilog HDL’ by Samir Palnitkar.
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From previous sessions you have learnt the different modelling styles in Verilog. In this session
we will explain all the modelling styles for flip-flops and related circuits. With this session you
will begin coding sequential circuits before which you should be correct in the usage of blocking
and non-blocking assignments i.e. = and <=. Sequential operations are described using <= and
combinational using =. The modelling of clock and reset will be done using the key words
posedge and negedge.
Verilog Assignments
Exercise #01: J K flip-flop—a versatile and widely used flip-flop. IC 7476 is a dual master-slave
J K flip-flop with preset and clear.
Implement Verilog module for JK flip-flop using ‘case’ in behavioral modeling
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Testing of JK Flip-flop
Generate clock as mentioned in D flip-flop example. Give JK values as (0 0), (0 1), (1 0), (1 1) in the
test bench.
III Test yourself
1. How would an S R latch constructed from cross-coupled NOR gates be different from
that constructed from cross coupled NAND gates?
2. How does an S R latch find application in the construction of toggle switches?
3. What is the importance of asynchronous inputs such as preset and clear?
4. Define set up and hold time in the context of a) flip-flop b) latch. Draw suitable diagrams
to explain the same.
5. How do set up and hold time limit the operation of flip-flops and latches?
6. The data sheet of a certain flip-flop specifies the minimum high time for clock pulse to be
30 ns and minimum low time to be 37 ns. What is the maximum operating frequency?
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