Logic Circuit Design Lab

(ICE2005)
Week 7

Instructor: Il Yong Chun, EEE & AI

(Revised by Il Yong Chun, 22-10-09)

Objectives
l Review flip flops.

l Design and implement flip flops.

l Design your own testbench.

2
Agenda
l Verilog today
• Clock
• Timescale
• Asynchronous and synchronous input

l Flip Flops

l Homework

3
Verilog Today

4
Clock
l Signal for
• Sequential logics
• All the hardware designs that you will work on

l A simple single-bit signal that periodically oscillates

Time
5
Clock: Frequency and Period
l Frequency: How many the clock oscillates in a second?

l Unit: Hertz (Hz)

• Ex) 1 billion time/second? --> 1 GHz

l Period: Reciprocal number of frequency

Period: 1ns Time

6
Clock: Edges

Time

Negative Positive
edge edge

7
Timescale
l What is timescale?
• Definition of “Unit of delay” and “Precision”
• Delay: #Num à We all know this.

l You may see this in the testbench files.

`timescale 1ns/1ns

Precision
Basic unit
(Minimum period
of delay
that a single delay supports)
8
More About Delay Unit and Precision
l Example
`timescale 1ns/100ps //Unit of delay: 1ns, precision: 100ps
(In a part of a testbench)
#10 a <= 1’b1; //Delay: 10ns
#1 a <= 1’b0; //Delay: 1ns
#1.1 a <= 1’b1; //Delay: 1.1ns (1ns + 100ps)

9
More About Delay Unit and Precision
l Example
`timescale 1ns/100ps //Unit of delay: 1ns, precision: 100ps
(In a part of a testbench)
#1.01 a <= 1’b0; //Delay: 1ns (1ns + 100ps)?
#1.05 a <= 1’b0; //Delay: 1.1ns (1ns + 100ps)?

Round and apply delays

10
Syntax for Clock
l Going back to a slide of the week 1 class
initial
begin

forever
begin
#10 CLK = !CLK;
end
end

11
Syntax for Clock Edges
l Let’s assume an 1-bit full adder.
input a, b, carry_in;
output sum, carry_out;
reg sum, carry_out;

always @ (posedge clk) //à Adder 1

begin
{carry_out, sum} <= a + b + carry_in;
end

always @ (negedge clk) //à Adder 2

begin
{carry_out, sum} <= a + b + carry_in;
12
end
What Would Waveform Look Like?

Adder 2 Adder 1
(negedge) (posedge)

Input
A=1
B=1
CARRY_IN = 1 13
Inputs to Sequential Logics
l Asynchronous input
• Incoming inputs that take an effect to output in any instances

l Synchronous input
• Incoming inputs that takes effects at clock edges

14
Going Back to Waveform with Adders

Input
A=1 Asynchronous
B=1 Input!
CARRY_IN = 1 15
Flip Flops

16
Basic of Flip Flops
l Flip Flop: A circuit maintaining a state until inputs change

l Inputs include
• Set
• Reset
• Clock

l You may consider flip flops as

extended implementations of latches
operated with synchronous inputs.
(a.k.a. edge-triggered latches)

17
Types of Flip Flop
l SR flip flop

l D flip flop

l JK flip flop
Homework!
(Details later)
l T flip flop

18
What to Cover in This Class
l Truth tables

l Schematic

l What would be proper modeling schemes?

l Sample codes

19
SR Flip Flop
l Logic based on clock and synchronous inputs
(We study a positive clock edge-triggered SR flip flop
in this class.)

S (Set) Q
SR
CLK Flip
Flop
R (Reset) Q

20
SR Flip Flop: Truth Table
l Truth table: The same as that of SR latch
(Clock does not need to be included.)
Only at a positive clock edge

S R Q Q

0 0 Latch (Maintain outputs)

0 1 0 1

1 0 1 0

1 1 Undefined
21
SR Flip Flop (Clocked)
l Gate-level implementation (with NOR gates)

R
Q

CLK

Q
S

22
SR Flip Flop (Clocked)
l Gate-level implementation (with NAND gates)
S
Q

CLK

Q
R

Similar to gated SR latch

23
Flip Flop Modeling
l What we are studying
• Behavioral modeling
• Dataflow modeling
• Gate-level modeling
• Structural modeling

l Are all these modeling schemes applicable to

the clocked flip flop implementations?

24
SR Flip Flop: Behavioral Modeling
module sr_flip_flop_behavioral_module (s, r, clk, q, q_bar);
input s, r;
input clk;
output q, q_bar;
reg q, q_bar;

always @ (posedge clk)

begin
case({s, r})
2'b00: begin q <= q; q_bar <= q_bar; end
2'b01: begin q <= 1'b0; q_bar <= 1'b1; end
2'b10: begin q <= 1'b1; q_bar <= 1'b0; end
2'b11: begin q <= 1'b0; q_bar <= 1'b0; end
endcase
end
endmodule

25
SR Flip Flop: Dataflow Modeling
module sr_flip_flop_dataflow_module (s, r, clk, q, q_bar);
input s, r;
input clk; //clock

output q, q_bar;

wire q_tmp, q_bar_tmp;

assign q = (clk == 1'b1) ? !(r || q_bar) : q;

assign q_bar = (clk == 1'b1) ? !(s || q) : q_bar;

endmodule

26
 SR Flip Flop: Gate-level Modeling
module sr_flip_flop_gatelevel_module (s, r, clk, q, q_bar);
input s, r;
input clk; //clock

output q, q_bar;

wire and_1_output, and_2_output;

wire or_1_output, or_2_output;

and_gate and_1(.a(clk), .b(s), .out(and_1_output));

and_gate and_2(.a(clk), .b(r), .out(and_2_output));

or_gate or_1(.a(and_2_output), .b(q_bar), .out(or_1_output));

not_gate not_1(.a(or_1_output), .out(q));

or_gate or_2(.a(and_1_output), .b(q), .out(or_2_output));

not_gate not_2(.a(or_2_output), .out(q_bar));

endmodule 27
 SR Flip Flop with Asynchronous Input
module tb_w7;

...

initial
begin
forever
begin
#10 CLK = !CLK;
end
end

#15
#20 S = 1'b0; R = 1'b0;
Creating
#20 S = 1'b0; R = 1'b1; Asynchronous
#20 S = 1'b1; R = 1'b0; Input

28
SR Flip Flop with Asynchronous Input
l Waveform

Output has
changed at a
not-edge state!

Not quite our direction

29
Our Direction for Flip Flop Modeling
l Behavioral modeling

l Dataflow modeling

l Gate-level modeling

l Structural modeling
(using module based on behavioral modeling)

30
D Flip Flop
l What we study:
A positive clock edge-triggered D latch

D Q
D
CLK Flip
Flop
Q

31
D Flip Flop
l Truth table

Only at a positive clock edge

D Q Q

0 0 1

1 1 0

32
D Flip Flop (Clocked)
l Schematic

D
Q

CLK

33
D Flip Flop: Behavioral Modeling
module d_flip_flop_behavioral_module (d, clk, q, q_bar);
input d;
input clk; // clock

output q, q_bar;
reg q, q_bar;

always @ (posedge clk)

begin
q <= d;
q_bar <= !d;
end
endmodule

34
D Flip Flop (Clocked)
l Take a look at this.

D
Q

CLK

SR Flip Flop 35
 D Flip Flop: Structural Modeling
module d_flip_flop_structural_module (d, clk, q, q_bar);
input d;
input clk; // clock

output q, q_bar;

wire not_1_output;

not_gate not_1(.a(d), .out(not_1_output));

sr_flip_flop_behavioral_module sr_flip_flop_behavioral
(.s(d), .r(not_1_output), .clk(clk), .q(q), .q_bar(q_bar));

endmodule

36
D Flip Flop Simulation
l Waveform

OK!

37
Homework

38
What to Do
l Design and implement
• JK flip flop
• T flip flop

l Use
• Behavioral modeling
• Structural modeling

39
JK Flip Flop
l A flip flop that includes the behavior when S=1 and R =1
l S become J, and R becomes K
(J and K denote Jack and Kilby, respectively).

J Q
JK
CLK Flip
Flop
K Q

40
JK Flip Flop: Truth Table
Only at a positive clock edge

J(=S) K(=R) Q Q

0 0 Latch (Maintain outputs)

0 1 0 1

1 0 1 0

1 1 Flip previous output.

41
JK Flip Flop (Clocked)
l Gate-level implementation (with NOR gates)

K
Q

CLK

Q
J

42
T Flip Flop
l A flip flop that toggles output.

T Q
T
CLK Flip
Flop
Q

43
T Flip Flop: Truth Table

Only at a positive clock edge

T Q Q

0 Latch (Maintain outputs)

1 Toggle previous output.

44
 T Flip Flop (Clocked)
l Gate-level implementation (with NOR gates)

T
Q

CLK

45
Homework: Theoretical Approach
l You have nothing to do regarding theoretical design.

l The instructor already provided theoretical approaches,

so do not include them in your report.

46
Homework: Behavioral Modeling
l Two ways of implementation with behavioral modeling
• if~else
• case

l Choose what you prefer

• No restriction
• No absolute answer
• However, your module should work correctly.

l FYI, you already have a good hint.

47
Homework: Structural Modeling
l Use SR latch or SR flip flop
• Anything is fine.
• While using a latch or a flip flop,
use a behavioral modeling implementation.

l You may add basic logic gates (AND/OR/NOT),

wire, and regs if you want.
• NAND, NOR, XOR, XNOR gates are not allowed to use.
• In structural modeling, using logic gates only is not allowed.
(That is equivalent to the gate-level modeling.)

48
Create Everything from Scratch
l No empty files are given (except the testbench file).
• Create them by yourself.

l Of course, you should declare all the ports, regs, and wires
by yourself.

l Create your own testplan.

49
 Requirements (Read This Carefully!)
l Dissatisfying the following will lead to score deductions.

l Include a brief description of the objective of this week’s

experiment at the beginning of your report.

l Verilog implementations
• Behavioral modeling
§ A hybrid implementation is not allowed.
• Structural modeling
§ Use behavioral modeling-based latches or flip flops.
§ If you need logic gates, use the source codes of AND, OR, NOT gates,
which are provided by the instructor.
(Using built-in primitive gates in Verilog is not allowed.)
50
 Your Source Codes
l Download
• Download a zip file in I-Campus (W7_Source.zip)
• Unpack the zip file and place the source codes into your project folder.
• Create a new ModelSim project and do your homework.

l Coding
• In each file, find “//Fill this out”
• Literally, fill the empty parts out.
• Read the comments in the file very carefully.

51
 Your Source Codes
l Upload to I-Campus
• Create a folder and name it with your student number.
• Copy all the (.v) files into the created folder.
• Submit the zip file with your report to I-Campus.

Submit
the zip file
Simply,
copy and paste to I-Campus
all the .v files with your
In your project
folder
(Including the
sample files). 52
 Deadline
l Refer to I-Campus.

l I STRONGLY recommend avoiding late submission.

l Each delay in submission of a second after the deadline will

result in penalty in the attendance score.

l Each delay in submission of a day and more after the deadline

will result in….
à 0 score for the corresponding report.
à Regarded as an absence.
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