Logic Circuit Design Lab
(ICE2005)
Week 9
Instructor: Il Yong Chun, EEE & AI
(Revised by Il Yong Chun, 22-10-17)
Objectives
l Review counters.
l Design and implement counters.
2
Agenda
l Counters
l Homework
3
Counters
4
Basic of Counters
l Intuitively, counters
• Increment number(s)
• Decrement number(s)
l Counters as hardware logics regularly do one of
• Incrementing number(s).
• Decrementing number(s).
• Changing bitset(s).
l Regularly?
• Action at clock edges
• Action by predetermined rules
5
Counters: Basic Operations
l Have initialized value(s)
l Detect predetermined event(s) including
• Clock edge
• Or whatever designers make
l Change output at an event
6
Types of Counters
l Simple counter
l Up-down counter
l Ripple counter
l Ring counter
l etc. (Johnson counter, Ring Johnson counter)
7
Simple Counter
l Simply, the basic counter increments a number at a clock
edge.
Output: 0000 à 0001 à 0010 à 0011 à 0100
l It is also called an up counter.
8
Simple Counter: Behavioral Modeling
module simple_counter_behavioral_module(clk, rst, out);
input clk;
input rst;
output [3:0] out;
reg [3:0] out;
always @ (posedge clk)
begin
if(rst == 1'b1)
begin
out <= 1'b0;
end
else
begin
out <= out + 1'b1;
end
end
9
endmodule
One Step Further
l Up-down counter
l Up-down counter has two modes
• Up
• Down
l It increments or decrements a number at a clock edge
depending on the current mode.
Output (Up mode): 0000 à 0001 à 0010 à 0011 à 0100
Output (Down mode): 0000 à 1111 à 1110 à 1101 à 1100
10
Up-Down Counter: Behavioral Modeling
module updown_counter_behavioral_module(clk, rst, mode, out);
input clk;
input rst;
input mode; //1 for up, 0 for down
output [3:0] out;
reg [3:0] out;
always @ (posedge clk)
begin
if(rst == 1'b1)
begin
out <= 1'b0;
end
else
begin
if(mode == 1'b1) //up
out <= out + 1'b1;
else //down
out <= out - 1'b1;
end
end
endmodule
11
Up-Down Counter: Simulation Results 1
l Up mode
12
Up-Down Counter: Simulation Results 2
l Down mode
13
Ripple Counter
l A multi-stage counter that consists of multiple cascaded flip
flops
l A structural modeling of simple counter
l We can design a ripple counter as a structural modeling
implementation of a down counter as well.
14
4-Bit Ripple Counter: A Schematic
l With D flip flops
D Q D Q D Q D Q
D D D D
Flip Flip Flip Flip
Flop Flop Flop Flop
CLK Q CLK Q CLK Q CLK Q
4-Bit Output
15
Check New and Incomplete D Flip Flop
module d_flip_flop_behavioral_module (d, clk, rst, preset, q, q_bar);
input d;
input clk; // clock
input rst;
input preset;
output q, q_bar;
reg q, q_bar;
always @ (posedge clk)
if(rst == 1'b1)
begin
if(preset == 1'b1)
begin For your
homework
q <= 1'b1;
q_bar <= 1'b0;
end
else
begin
q <= 1'b0;
q_bar <= 1'b1;
end
end
else
begin
q <= d;
q_bar <= !d;
end
endmodule 16
Ripple Counter: Code Example
module ripple_counter_module(clk, rst, preset, out);
input clk;
input rst;
input [3:0] preset;
output [3:0] out;
wire [3:0] out_bar;
d_flip_flop_behavioral_module
d_flip_flop_behavioral0(.d(out_bar[0]), .clk(clk), .rst(rst), .preset(preset[0]),
.q(out[0]), .q_bar(out_bar[0]));
d_flip_flop_behavioral_module
d_flip_flop_behavioral1(.d(out_bar[1]), .clk(out_bar[0]), .rst(rst), .preset(preset[1]),
.q(out[1]), .q_bar(out_bar[1]));
d_flip_flop_behavioral_module
d_flip_flop_behavioral2(.d(out_bar[2]), .clk(out_bar[1]), .rst(rst), .preset(preset[2]),
.q(out[2]), .q_bar(out_bar[2]));
d_flip_flop_behavioral_module
d_flip_flop_behavioral3(.d(out_bar[3]), .clk(out_bar[2]), .rst(rst), .preset(preset[3]),
.q(out[3]), .q_bar(out_bar[3]));
endmodule 17
Ripple Counter: Simulation Results
l Here, you don’t need to consider the preset input.
(Check out the testbench file.)
l The results look ok?
18
Ripple Counter: What Else?
l What about using another type of flip flop?
l What is the problem in the current implementation?
l More details in the homework assignment.
19
Ring Counter
l A counter that perform the shift operation.
l Also, it circulates a bit.
(Move the MSB to LSB.)
l What we cover in this class
• Ring counter performing the shift left operation.
20
Ring Counter
l A counter that perform the shift operation at a clock edge
l Also, it circulates a bit.
(Move the MSB to LSB.)
l What we cover in this class
• Ring counter performing the shift left operation.
Output: 0001 à 0010 à 0100 à 1000 à 0001
21
Ring Counter: Behavioral Modeling
module ring_counter_behavioral_module(clk, rst, out);
input clk;
input rst;
output [3:0] out;
reg [3:0] out;
always @ (posedge clk)
begin
if(rst == 1'b1)
begin
out <= 4'b0001;
end
else
begin
if(out == 4'b0000)
out <= 4'b0001;
else
out <= out << 1;
out [0] <= out[3];
end
end
22
endmodule
Ring Counter: Simulation Results
23
Homework
24
What to Do
l Figure out and fix the problem in current implementation of
• Ripple counter with structural modeling
l Design and implement
• Ripple counter with another structural modeling
• Ring counter with structural modeling
25
Homework: Ripple Counter
l In the current implementation in the provided source codes,
figure out the problem and fix it.
l Use JK flip flops. Your implementation should not include
the same problem unlike the example codes.
l Draw a schematic of the ripple counter with JK flip flops.
• You may add basic logic gates (AND/OR/NOT) if you want.
• You may add regs or wires (and relevant `assign`s)
if you want.
• NAND, NOR, XOR, XNOR gates are not allowed to use.
• In structural modeling, using logic gates only is not allowed.
(That is equivalent to the gate-level modeling.) 26
Homework: Ring Counter
l Use NEW D flip flops and modify them if neccessary.
l Draw a schematic of the ring counter with D flip flops.
• You may add basic logic gates (AND/OR/NOT) if you want.
• You may add regs or wires (and relevant `assign`s)
if you want.
• NAND, NOR, XOR, XNOR gates are not allowed to use.
• In structural modeling, using logic gates only is not allowed.
(That is equivalent to the gate-level modeling.)
27
Ring Counter: How To Set Initial Value?
Hint:
Consider
Your preset!
28
Create Everything from Scratch
l No empty files are given (except the testbench file).
• Create them by yourself.
l Of course, you should declare all the ports, regs, and wires
by yourself.
l You don’t need to create your own testplan.
29
Requirements (Read This Carefully!)
l Dissatisfying the following will lead to score deductions.
l Include a brief description of the objective of this week’s
experiment at the beginning of your report.
l Verilog implementations
• Structural modeling
§ If you need logic gates, use the source codes of AND, OR, NOT gates,
which are provided by the instructor.
(Using built-in primitive gates in Verilog is not allowed.)
30
Your Source Codes
l Download
• Download a zip file in I-Campus (W9_Source.zip)
• Unpack the zip file and place the source codes into your project folder.
• Create a new ModelSim project and do your homework.
l Coding
• In each file, write your source code by yourself.
• Leave your comments in the files accordingly.
31
Your Source Codes
l Upload to I-Campus
• Create a folder and name it with your student number.
• Copy all the (.v) files into the created folder.
• Submit the zip file with your report to I-Campus.
Submit
the zip file
Simply,
copy and paste to I-Campus
all the .v files with your
In your project
folder
(Including the
sample files). 32
Deadline
l Refer to I-Campus.
l I STRONGLY recommend avoiding late submission.
l Each delay in submission of a second after the deadline will
result in penalty in the attendance score.
l Each delay in submission of a day and more after the deadline
will result in….
à 0 score for the corresponding report.
à Regarded as an absence.
33
