Registers & Counters

Logic and Digital System Design - CS 303

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 Registers
• Registers are clocked sequential circuits
• A register is a group of flip-flops
– Each flip-flop capable of storing one bit of information
– An n-bit register
• consists of n flip-flops
• capable of storing n bits of information
– besides flip-flops, a register usually contains combinational
logic to perform some simple tasks
– In summary
• flip-flops to hold information
• combinational logic to control the state transition
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 Counters
• A counter is essentially a register that goes through a
predetermined sequence of states
• i.e., “Counting sequence”

FF0 FF1 Register FFn-1

Combinational logic

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 Uses of Registers and Counters
• Registers are useful for storing and manipulating
information
– internal registers in microprocessors to manipulate data
• Counters are extensively used in control logic
– PC (program counter) in microprocessors

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 4-bit Register
D0 D Q Q0 REG
C
R
clear
D0 Q0
D1 D Q Q1
D1 Q1
C
R D2 Q2

D3 Q3

D2 D Q Q2
C
FD16CE
R
16 16
D[15:0] Q[15:0]
D3 D Q Q3
CE
C
clock R C
CLR
clear 5
 Register with Parallel Load
Load
D Q Q0
D0 C
R

D Q Q1
D1 C
R

D Q Q2
D2 C
R

D Q Q3
D3 C
R
clock 6
clear
 Register Transfer 1/2
load

n
R1 R2 R2  R1

clock

clock

R1 010…10 110…11

load

R2 010…10 7
 Register Transfer 2/2

n-bit
adder

n n

load
R1 R2

clock

R1  R1 + R2
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 Shift Registers
• A register capable of shifting its content in one or both
directions
– Flip-flops in cascade

serial SI SO serial
D Q D Q D Q D Q
input output
C C C C

clock

• The state of an n-bit shift register can be transferred in n clock

cycles

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 Serial Mode
• A digital system is said to operate in serial mode when
information is transferred and manipulated one bit a
time.

SI SO SI SO
shift register A shift register B
clock clk clk
shift
control

clock

shift
control

clk
T1 T2 10
T3 T4
 BA Serial Transfer
• Suppose we have two 4-bit shift registers
Timing pulse Shift register A Shift register B
initial value 1 0 1 1 0 0 1 0
After T1
After T2
After T3
After T4 1 0 1 1 1 0 1 1

clock A B
clk clk
shift
control

clk
shift clock
control
T1 T2 T3 T4 11
 Universal Shift Register
• Capabilities:
1. A “clear” control to set the register to 0.
2. A “clock” input
3. A “shift-right” control
4. A “shift-left” control
5. n input lines & a “parallel-load” control
6. n parallel output lines

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 4-Bit Universal Shift Register
parallel outputs
A3 A2 A1 A0

Q Q Q Q
C C C C
D D D D
clear
clk

s1 4 1 4 1 4 1 4 1
MUX MUX MUX MUX
s0
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

serial serial
input for input for
shift-right shift-left
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parallel inputs
 Universal Shift Register

Mode Control

s1 s0 Register operation

0 0 No change

0 1 Shift right

1 0 Shift left

1 1 Parallel load

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 Coding Universal 32-bit Shift Register
module SR_32_BEH(
output reg [31:0] A_par, // Register output
input [31:0] I_par, // Parallel input
input s1, s0, // selection inputs
MSB_in, LSB_in, // Serial inputs
clk, clear); // clock, reset
always @(posedge clk, negedge clear)
if(~clear) A_par <= 32’h00000000;
else
case ({s1,s0})
2b’00: A_par <= A_par // no change
2b’01: A_par <= {MSB_in, A_par[31:1]}; // shift right
2b’10: A_par <= {A_par[30:0], LSB_in}; // shift right
2b’11: A_par <= I_par; // parallel load
endcase
endmodule
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 Counters
• registers that go through a prescribed sequence of
states upon the application of input pulses
– input pulses are usually clock pulses
• Example: n-bit binary counter
– count in binary from 0 to 2n-1
• Classification
1. Synchronous counters
• flip-flops receive the same common clock as the pulse
2. Ripple counters
• flip-flop output transition serves as the pulse to trigger
other flip-flops

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 Binary Ripple Counter
3-bit binary ripple counter

0 0 0 0 • Idea:
1 0 0 1 – to connect the output of one flip-flop to the
2 0 1 0 C input of the next high-order flip-flop

3 0 1 1 • We need “complementing” flip-flops

– We can use T flip-flops to obtain
4 1 0 0
complementing flip-flops or
5 1 0 1 – JK flip-flops with its inputs are tied together
6 1 1 0 or
7 1 1 1 – D flip-flops with the complement output
connected to the D input.
0 0 0 0
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 4-bit Binary Ripple Counter
logic-1 A0
T Q 0 0 0 0 0 D Q A0
count count
C
1 0 0 0 1 C
R R
2 0 0 1 0
3 0 0 1 1
A1 4 0 1 0 0
T Q D Q A1
5 0 1 0 1
C C
R 6 0 1 1 0 R

7 0 1 1 1
A2 8 1 0 0 0
T Q D Q A2
9 1 0 0 1
C C
R 10 1 0 1 0 R
11 1 0 1 1

A3 12 1 1 0 0
T Q 13 1 1 0 1
D Q A3
C C
14 1 1 1 0 R
R
15 1 1 1 1 clear
clear 22
0 0 0 0 0
 4-bit Binary Ripple Counter
T Q A0 – Suppose the current
count C
R
state is 1100
– What is the next state?

T Q A1
C
R

T Q A2
C
R

logic-1
T Q A3
C
R
clear 23
 Verilog of Binary Ripple Counter
`timescale 1ns / 1ps module TestRippleCounter;
module TFF(Q, T, clk, reset); reg Cnt;
input T,reset,clk; reg Rst;
output reg Q; wire [3:0] A;
always @(negedge reset, negedge clk) // Instantiate ripple counter
if(reset) Q <= 1’b0; RippleCounter Counter(A, Cnt, Rst);
else Q <= #1 T^Q; always
endmodule #5 Cnt = ~Cnt;
module RippleCounter( initial
output [3:0] A, begin
input Count, reset); Cnt = 1’b0;
TFF FF0(A[0], 1’b1, Count, reset); Rst = 1’b0;
TFF FF1(A[1], 1’b1, A[0], reset); #4 Rst = 1’b1;
TFF FF2(A[2], 1’b1, A[1], reset); end
TFF FF3(A[3], 1’b1, A[2], reset); initial #170 $finish;
endmodule endmodule
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 Simulation

A
0110 0111 0110 0100 0000 1000

Cnt

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 Synchronous Counters
• There is a common clock
– that triggers all flip-flops simultaneously
– If T = 0 or J = K = 0 the flip-flop
0 0 0 0
does not change state.
1 0 0 1
– If T = 1 or J = K = 1 the flip-flop
2 0 1 0
does change state.
3 0 1 1
• Design procedure is so simple 4 1 0 0
– no need for going through sequential 5 1 0 1
logic design process 6 1 1 0
– A0 is always complemented 7 1 1 1
– A1 is complemented when A0 = 1 0 0 0 0
– A2 is complemented when A0 = 1 and A1 = 1
– so on
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 4-bit Binary Synchronous Counter
T Q A0
C
Count_enable

T Q A1
C Polarity of the
clock is not
essential
T Q A2
C

T Q A3
C

to next
stage
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clock
 Timing of Synchronous Counters

clock

A0

A1

A2

A3

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 Timing of Ripple Counters

clock

A0

A1

A2

A3

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 Up-Down Binary Counter
• When counting downward
– the least significant bit is always complemented (with each
clock pulse)
– A bit in any other position is complemented if all lower
significant bits are equal to 0. 0 0 0 0
– For example: 0 1 0 0 7 1 1 1
• Next state: 6 1 1 0
– For example: 1 1 0 0 5 1 0 1
• Next state: 4 1 0 0
3 0 1 1
2 0 1 0
1 0 0 1
0 0 0 0 30
 Up-Down Binary Counter
up
T Q A0
down
C

T Q A1
C

Q
A2
T
C

• The circuit clock C 31

 Binary Counter with Parallel Load
count
load
D0 J Q A0
C
K

D1 J Q A1
C
K

D2 J Q A2
C
K
carry
clock output

clear 32
 Binary Counter with Parallel Load
Function Table
clear clock load Count Function

0 X X X clear to 0

1 1 X load inputs

1 0 1 count up

1 0 0 no change

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 Verilog of Binary Counter
module BinaryCounter_8_BEH(
output reg [7:0] A_cnt, // Counter output
output C_out, // If a cycle is completed
input [7:0] Data_in, // Parallel input
input Count, // Active high to count
Load, // Active high to load
clk, clear); // clock, reset
assign C_out = Count & (~Load) & (A_cnt == 8’hFF);
always @(posedge clk, negedge clear)
if(~clear) A_cnt <= 8’h00;
else if(Load) A_cnt <= Data_in;
else if(Count) A_cnt <= A_cnt + 1’b1;
else A_cnt <= A_cnt;
endmodule
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 Other Counters
• Ring Counter
– A ring counter is a circular shift register with only one flip-flop
being set at any particular time, all others are cleared.

initial value
shift 1000
right T0 T1 T2 T3

• Usage
– Timing signals control the sequence of operations in a digital
system 35
 Ring Counter
• Sequence of timing signals

clock

T0

T1

T2

T3

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 Ring Counter
• To generate 2n timing signals,
– we need a shift register with 2n flip-flops
• or, we can construct the ring counter with a binary
counter and a decoder
T0 T1 T2 T3
Cost:
• 2 flip-flops
• 2-to-4 line decoder
2x4
Cost in general case:
decoder
• n flip-flops
• n-to-2n line decoder
count 2-bit counter • 2n n-input AND gates
• n NOT gates
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 Johnson Counter
• A k-bit ring counter can generate k distinguishable states
• The number of states can be doubled if the shift register
is connected as a switch-tail ring counter

X Y Z T
D Q D Q D Q D Q

C C C C
X’ Y’ Z’ T’

clock

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 Johnson Counter
• Count sequence and required decoding
sequence Flip-flop outputs
number X Y Z T Output
1 0 0 0 0 S0 = X’T’
2 S1 = XY’
3 S2 = YZ’
4 S3 = ZT’
5 S4 = XT
6 S5 = X’Y
7 S6 = Y’Z
8 S7 = Z’T
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 Johnson Counter
• Decoding circuit
S0 S1 S2 S3 S4 S5 S6 S7

X Y Z T
D Q D Q D Q D Q

C C C C

clock
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 Unused States in Counters
• 4-bit Johnson counter

0000 1000 1100 0010 1001 0100

0001 1110 0101 1010

0011 0111 1111 1011 0110 1101

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 Correction

0000 1000 1100 0010 1001 0100

0001 1110 0101 1010

0011 0111 1111 1011 0110 1101

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 Johnson Counter
Present State Next State
X Y Z T X Y Z T
0 0 0 0 1 0 0 0
1 0 0 0 1 1 0 0
1 1 0 0 1 1 1 0
1 1 1 0 1 1 1 1
1 1 1 1 0 1 1 1
0 1 1 1 0 0 1 1
0 0 1 1 0 0 0 1
0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 1
1 0 0 1 0 0 0 0
0 1 0 0 1 0 1 0
1 0 1 0 1 1 0 1
1 1 0 1 0 1 1 0
0 1 1 0 1 0 1 1
1 0 1 1 0 1 0 1
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0 1 0 1 0 0 1 0
 K-Maps
ZT ZT
XY 00 01 11 10 XY 00 01 11 10
00 1 1 00
01 1 1 01
11 1 1 11 1 1 1 1
10 1 1 10 1 0 1 1

X(t+1) = T’ Y(t+1) = XY + XZ + XT’

ZT ZT
XY 00 01 11 10 XY 00 01 11 10
00 00 1 1
01 1 1 1 1 01 1 1
11 1 1 1 1 11 1 1
10 10 1 1

Z(t+1) = Y T(t+1) = Z 44
 Unused States in Counters
• Remedy X(t+1) = T’ Y(t+1) = XY + XZ + XT’
Z(t+1) = Y T(t+1) = Z

DY = X(Y+Z+T’)

X Y Z T
D Q D Q D Q D Q

C C C C

clock

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