Registers & Counters

Logic and Digital System Design - CS 303

Erkay Savaş
Sabanci University

1
 Registers
• Registers like counters are clocked sequential
circuits
• A register is a group of flip-flops
– Each flip-flop capable of storing one bit of information
– An n-bit register
• consists of n flip-flops
• capable of storing n bits of information
– besides flip-flops, a register usually contains
combinational logic to perform some simple tasks
– In summary
• flip-flops to hold information
• combinational logic to control the state transition
2
 Counters
• A counter is essentially a register that goes
through a predetermined sequence of states

FF0 FF1 flip-flops FFN

Combinational logic

3
 Uses of Registers and Counters
• Registers are useful for storing and manipulating
information
– internal registers in microprocessors to manipulate
data
• Counters are extensively used in control logic
– PC (program counter) in microprocessors

4
 4-bit Register
D0 D Q Q0
C
R
REG

D1 D Q Q1
clear
C
D0 Q0
R
D1 Q1

D2 Q2
D2 D Q Q2
D3 Q3
C
R

D3 D Q Q3
C
clock R
clear 5
 Register with Parallel Load
Load
D Q Q0
D0 C
R

D Q Q1
D1 C
R

D Q Q2
D2 C
R

D Q Q3
D3 C
R
clock 6
clear
 Loading Register

clock

load

C inputs

7
 Register Transfer - 1
load

n
R1 R2 R2 Å R1

clock

clock

R1 010…10 110…11

load

R2 010…10 8
 Register Transfer - 2

n-bit
adder

n n

load
R1 R2

clock

R1 Å R1 + R2
9
 Datapath & Control Unit

Control signals

Control Control Status signals Data

inputs Datapath outputs
Unit

Control Data
outputs inputs

10
 Shift Registers
• A register capable of shifting its information in
one or both directions
– Flip-flops in cascade

serial SI SO serial
D Q D Q D Q D Q
input output
C C C C

clock

• The current state can be output in n clock cycles

11
 Serial Mode
• A digital system is said to operate in serial mode
when information is transferred and manipulated
one bit a time.

SI SO SI SO
shift register A shift register B
clock clk clk
shift
control

clock

shift
control

clk
T1 T2 T3 T4 12
 Serial Transfer
• Suppose we have two 4-bit shift registers

Timing pulse Shift register A Shift register B

initial value 1 0 1 1 0 0 1 0
After T1 1 1 0 1 1 0 0 1
After T2 1 1 1 0 1 1 0 0
After T3 0 1 1 1 0 1 1 0
After T4 1 0 1 1 1 0 1 1

BÅA

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 Serial Addition
• In digital computers, operations are usually
executed in parallel, since it is faster
• Serial mode is sometimes preferred since it
requires less equipment

SI SO
a S
clock shift register A
shift b FA
control C
C_in

serial SI
input SO
shift register B Q D
C

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reset
 Example: Serial Addition
• A and B are 2-bit shift registers

reset

clock

shift
control

SR-A 00 00 00 10 01 00 10

SR-B 00 10 01 10 01 00 00

serial
input

C_in 15
 Designing Serial Adder - 1
Q(t+1) = JQ’ + K’Q
Present state Inputs Next state Output Flip-flop inputs
Q x y Q S JQ KQ
0 0 0 0 0 0 X
0 0 1 0 1 0 X
0 1 0 0 1 0 X
0 1 1 1 0 1 X
1 0 0 0 1 X 1
1 0 1 1 0 X 0
1 1 0 1 0 X 0
1 1 1 1 1 X 0

JQ = xy KQ = x’y’ = (x + y)’ S=x⊕y⊕Q

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 Designing Serial Adder - 2
JQ = xy KQ = x’y’ = (x + y)’ S=x⊕y⊕Q

SI SO = x S
clock shift register A
shift
control

serial SI
input SO = y J
shift register B Q
C
K

reset

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 Universal Shift Register
• Capabilities:
1. A clear control to set the register to 0.
2. A clock input
3. A shift-right control
4. A shift-left control
5. n input lines
6. A parallel-load control
7. n parallel output lines
8. A shift-control

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 Universal Shift Register
parallel outputs
A3 A2 A1 A0

Q Q Q Q
C C C C
D D D D
clear
clk

s1 4×1 4×1 4×1 4×1

MUX MUX MUX MUX
s2
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

serial serial
input for input for
shift-right shift-left
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parallel inputs
Universal Shift Register

Mode Control

s1 s0 Register operation

0 0 No change

0 1 Shift right

1 0 Shift left

1 1 Parallel load

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 Counters
• A counter is basically a register that goes
through a prescribed sequence of states upon
the application of input pulses
– input pulses are usually clock pulses
• Example: n-bit binary counter
– count in binary from 0 to 2n-1
• Classification
1. Ripple counters
• flip-flop output transition serves as the pulse to
trigger other flip-flops
2. Synchronous counters
• flip-flops receive the same common clock as the
pulse
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 Binary Ripple Counter
3-bit binary ripple counter

0 0 0 0 • Idea:
1 0 0 1 – to connect the output of one flip-flop
to the C input of the next high-order
2 0 1 0 flip-flop
3 0 1 1 • We need “complementing” flip-flops
4 1 0 0 – We can use T flip-flops to obtain
complementing flip-flops or
5 1 0 1
– JK flip-flops with its inputs are tied
6 1 1 0 together or
7 1 1 1 – D flip-flops with complement output
connected to the D input.
0 0 0 0
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 4-bit Binary Ripple Counter
T Q A0 D Q A0
count C count C
R R

T Q A1 D Q A1
C C
R R

T Q A2 D Q A2
C C
R R

logic-1 D Q A3
T Q A3
C C
R R

clear clear
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 4-bit Binary Ripple Counter
T Q A0 – Suppose the
count C
R current state is
1100
T Q A1
– What is the next
C
state?
R
– A0 = 1 (0 Æ 1)
– A1 = 1 (0 Æ 1)
Q A2
T
– A2 = 0 (1Æ 0)
C
R – A3 = 1
– next state: 1011
logic-1
T Q A3 • Binary count-down
counter
C
R
clear 24
 BCD Ripple Counter
• State diagram

0000 0001 0010 0011 0100

1001 1000 0111 0110 0101

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 BCD Ripple Counter
• State transitions
A3 A2 A1 A0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0
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BCD Ripple Counter with JK FFs
J Q A0
count C
K

J Q A1
C
K

J Q A2
C
K

J Q A3
C
K

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logic-1
 Multi-digit BCD Counter
A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0

BCD BCD BCD count

Counter Counter Counter pulses

3-digit BCD counter

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 Synchronous Counters
• There is a common clock
– that triggers all flip-flops simultaneously
– If T = 0 or J = K = 0 the flip-flop does not change
state.
– If T = 1 or J = K = 1 the flip-flop does change state.
• Design procedure is so simple
– no need for going through sequential logic design
process
– A0 is always complemented
– A1 is complemented when A0 = 1
– A2 is complemented when A0 = 1 and A1 = 1
– so on

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4-bit Binary Synchronous Counter
J Q A0
count C
K
enable

J Q A1
C Polarity of the
K clock is not
essential
J Q A2
C
K

J Q A3
C
K
to next
stage
30
clock
 Up-Down Binary Counter
• When counting downward
– the least significant bit is always complemented (with
each clock pulse)
– A bit in any other position is complemented if all lower
significant bits are equal to 0.
– For example: 0100
• Next state: 0011
– For example: 1100
• Next state: 1011

31
 Up-Down Binary Counter
up
T Q A0
down
C

T Q A1
C

Q
A2
T
C

• The circuit clock C 32

 Synchronous BCD Counter
• Better to apply the sequential circuit design
procedure
Present state Next state output Flip-Flop inputs
A8 A4 A2 A1 A8 A4 A2 A1 y T8 T4 T2 T1
0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 1 0 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 0 1
0 0 1 1 0 1 0 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 0 1
0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 0 1 1 0 0 1
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 Synchronous BCD Counter
• The flip-flop input equations
– T1 = 1
– T2 = A8’ A1
– T4 = A2A1
– T8 = A8 A1 + A4 A2 A1
• Output equation
– y = A8A1
• Cost
– Four T flip-flops
– four 2-input AND gates
– one OR gate
– one inverter
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 Binary Counter with Parallel Load
count
load
D0 J Q A0
C
K

D1 J Q A1
C
K

D2 J Q A2
C
K
carry
clock output

clear 35
Binary Counter with Parallel Load
Function Table
clear clock load Count Function

0 X X X clear to 0

1 ↑ 1 X load inputs

1 ↑ 0 1 count up

1 ↑ 0 0 no change

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 Other Counters
• Ring Counter
– Timing signals control the sequence of operations in a
digital system
– A ring counter is a circular shift register with only one
flip-flop being set at any particular time, all others are
cleared.

initial value
shift 1000
right T0 T1 T2 T3

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 Ring Counter
• Sequence of timing signals

clock

T0

T1

T2

T3

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 Ring Counter
• To generate 2n timing signals,
– we need a shift register with 2n flip-flops
• or, we can construct the ring counter with a
binary counter and a decoder
T0 T1 T2 T3
Cost:
• 2 flip-flop
• 2-to-4 line decoder
2x4
Cost in general case:
decoder
• n flip-flops
• n-to-2n line decoder
count 2-bit counter • 2n n-input AND gates

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 Johnson Counter
• A k-bit ring counter can generate k
distinguishable states
• The number of states can be doubled if the shift
register is connected as a switch-tail ring
counter

X Y Z T
D Q D Q D Q D Q

C C C C
X’ Y’ Z’ T’

clock

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 Johnson Counter
• Count sequence and required decoding
sequence Flip-flop outputs
number X Y Z T Output
1 0 0 0 0 X’T’
2 1 0 0 0 XY’
3 1 1 0 0 YZ’
4 1 1 1 0 ZT’
5 1 1 1 1 XT
6 0 1 1 1 X’Y
7 0 0 1 1 Y’Z
8 0 0 0 1 Z’T
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 Johnson Counter
• Decoding circuit
S0 S1 S2 S3 S4 S5 S6 S7

X Y Z T
D Q D Q D Q D Q

C C C C

clock
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 Unused States in Counters
• 4-bit Johnson counter

0000 1000 1100 0010 1001 0100

0001 1110 0101 1010

0011 0111 1111 1011 0110 1101

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 Johnson Counter
Inputs Outputs
X Y Z T X Y Z T
0 0 0 0 1 0 0 0
1 0 0 0 1 1 0 0
1 1 0 0 1 1 1 0
1 1 1 0 1 1 1 1
1 1 1 1 0 1 1 1
0 1 1 1 0 0 1 1
0 0 1 1 0 0 0 1
0 0 0 1 0 0 0 0
1 0 1 0 1 1 0 1
1 1 0 1 0 1 1 0
0 1 1 0 1 0 1 1
1 0 1 1 0 1 0 1
0 1 0 1 0 0 0 0
0 0 1 0 1 0 0 1
1 0 0 1 0 1 0 0
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0 1 0 0 1 0 0 0
 K-Maps
ZT ZT
XY 00 01 11 10 XY 00 01 11 10
00 1 1 00
01 1 1 01
11 1 1 11 1 1 1 1
10 1 1 10 1 1 1 1

X = T’ Y=X

ZT ZT
XY 00 01 11 10 XY 00 01 11 10
00 00 1 1
01 1 1 01 1 1
11 1 1 1 1 11 1 1
10 10 1 1

Z = XY + YZ T=Z 45
 Unused States in Counters
• Remedy

DZ = Y(X+Z)

X Y Z T
D Q D Q D Q D Q

C C C C

clock

46
 Unused States in Counters
• State diagram

1011 0101 0100 1001 0010

0110
0000 1000 1100

1101
0001 1110

1010
0011 0111 1111

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