UMBB - IGEE Digital systems II with VHDL
Spring 2024 EE222 – L04
Lab work # 4
Digital counters (1)
Objectives
The objective of this lab assignment is to explore fundamental concepts of asynchronous counters (ripple
counters), and to implement them using discrete ICs, schematic design, and structural VHDL.
Note: The pre-lab of each problem must be prepared before coming to the lab!
Problem 1 – Four-bit UP Counter with 7476 IC
Pre-Lab: Design a 4-bit ripple counter in the up mode using negative-edge triggered JK flip-flops.
In-Lab: Using the provided tools and wires,
1) Construct the 4-bit ripple counter in the up mode, then denote its size.
2) Connect the clock signal to a push button and four LEDs to the output, then test your counter.
3) Now, apply the clock signal of the Digi-designer and set it to 1KHz. Using the two oscilloscope channels,
determine the relationship between each output frequency and the clock signal.
Problem 2 – MOD-12 truncated Up counter with 7476 and 7400 ICs
Pre-Lab: Design a mod-12 up counter using negative-edge triggered JK flip-flops and gates.
In-Lab: Using the provided tools and wires, modify the previous circuit to construct a mod-12 ripple up
counter, then test your counter.
Problem 3 – MOD-12 truncated up counter with schematic design
The Quartus II library of components provides positive edge-triggered JK flip-flops with active-low PR and
CLR (in the BDF window, browse for JKFF).
Pre-lab: The same as the pre-lab for problem 2.
In-Lab: In a new directory (D:\lab4\pbm3),
1) Create a new Quartus project and implement the design of the MOD-12 up counter, save your work then
proceed with analysis and synthesis.
2) Conduct functional simulation with an end time set to 1.6 us, grid size to 100 ns, clock period (T) to 100
ns, with a duty cycle (DC) of 25%.
3) Assign pins, compile, then download the design onto the DE2 board to test its functionality.
Problem 4 – MOD-12 truncated down counter with schematic design
Pre-Lab: Design a MOD-12 truncated down counter using negative-edge triggered JK flip-flops and gates.
In-Lab: In a new directory (D:\lab4\pbm4),
1) Create a new Quartus project and implement the design of the MOD-12 down counter. Save your work
and proceed with analysis and synthesis.
2) Conduct functional simulation with an end time set to 1.6 us, grid size to 100 ns, clock period (T) to 100
ns with a duty cycle (DC) of 25%.
3) Assign pins, compile, then download the design onto the DE2 board to test its functionality.
Hint: The MOD-12 down counter can start counting from 12 down to 1 and reset the counter at 0.
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UMBB - IGEE Digital systems II with VHDL
Spring 2024 EE222 – L04
Problem 5 – Counters using structural VHDL
Pre-lab: Write the VHDL code for the negative-edge triggered JK flip-flop provided with asynchronous
active-low CLR and PR. Thereafter, write the structural VHDL (port map statements) that interconnects JK
FFs to implement the Digital counter of Fig.2, considering the mode selection input (Sel).
In-lab: In a new directory (D:\lab4\pbm5), create a new Quartus II project to implement the digital counter.
After successful analysis, assign pins, compile, then and download the design onto the DE2 board to test the
counters’ functionality.
Note: You can not write port map statements within process block.
Hint: You may use the seven-segment display to display the output.
Sel Qa
Digital
Qb
counter
Clock Qc
Fig.2
Sel Counter Mode
Fig.1: 7476 IC pinout 0 MOD-8 up
1 MOD-8 down
