Scribd
Upload
33 views1 page

Module Alu

This document describes a Verilog module for an arithmetic logic unit (ALU) that performs various operations based on a 4-bit input control signal. The ALU can pass inputs, increment, add, subtract, shift, and perform logical operations while also setting flags for negative (N) and zero (Z) results. The module outputs the result and carry flag (C) based on the specified operation.

Uploaded by

2017a.tech
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
33 views1 page

Module Alu

This document describes a Verilog module for an arithmetic logic unit (ALU) that performs various operations based on a 4-bit input control signal. The ALU can pass inputs, increment, add, subtract, shift, and perform logical operations while also setting flags for negative (N) and zero (Z) results. The module outputs the result and carry flag (C) based on the specified operation.

Uploaded by

2017a.tech
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
You are on page 1/ 1

`timescale 1ns / 1ps

module alu__(
input [3:0] R, S,
input [3:0] Alu_op,
output reg [3:0] Y,
output reg N, Z, C
);

always @(*) begin


case (Alu_op)
4'b0000: begin // pass S
C = 1'b0;
Y = S;
end
4'b0001: begin // pass R
C = 1'b0;
Y = R;
end
4'b0010: begin // increment S
{C, Y} = S + 1;
end
4'b0011: begin // add
{C, Y} = R + S;
end
4'b0100: begin // subtract
{C, Y} = R - S;
end
4'b0101: begin // right shift S (logical)
C = S[0];
Y = {1'b0, S[3:1]};
end
4'b0110: begin // left shift S (logical)
C = S[3];
Y = {S[2:0], 1'b0};
end
4'b0111: begin // logic AND
{C, Y} = {1'b0, R & S};
end
4'b1000: begin // logic OR
{C, Y} = {1'b0, R | S};
end
4'b1001: begin // logic XOR
{C, Y} = {1'b0, R ^ S};
end
default: begin // pass S for default
C = 1'b0;
Y = S;
end
endcase

// Set N and Z flags


N = Y[3];
Z = (Y == 4'b0) ? 1'b1 : 1'b0;
end

endmodule

You might also like