Microprocessors &
Microcontrollers
Lecture 5 & 6
31/01/2022- 1/02/2022
Classification of Instruction Set
• Data Transfer Instruction
• Arithmetic Instruction
• Logical Instruction
• Branching Instruction
• Control Instruction
Logical Instruction
CMP M
Operation A=A Compare M
Machine Cycle OP + MR
No. of bytes 1 byte
Flags S, AC and P reflect the result of
subtraction and CY and Z flag are
used to indicate the result of
comparison.
Addressing mode Indirect Addressing mode
T-states 4 +3
The result of comparison is indicated by setting the flags as follow:
If A > M : CY = 0 and Z =0
If A = M : Z = 1 and CY = 0
If A < M ; CY =1, Z = 0
Logical Instruction
Let A = 20 H, H = C0 H, L =02 H, at memory location C002= 10 H
is stored and the instruction CMP M is executed. Then after the
instruction is executed we get:
A=00100000 20 H
M(C002) = 0 0 0 1 0 0 0 0 10 H
__________________________
CY = 0, Z =0, P=0, S=0, AC=0
Logical Instruction
CPI Data
Operation A=A Compare M
Machine Cycle OP + MR
No. of bytes 2 byte
Flags S, AC and P reflect the result of
subtraction and CY and Z flag are
used to indicate the result of
comparison.
Addressing mode Immediate Addressing mode
T-states 4 + 3 =7
The result of comparison is indicated by setting the flags as follow:
If A > data : CY = 0 and Z =0
If A = data : Z = 1 and CY = 0
If A < data; CY =1, Z = 0
Logical Instruction
RLC
(Rotate Accumulator Left)
Operation Cy ----B7
Machine Cycle OP
No. of bytes 1 byte
Flags Only the CY flag is modified. Bit B7
is copied to the CY flag. No other
flags are modified.
Addressing mode Implied Addressing mode
T-states 4
A= 1F H, CY flag = 0and instruction RLC is executed; after execution A= 38
H
Logical Instruction
RRC
(Rotate Accumulator Right)
Operation CY{0} --- B{0}
Machine Cycle OP
No. of bytes 1 byte
Flags Only the CY flag is modified. No
other flags are modified.
Addressing mode Implied Addressing mode
T-states 4
A= 1C H, CY flag = 1 and instruction RRC is executed; after execution A=
0E H
Logical Instruction
RAL
(Rotate Accumulator Left through Carry)
Operation CY---B{0}
Machine Cycle OP
No. of bytes 1 byte
Flags Only the CY flag is modified. No
other flags are modified.
Addressing mode Implied Addressing mode
T-states 4
A= 1E H, CY flag = 1 and instruction RAL is executed; after execution A=
1D H and CY =0
Logical Instruction
RAR
(Rotate Accumulator Right through Carry)
Operation CY--- B{7}
Machine Cycle OP
No. of bytes 1 byte
Flags Only the CY flag is modified. No
other flags are modified.
Addressing mode Implied Addressing mode
T-states 4
A= 0E H, CY flag = 1 and instruction RAR is executed; after execution A=
87 H and CY =0
Branching Instruction
Branching Instruction
• Stack area is usually defined in RAM only.
• Stack is used to store information (data) temporarily.
• The location which has the most recent entry is called
as the top of the stack.
• When the information is written on the stack operation
is called PUSH.
• When the information is read from the stack, the
operation is called POP.
• Stack works on the principle of Last in First Out or First
in Last Out.
Stack Related Instructions
PUSH Rp
Push the contents of register pair on the stack
Operation SP--- SP -1
SP = higher order Rp
SP = SP -1
SP = Lower order Rp
Machine Cycle OP + MW + MW
No. of bytes 1 byte
Flags No flags are affected.
Addressing mode Register Addressing mode
T-states 6+3+3
Stack Related Instructions
This instruction is used to write 16-bit data on the stack.
When this instruction is executed:
1) The SP is decremented by 1 and the content of higher
order register of the specified register pair are copied
to the memory location pointed the stack pointer.
2) The SP is again decremented by 1 and the contents of
lower order of register pair are copied to memory
location pointed by the stack pointer.
The register pair can be BC, DE, HL and PSW.
Stack Related Instructions
Stack Related Instructions
POP Rp
POP off stack contents to register pair
Operation Lower order bte of Rp --- SP
SP = SP +1
Higher order byte of Rp SP
SP = SP +1
Machine Cycle OP + MR+ MR
No. of bytes 1 byte
Flags No flags are modified.
Addressing mode Register Addressing mode
T-states 6+3+3
Stack Related Instructions
Stack Related Instructions
SPHL
Operation SP=HL
Machine Cycle OP
No. of bytes 1 byte
Flags No flags are modified.
Addressing mode Implied Addressing mode
T-states 6
Stack Related Instructions
XTHL
(Exchange HL with top of stack)
Operation L - SP
H-(SP +1)
Machine Cycle OP + MR + MR+ MW + MW
No. of bytes 1 byte
Flags No flags are modified.
Addressing mode Implied Addressing mode
T-states 4+3+3+3+3
Stack Related Instructions
• LXI SP, data (16 bit)
• INX SP
Increments SP by 1
• DAD SP
Adds the content of SP with the content of HL
register pair
• DCX SP
• Decrements SP by 1
Branch Group
• Call Instructions
1. JMP address
2. Conditional JMP instructions
3. PCHL
• Call and return instructions
1. Call Address
2. Conditional call instructions
3. RET
4. Conditional RET instructions
• Restart instructions
1. RST N
Branch Group
JMP Address
Operation PC ---- Address
Machine Cycle OP + MR + MR
No. of bytes 3 byte
Flags No flags are modified.
Addressing mode Implied Addressing mode
T-states 4+3+3
Branch Group
Conditional JUMP instructions
Jcond Address
Operation If condition is true
PC ---- Address
Else, PC -- PC + 3
Machine Cycle OP + MR + MR (True condition)
OP + MR (False condition)
No. of bytes 3 byte
Flags No flags are modified.
Addressing mode Implied Addressing mode
T-states 4+3+3
Branch Group
Conditional JUMP instructions
Jcond Address
Instruction code Description Condition to JUMP
JZ JUMP if zero ZF =1
JNZ JUMP if not zero ZF = 0
JP JUMP if positive SF = 0
JM JUMP on minus SF=1
JPO JUMP id parity odd PF=0
JPE JUMP if parity even PF=1
JC JUMP if carry CF=1
JNC JUMP if no carry CF =0
Branch Group
PCHL
Operation PC < ----- HL
Machine Cycle OP
No. of bytes 1 byte
Flags No flags are modified.
Addressing mode Implied Addressing mode
T-states 6
Branch Group
CALL Address
Operation
Machine Cycle OP + MR + MR + MW + MW
No. of bytes 3 byte
Flags No flags are modified.
Addressing mode Implied Addressing mode
T-states 6 + 3+ 3+3+3
Branch Group
Conditional CALL instructions
Operation
Machine Cycle OP + MR + MR + MW + MW(true)
OP + MR(false)
No. of bytes 3 byte
Flags No flags are modified.
Addressing mode Implied Addressing mode
T-states 4+3+3+3+3
Branch Group
Conditional CALL instructions
Instruction code Description Condition to JUMP
CZ CALL on zero ZF =1
CNZ CALL if not zero ZF = 0
CP CALL if positive SF = 0
CM CALL on minus SF=1
CPO CALL if parity odd PF=0
CPE CALL if parity even PF=1
CC CALL if carry CF=1
CNC CALL if no carry CF =0
Branch Group
RET
Operation
Machine Cycle OP + MR + MR
No. of bytes 1 byte
Flags No flags are modified.
Addressing mode Implied Addressing mode
T-states 4+3+3
Branch Group
Conditional RET instructions
Operation
Machine Cycle OP + MR + MR ( TRUE)
OP ( FALSE)
No. of bytes 1 byte
Flags No flags are modified.
Addressing mode indirect Addressing mode
T-states 4+3+3
Control Instruction
Control Instruction
NOP
Operation PC --- PC +1
Machine Cycle OP
No. of bytes 1 byte
Flags No flags are modified.
Addressing mode implied Addressing mode
T-states 4
When this instruction is executed no operation is performed instead of that
instruction
Control Instruction
HLT
Operation PC --- PC +1
Machine Cycle OP + 1 T state
No. of bytes 1 byte
Flags No flags are modified.
Addressing mode implied Addressing mode
T-states 4+1
When this instruction is executed, microprocessor halts
Control Instruction
EI
Operation IE Flip flop ------ 1
Machine Cycle OP
No. of bytes 1 byte
Flags No flags are modified.
Addressing mode implied Addressing mode
T-states 4
When this instruction is executed, the interrupt enables flip flop is set so that all
the maskable interrupts
When the interrupt in acknowledged, the interrupt enable flip flop is reset
Control Instruction
DI
Operation IE Flip flop ------ 0
Machine Cycle OP
No. of bytes 1 byte
Flags No flags are modified.
Addressing mode implied Addressing mode
T-states 4
When this instruction is executed, the interrupt enables flip flop is reset so that
all the maskable interrupts are disabled
Apart from TRAP all the maskable interrupts can be disabled
Control Instruction
IN 8-bit address
Operation A------ 8-bit address
Machine Cycle OP + MR + IOR
No. of bytes 2 byte
Flags No flags are modified.
Addressing mode Direct Addressing mode
T-states 4 +3+3
Copy the data from input port address specified into the accumulator
Control Instruction
OUT 8-bit address
Operation 8-bit address ------- A
Machine Cycle OP + MR + IOW
No. of bytes 2 byte
Flags No flags are modified.
Addressing mode Direct Addressing mode
T-states 4 +3+3
Copy the content of accumulator to the output port whose address is specified
into the instruction
Hardware Interrupts
• TRAP
• RST 7.5
• RST 6.5
• RST 5.5
• INTR
Control Instruction
RST n
(n =0 to 7)
8085 microprocessor has 8 software interrupts
This instruction transfers the program control to the specified memory address.
Control Instruction
Assignment ---1
Q1 What do you mean by RIM & SIM instruction? Explain with bit pattern?
Q2 Explain in detail about the maskable and non-maskable interrupts?
Q3Here are some instructions
MVI A, 1D H
SIM
After SIM instruction is executed, which interrupts are masked?
Q4 What is the difference between hardware and software interrupts?
Q5 How is INTR interrupt used in 8085?
Example
• Add two hexadecimal numbers stored in
memory locations 2501 H and 2502 H. The
answer should be stored in 2503 H memory
location. The carry if any should be stored in
2504 H memory location.
• LXI H, 2501 H ; Loads the address of the first number in H-
L register pair.
• MVI C, 00 H ; Clears C-register for carry (most significant
bit).
• MOV A, M ; Saves the first number in accumulator.
• INX H ; Increments the H-L register pair.
• ADD M ; Adds the two numbers.
• JNC NEXT ; if no carry go to NEXT.
• INR C ; Else increment the content of C-register.
• NEXT STA 2503 H ; Stores the answer .
• MOV A, C ; Moves the contents of C register (carry
contents) to accumulator
• STA 2504 H ; Saves the contents of carry.
• HLT
Example
• Add two hexadecimal numbers stored in
memory locations 2501 H and 2502 H. The
answer should be stored in 2503 H memory
location. The carry if any should be stored in
2504 H memory location.
• LXI H, 2501 H ;Loads the address of the first number in H-L
register pair.
• MOV A, M ;Saves the first number in accumulator.
• INX H ;Increments the H-L register pair.
• CMP M ;compares the two numbers.
• JC NEXT ;if carry smaller number is in accumulator go to NEXT.
• MOV A, M ;If no carry then move the smaller number to
accumulator.
• NEXT STA 2503 H ;Stores the smaller number in 2503 memory
location .
• HLT
Thank You
