32 Bit Counter
Module
module counter(
input clk,rst,udb,
output [31:0] count);
reg [31:0] count;
always @(posedge clk) begin
if(rst==1)
count=32'd0;//reset
else
case(udb)
1'b0:count=count+1;//up count
1'b1:count=count-1;//down count
default:count =count;// no change
endcase
end
endmodule
Test Bench
module counter_tb;
reg clk,rst,udb;
wire [31:0] count;
counter HA1 (.clk(clk),.rst(rst),.udb(udb),.count(count));
initial begin
clk=1'b0;
rst=1'b1;
udb = 1'b0;
#30 rst = 1'b0;
#50 udb = 1'b1;
#80 udb = 1'b0;
#80 rst = 1'b1;
#30 rst = 1'b0;
end
always #10 clk=~clk;
endmodule
4-Bit ADDER
Module
module adder4bit(
input [3:0] A,B,
input Cin,
output [3:0] Sum,
output Carry);
reg [3:0] Sum;
reg Carry;
always @(*) begin
{Carry,Sum} = A + B + Cin;
end
endmodule
Test Bench
module adder_tb;
reg [3:0] a,b;
reg cin;
wire [3:0] sum;
wire carry;
adder4bit inst1 (.A(a),.B(b),.Cin(cin),.Sum(sum),.Carry(carry));
initial begin
a=4'd1;b=4'd6;cin=1'd0;
#40 a=4'd10;b=4'd7;cin=1'd0;
#30 a=4'd15;b=4'd12;cin=1'd1;
#50 a=4'd15;b=4'd15;cin=1'd1;
end
endmodule
UART
// This file contains the UART Receiver. This receiver is able to
// receive 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When receive is complete o_rx_dv will be
// driven high for one clock cycle.
//
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 10 MHz Clock, 115200 baud UART
// (10000000)/(115200) = 87
`timescale 1ns/10ps
Module
module uart_rx
#(parameter CLKS_PER_BIT=87)
(
input i_Clock,
input i_Rx_Serial,
output o_Rx_DV,
output [7:0] o_Rx_Byte
);
parameter s_IDLE = 3'b000;
parameter s_RX_START_BIT = 3'b001;
parameter s_RX_DATA_BITS = 3'b010;
parameter s_RX_STOP_BIT = 3'b011;
parameter s_CLEANUP = 3'b100;
reg r_Rx_Data_R = 1'b1;
reg r_Rx_Data = 1'b1;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0; //8 bits total
reg [7:0] r_Rx_Byte = 0;
reg r_Rx_DV = 0;
reg [2:0] r_SM_Main = 0;
// Purpose: Double-register the incoming data.
// This allows it to be used in the UART RX Clock Domain.
// (It removes problems caused by metastability)
always @(posedge i_Clock)
begin
r_Rx_Data_R <= i_Rx_Serial;
r_Rx_Data <= r_Rx_Data_R;
end
// Purpose: Control RX state machine
always @(posedge i_Clock)
begin
case (r_SM_Main)
s_IDLE :
begin
r_Rx_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (r_Rx_Data == 1'b0) // Start bit detected
r_SM_Main <= s_RX_START_BIT;
else
r_SM_Main <= s_IDLE;
end
// Check middle of start bit to make sure it's still low
s_RX_START_BIT :
begin
if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
begin
if (r_Rx_Data == 1'b0)
begin
r_Clock_Count <= 0; // reset counter, found the
middle
r_SM_Main <= s_RX_DATA_BITS;
end
else
r_SM_Main <= s_IDLE;
end
else
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_START_BIT;
end
end // case: s_RX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles to sample serial data
s_RX_DATA_BITS :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
// Check if we have received all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_RX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= s_RX_STOP_BIT;
end
end
end // case: s_RX_DATA_BITS
// Receive Stop bit. Stop bit = 1
s_RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_STOP_BIT;
end
else
begin
r_Rx_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= s_CLEANUP;
end
end // case: s_RX_STOP_BIT
// Stay here 1 clock
s_CLEANUP :
begin
r_SM_Main <= s_IDLE;
r_Rx_DV <= 1'b0;
end
default :
r_SM_Main <= s_IDLE;
endcase
end
assign o_Rx_DV = r_Rx_DV;
assign o_Rx_Byte = r_Rx_Byte;
endmodule // uart_rx
UART Test Bench
// This testbench will exercise both the UART Tx and Rx.
// It sends out byte 0xAB over the transmitter
// It then exercises the receive by receiving byte 0x3F
`timescale 1ns/10ps
//`include "uart_tx.v"
//`include "uart_rx.v"
module uart_tb ();
// Testbench uses a 10 MHz clock
// Want to interface to 115200 baud UART
// 10000000 / 115200 = 87 Clocks Per Bit.
parameter c_CLOCK_PERIOD_NS = 100;
parameter c_CLKS_PER_BIT = 87;
parameter c_BIT_PERIOD = 8600;
reg r_Clock = 0;
reg r_Tx_DV = 0;
wire w_Tx_Done;
reg [7:0] r_Tx_Byte = 0;
reg r_Rx_Serial = 1;
wire [7:0] w_Rx_Byte;
// Takes in input byte and serializes it
task UART_WRITE_BYTE;
input [7:0] i_Data;
integer ii;
begin
// Send Start Bit
r_Rx_Serial <= 1'b0;
#(c_BIT_PERIOD);
#1000;
// Send Data Byte
for (ii=0; ii<8; ii=ii+1)
begin
r_Rx_Serial <= i_Data[ii];
#(c_BIT_PERIOD);
end
// Send Stop Bit
r_Rx_Serial <= 1'b1;
#(c_BIT_PERIOD);
end
endtask // UART_WRITE_BYTE
uart_rx #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_INST
(.i_Clock(r_Clock),
.i_Rx_Serial(r_Rx_Serial),
.o_Rx_DV(),
.o_Rx_Byte(w_Rx_Byte)
);
uart_tx #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_INST
(.i_Clock(r_Clock),
.i_Tx_DV(r_Tx_DV),
.i_Tx_Byte(r_Tx_Byte),
.o_Tx_Active(),
.o_Tx_Serial(),
.o_Tx_Done(w_Tx_Done)
);
always
#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;
// Main Testing:
initial
begin
// Tell UART to send a command (exercise Tx)
@(posedge r_Clock);
@(posedge r_Clock);
r_Tx_DV <= 1'b1;
r_Tx_Byte <= 8'hAB;
@(posedge r_Clock);
r_Tx_DV <= 1'b0;
@(posedge w_Tx_Done);
// Send a command to the UART (exercise Rx)
@(posedge r_Clock);
UART_WRITE_BYTE(8'h3F);
@(posedge r_Clock);
// Check that the correct command was received
if (w_Rx_Byte == 8'h3F)
begin
$display("Test Passed - Correct Byte Received");
$finish;
end
else
begin
$display("Test Failed - Incorrect Byte Received");
$finish;
end
end
endmodule
32-Bit ALU
Module
module alu_if(
input [31:0] P,Q,
input [2:0]sel,
output reg [63:0]Acc);
always@(sel or P or Q) begin
Acc = 64'd0;
if(sel == 3'd0)
Acc = P + Q;
else if(sel == 3'd1)
Acc = P - Q;
else if(sel == 3'd2)
Acc = P * Q;
else if(sel == 3'd3)
Acc = P / Q;
else if(sel == 3'd4)
Acc = P | Q;
else if(sel == 3'd5)
Acc = P & Q;
else if(sel == 3'd6)
Acc = P ^ Q;
else if(sel == 3'd7)
Acc = ~P;
end
endmodule
Test Bench
module alu_tb;
reg [31:0] p,q;
reg [2:0]sel;
wire [63:0]acc_case;
wire [63:0]acc_if;
alu_case inst1(.P(p),.Q(q),.sel(sel),.Acc(acc_case));
alu_if inst2(.P(p),.Q(q),.sel(sel),.Acc(acc_if));
initial begin
sel=3'd0;p=32'd14;q=32'd18;
#20 sel=3'd1;
#20 sel=3'd2;
#20 sel=3'd3;
#20 sel=3'd4;
#20 sel=3'd5;
#20 sel=3'd6;
#20 sel=3'd7;
end
endmodule
FLIP FLOPS
Module
module dFlip(d,clk,q,qb);
input d,clk;
output q,qb;
reg q,qb;
always @(posedge clk)
begin
q = d;
qb = ~q;
end
endmodule
Test Bench
module dflip_tb;
// Inputs
reg d;
reg clk;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
dFlip uut (
.d(d),
.clk(clk),
.q(q),
.qb(qb)
);
initial begin
// Initialize Inputs
d = 0;
clk = 0;
end
always #10 clk = ~clk;
initial begin
#10 d = 1;
#20 d = 0;
#40 d = 1;
end
endmodule
Module
module sr_flip(sr,q,qb,clk);
input [1:0] sr;
output q,qb;
reg q,qb;
input clk;
initial q = 0;
always @(posedge clk) begin
case(sr)
2'b00 : q = q;
2'b01 : q = 1'b0;
2'b10 : q = 1'b1;
default : q = q;
endcase
qb = ~q;
end
endmodule
Test Bench
module sr_tb;
// Inputs
reg [1:0] sr;
reg clk;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
sr_flip uut (
.sr(sr),
.q(q),
.qb(qb),
.clk(clk)
);
initial begin
// Initialize Inputs
sr = 2'b00;
clk = 0;
end
always #10 clk = ~clk;
initial begin
// Wait 100 ns for global reset to finish
#40 sr = 2'b01;
#40 sr = 2'b10;
#40 sr = 2'b00;
#40 sr = 2'b01;
// Add stimulus here
end
endmodule
Module
module jk_flip(j,k,clk,q,qb);
input j,k,clk;
output q,qb;
reg q,qb;
// wire clk_br,qm,qmb,s1,r1;
//
// not uut1(clk,clk_br);
// sr_flip uut2 (.sr({s1,r1}),.q(qm),.qb(qmb),.clk(clk));
// sr_flip uut3 (.sr({qm,qmb}),.q(q),.qb(qb),.clk(clk_br));
// and uut4(j,qb,s1);
// and uut5(k,q,r1);
initial begin
q = 1'b0;
qb = 1'b1;
end
always @(posedge clk) begin
case({j,k})
2'b00 : q = q;
2'b01 : q = 1'b0;
2'b10 : q = 1'b1;
2'b11 : q = qb;
endcase
qb = ~q;
end
endmodule
Test Bench
module jk_tb;
// Inputs
reg j;
reg k;
reg clk;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
jk_flip uut (
.j(j),
.k(k),
.clk(clk),
.q(q),
.qb(qb)
);
initial begin
// Initialize Inputs
j = 0;
k = 0;
clk = 0;
end
always #10 clk = ~clk;
initial begin
#30 {j,k} = 2'b01;
#30 {j,k} = 2'b00;
#30 {j,k} = 2'b10;
#30 {j,k} = 2'b11;
end
endmodule
