25AA1024/25LC1024

1 Mbit SPI Bus Serial EEPROM

Device Selection Table
Part Number VCC Range Page Size Temp. Ranges Packages
25LC1024 2.5-5.5V 256 Byte I,E P, SM, MF
25AA1024 1.8-5.5V 256 Byte I P, SM, MF

Features: Description:
• 20 MHz max. Clock Speed The Microchip Technology Inc. 25AA1024/25LC1024
• Byte and Page-level Write Operations: (25XX1024*) is a 1024 Kbit serial EEPROM memory
- 256 byte page with byte-level and page-level serial EEPROM func-
- 6 ms max. write cycle time tions. It also features Page, Sector and Chip erase
- No page or sector erase required functions typically associated with Flash-based prod-
• Low-Power CMOS Technology: ucts. These functions are not required for byte or page
- Max. Write current: 5 mA at 5.5V, 20 MHz write operations. The memory is accessed via a simple
- Read current: 7 mA at 5.5V, 20 MHz Serial Peripheral Interface (SPI) compatible serial bus.
- Standby current: 1μA at 2.5V The bus signals required are a clock input (SCK) plus
(Deep power-down) separate data in (SI) and data out (SO) lines. Access to
• Electronic Signature for Device ID the device is controlled by a Chip Select (CS) input.
• Self-Timed Erase and Write Cycles: Communication to the device can be paused via the
- Page Erase (6 ms max.) hold pin (HOLD). While the device is paused, transi-
- Sector Erase (10 ms max.) tions on its inputs will be ignored, with the exception of
- Chip Erase (10 ms max.) Chip Select, allowing the host to service higher priority
• Sector Write Protection (32K byte/sector): interrupts.
- Protect none, 1/4, 1/2 or all of array
The 25XX1024 is available in standard packages
• Built-In Write Protection: including 8-lead PDIP and SOIJ, and advanced 8-lead
- Power-on/off data protection circuitry DFN package. All devices are Pb-free.
- Write enable latch
- Write-protect pin
• High Reliability:
Package Types (not to scale)
- Endurance: 1M erase/write cycles
• Temperature Ranges Supported: DFN PDIP/SOIJ
(MF) (P, SM)
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C CS 1 8 VCC
CS 1 8 VCC
25LC1024

25LC1024

• Pb-free packages available SO 2 7 HOLD SO 2 7 HOLD

WP 3 6 SCK WP 3 6 SCK
Pin Function Table VSS 4 5 SI VSS 4 5 SI

Name Function

CS Chip Select Input

SO Serial Data Output
WP Write-Protect
VSS Ground
SI Serial Data Input
SCK Serial Clock Input
HOLD Hold Input
VCC Supply Voltage *25XX1024 is used in this document as a generic part number
for the 25AA1024, 25LC1024 devices.

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 1

25AA1024/25LC1024
1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias ...............................................................................................................-40°C to 125°C
ESD protection on all pins ..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

Industrial (I): TA = -0°C to +85°C VCC = 1.8V to 5.5V
DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V
Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V

Param.
Sym. Characteristic Min. Max. Units Test Conditions
No.
D001 VIH1 High-level input .7 VCC VCC +1 V
voltage
D002 VIL1 Low-level input -0.3 0.3 VCC V VCC ≥ 2.7V
D003 VIL2 voltage -0.3 0.2 VCC V VCC < 2.7V
D004 VOL Low-level output — 0.4 V IOL = 2.1 mA
D005 VOL voltage — 0.2 V IOL = 1.0 mA, VCC < 2.5V
D006 VOH High-level output VCC -0.5 — V IOH = -400 μA
voltage
D007 ILI Input leakage current — ±1 μA CS = VCC, VIN = VSS TO VCC
D008 ILO Output leakage — ±1 μA CS = VCC, VOUT = VSS TO VCC
current
D009 CINT Internal capacitance — 7 pF TA = 25°C, CLK = 1.0 MHz,
(all inputs and VCC = 5.0V (Note)
outputs)
D010 ICC Read — 10 mA VCC = 5.5V; FCLK = 20.0 MHz;
— SO = Open
Operating current 5 mA VCC = 2.5V; FCLK = 10.0 MHz;
SO = Open
D011 ICC Write — 7 mA VCC = 5.5V
— 5 mA VCC = 2.5V
D012 ICCS — 20 μA CS = VCC = 5.5V, Inputs tied to VCC or
Standby current — VSS, 125°C
12 μA CS = VCC = 5.5V, Inputs tied to VCC or
VSS, 85°C
D13 ICCSPD Deep power-down — 1 μA CS = VCC = 2.5V, Inputs tied to VCC or
current VSS, 85°C
— 2 μA CS = VCC = 5.5V, Inputs tied to VCC or
VSS, 125°C
Note: This parameter is periodically sampled and not 100% tested.

DS21836D-page 2 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
TABLE 1-2: AC CHARACTERISTICS
Industrial (I): TA = -0°C to +85°C VCC = 1.8V to 5.5V
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V
Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V

Param.
Sym. Characteristic Min. Max. Units Conditions
No.
1 FCLK Clock frequency — 20 MHz 4.5 ≤ VCC ≤ 5.5
— 10 MHz 2.5 ≤ VCC < 4.5
— 2 MHz 1.8 ≤ VCC < 2.5
2 TCSS CS setup time 25 — ns 4.5 ≤ VCC ≤ 5.5
50 — ns 2.5 ≤ VCC < 4.5
250 — ns 1.8 ≤ VCC < 2.5
3 TCSH CS hold time 50 — ns 4.5 ≤ VCC ≤ 5.5
100 — ns 2.5 ≤ VCC < 4.5
500 — ns 1.8 ≤ VCC < 2.5
(Note 3)
4 TCSD CS disable time 50 — ns
5 Tsu Data setup time 5 — ns 4.5 ≤ VCC ≤ 5.5
10 — ns 2.5 ≤ VCC < 4.5
50 — ns 1.8 ≤ VCC < 2.5
6 THD Data hold time 10 — ns 4.5 ≤ VCC ≤ 5.5
20 — ns 2.5 ≤ VCC < 4.5
100 — ns 1.8 ≤ VCC < 2.5
7 TR CLK rise time — 20 ns (Note 1)
8 TF CLK fall time — 20 ns (Note 1)
9 THI Clock high time 25 — ns 4.5 ≤ VCC ≤ 5.5
50 — ns 2.5 ≤ VCC < 4.5
250 — ns 1.8 ≤ VCC < 2.5
10 TLO Clock low time 25 — ns 4.5 ≤ VCC ≤ 5.5
50 — ns 2.5 ≤ VCC < 4.5
250 ns 1.8 ≤ VCC < 2.5
11 TCLD Clock delay time 50 — ns
12 TCLE Clock enable time 50 — ns
13 TV Output valid from clock low — 25 ns 4.5 ≤ VCC ≤ 5.5
— 50 ns 2.8 ≤ VCC < 4.5
— 250 ns 1.8 ≤ VCC < 2.5
14 THO Output hold time 0 — ns (Note 1)
15 TDIS Output disable time — 25 ns 4.5 ≤ VCC ≤ 5.5
— 50 ns 2.5 ≤ VCC < 4.5
— 250 ns 1.8 ≤ VCC < 2.5
(Note 1)
16 THS HOLD setup time 10 — ns 4.5 ≤ VCC ≤ 5.5
20 — ns 2.5 ≤ VCC < 4.5
100 — ns 1.8 ≤ VCC < 2.5
17 THH HOLD hold time 10 — ns 4.5 ≤ VCC ≤ 5.5
20 — ns 2.5 ≤ VCC < 4.5
100 — ns 1.8 ≤ VCC < 2.5
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but established by characterization and qualification. For endurance
estimates in a specific application, please consult the Total Endurance™ Model which can be obtained
from our web site at www.microchip.com.
3: Includes THI time.

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 3

25AA1024/25LC1024
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
Industrial (I): TA = -0°C to +85°C VCC = 1.8V to 5.5V
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V
Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V

Param.
Sym. Characteristic Min. Max. Units Conditions
No.
18 THZ HOLD low to output 15 — ns 4.5 ≤ VCC ≤ 5.5
High-Z 30 — ns 2.5 ≤ VCC < 4.5
150 — ns 1.8 ≤ VCC < 2.5
(Note 1)
19 THV HOLD high to output valid 15 — ns 4.5 ≤ VCC ≤ 5.5
30 — ns 2.5 ≤ VCC < 4.5
150 — ns 1.8 ≤ VCC < 2.5
20 TREL CS High to Standby mode — 100 μs VCC = 1.8V to 5.5V
21 TPD CS High to Deep power- — 100 μs VCC = 1.8V to 5.5V
down
22 TCE Chip erase cycle time — 10 ms VCC = 1.8V to 5.5V
23 TSE Sector erase cycle time — 10 ms VCC = 1.8V to 5.5V
24 TWC Internal write cycle time — 6 ms Byte or Page mode and Page
Erase
25 — Endurance 1M — E/W (Note 2) Per Page
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but established by characterization and qualification. For endurance
estimates in a specific application, please consult the Total Endurance™ Model which can be obtained
from our web site at www.microchip.com.
3: Includes THI time.

TABLE 1-3: AC TEST CONDITIONS

AC Waveform:
VLO = 0.2V —
VHI = VCC - 0.2V (Note 1)
VHI = 4.0V (Note 2)
CL = 30 pF —
Timing Measurement Reference Level
Input 0.5 VCC
Output 0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V

DS21836D-page 4 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
FIGURE 1-1: HOLD TIMING
CS
17 17
16 16

SCK
18 19
High-Impedance
SO n+2 n+1 n n n-1

Don’t Care 5
SI n+2 n+1 n n n-1

HOLD

FIGURE 1-2: SERIAL INPUT TIMING

CS 12
2 11
7
Mode 1,1 8 3

SCK Mode 0,0

5 6

SI MSB in LSB in

High-Impedance
SO

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

9 10 3
Mode 1,1
SCK Mode 0,0
13
14 15

SO MSB out LSB out

Don’t Care
SI

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 5

25AA1024/25LC1024
2.0 FUNCTIONAL DESCRIPTION BLOCK DIAGRAM
STATUS
2.1 Principles of Operation Register
HV Generator

The 25XX1024 is a 131,072 byte Serial EEPROM

designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
EEPROM
microcontrollers. It may also interface with microcon- I/O Control Memory X
Control Array
trollers that do not have a built-in SPI port by using Logic
Logic Dec
discrete I/O lines programmed properly in firmware to
match the SPI protocol.
Page Latches
The 25XX1024 contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must SI
be low and the HOLD pin must be high for the entire SO Y Decoder
operation. CS
Table 2-1 contains a list of the possible instruction SCK
bytes and format for device operation. All instructions, HOLD Sense Amp.
addresses and data are transferred MSB first, LSB last. R/W Control
WP
Data (SI) is sampled on the first rising edge of SCK VCC
VSS
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX1024 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WREN 0000 0110 Set the write enable latch (enable write operations)
WRDI 0000 0100 Reset the write enable latch (disable write operations)
RDSR 0000 0101 Read STATUS register
WRSR 0000 0001 Write STATUS register
PE 0100 0010 Page Erase – erase one page in memory array
SE 1101 1000 Sector Erase – erase one sector in memory array
CE 1100 0111 Chip Erase – erase all sectors in memory array
RDID 1010 1011 Release from Deep power-down and read electronic signature
DPD 1011 1001 Deep Power-Down mode

DS21836D-page 6 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
Read Sequence The data stored in the memory at the next address can
be read sequentially by continuing to provide clock
The device is selected by pulling CS low. The 8-bit pulses. The internal Address Pointer is automatically
READ instruction is transmitted to the 25XX1024 incremented to the next higher address after each byte
followed by the 24-bit address, with seven MSBs of the of data is shifted out. When the highest address is
address being “don’t care” bits. After the correct READ reached (1FFFFh), the address counter rolls over to
instruction and address are sent, the data stored in the address, 00000h, allowing the read cycle to be contin-
memory at the selected address is shifted out on the ued indefinitely. The read operation is terminated by
SO pin. raising the CS pin (Figure 2-1).

FIGURE 2-1: READ SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39
SCK

Instruction 24-bit Address

SI 0 0 0 0 0 0 1 1 23 22 21 20 2 1 0

Data Out
High-Impedance
SO 7 6 5 4 3 2 1 0

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 7

25AA1024/25LC1024
2.2 Write Sequence the data in the rest of the page is refreshed along with
the data bytes being written. For this reason,
Prior to any attempt to write data to the 25XX1024, the endurance is specified per page.
write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low Note: Page write operations are limited to writing
and then clocking out the proper instruction into the bytes within a single physical page,
25XX1024. After all eight bits of the instruction are regardless of the number of bytes
transmitted, the CS must be brought high to set the actually being written. Physical page
write enable latch. If the write operation is initiated boundaries start at addresses that are
immediately after the WREN instruction without CS integer multiples of the page buffer size (or
being brought high, the data will not be written to the ‘page size’), and end at addresses that are
array because the write enable latch will not have been integer multiples of page size – 1. If a
properly set. Page Write command attempts to write
across a physical page boundary, the
A write sequence includes an automatic, self timed
result is that the data wraps around to the
erase cycle. It is not required to erase any portion of the
beginning of the current page (overwriting
memory prior to issuing a Write command.
data previously stored there), instead of
Once the write enable latch is set, the user may being written to the next page as might be
proceed by setting the CS low, issuing a WRITE instruc- expected. It is therefore necessary for the
tion, followed by the 24-bit address, with seven MSBs application software to prevent page write
of the address being “don’t care” bits, and then the data operations that would attempt to cross a
to be written. Up to 256 bytes of data can be sent to the page boundary.
device before a write cycle is necessary. The only
For the data to be actually written to the array, the CS
restriction is that all of the bytes must reside in the
must be brought high after the Least Significant bit (D0)
same page. When doing a write of less than 256 bytes
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 2-2 and Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.

FIGURE 2-2: BYTE WRITE SEQUENCE

CS
Twc
0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39
SCK
Instruction 24-bit Address Data Byte
SI 0 0 0 0 0 0 1 0 23 22 21 20 2 1 0 7 6 5 4 3 2 1 0

High-Impedance
SO

DS21836D-page 8 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
FIGURE 2-3: PAGE WRITE SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39
SCK
Instruction 24-bit Address Data Byte 1
SI 0 0 0 0 0 0 1 0 23 22 21 20 2 1 0 7 6 5 4 3 2 1 0

CS

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
Data Byte 2 Data Byte 3 Data Byte n (256 max)
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 9

25AA1024/25LC1024
2.3 Write Enable (WREN) and Write The following is a list of conditions under which the
Disable (WRDI) write enable latch will be reset:
• Power-up
The 25XX1024 contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix. • WRDI instruction successfully executed
This latch must be set before any write operation will be • WRSR instruction successfully executed
completed internally. The WREN instruction will set the • WRITE instruction successfully executed
latch, and the WRDI will reset the latch. • PE instruction successfully executed
• SE instruction successfully executed
• CE instruction successfully executed

FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)

CS

0 1 2 3 4 5 6 7
SCK

SI 0 0 0 0 0 1 1 0

High-Impedance
SO

FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)

CS

0 1 2 3 4 5 6 7
SCK

SI 0 0 0 0 0 1 10 0

High-Impedance
SO

DS21836D-page 10 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
2.4 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status
(RDSR) of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
The Read Status Register instruction (RDSR) provides ‘0’, the latch prohibits writes to the array. The state of
access to the STATUS register. The STATUS register this bit can always be updated via the WREN or WRDI
may be read at any time, even during a write cycle. The commands regardless of the state of write protection
STATUS register is formatted as follows: on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
TABLE 2-2: STATUS REGISTER The Block Protection (BP0 and BP1) bits indicate
7 6 5 4 3 2 1 0 which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
W/R – – – W/R W/R R R
bits are nonvolatile and are shown in Table 2-3.
WPEN X X X BP1 BP0 WEL WIP
See Figure 2-6 for the RDSR timing sequence.
W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the
25XX1024 is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.

FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCK

Instruction

SI 0 0 0 0 0 1 0 1

Data from STATUS register

High-Impedance
SO 7 6 5 4 3 2 1 0

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 11

25AA1024/25LC1024
2.5 Write Status Register Instruction The Write-Protect Enable (WPEN) bit is a nonvolatile
(WRSR) bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
The Write Status Register instruction (WRSR) allows the (WPEN) bit in the STATUS register control the
user to write to the nonvolatile bits in the STATUS programmable hardware write-protect feature. Hard-
register as shown in Table 2-2. The user is able to ware write protection is enabled when WP pin is low
select one of four levels of protection for the array by and the WPEN bit is high. Hardware write protection is
writing to the appropriate bits in the STATUS register. disabled when either the WP pin is high or the WPEN
The array is divided up into four segments. The user bit is low. When the chip is hardware write-protected,
has the ability to write-protect none, one, two, or all four only writes to nonvolatile bits in the STATUS register
of the segments of the array. The partitioning is are disabled. See Table 2-4 for a matrix of functionality
controlled as shown in Table 2-3. on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.

TABLE 2-3: ARRAY PROTECTION

Array Addresses Array Addresses
BP1 BP0
Write-Protected Unprotected
0 0 none All (Sectors 0, 1, 2 & 3)
(00000h-1FFFFh)
0 1 Upper 1/4 (Sector 3) Lower 3/4 (Sectors 0, 1 & 2)
(18000h-1FFFFh) (00000h-17FFFh)
1 0 Upper 1/2 (Sectors 2 & 3) Lower 1/2 (Sectors 0 & 1)
(10000h-1FFFFh) (00000h-0FFFFh)
1 1 All (Sectors 0, 1, 2 & 3) none
(00000h-1FFFFh)

FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCK

Instruction Data to STATUS register

SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0

High-Impedance
SO

DS21836D-page 12 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
2.6 Data Protection 2.7 Power-On State
The following protection has been implemented to The 25XX1024 powers on in the following state:
prevent inadvertent writes to the array: • The device is in low-power Standby mode
• The write enable latch is reset on power-up (CS = 1)
• A write enable instruction must be issued to set • The write enable latch is reset
the write enable latch • SO is in high-impedance state
• After a byte write, page write or STATUS register • A high-to-low-level transition on CS is required to
write, the write enable latch is reset enter active state
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued

TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX

WEL WPEN WP
Protected Blocks Unprotected Blocks STATUS Register
(SR bit 1) (SR bit 7) (pin 3)
0 x x Protected Protected Protected
1 0 x Protected Writable Writable
1 1 0 (low) Protected Writable Protected
1 1 1 (high) Protected Writable Writable
x = don’t care

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 13

25AA1024/25LC1024
2.8 PAGE ERASE
The Page Erase function will erase all bits (FFh) inside CS must then be driven high after the last bit if the
the given page. A Write Enable (WREN) instruction address or the Page Erase will not execute. Once the
must be given prior to attempting a Page Erase. This CS is driven high, the self-timed Page Erase cycle is
is done by setting CS low and then clocking out the started. The WIP bit in the STATUS register can be
proper instruction into the 25XX1024. After all eight read to determine when the Page Erase cycle is
bits of the instruction are transmitted, the CS must be complete.
brought high to set the write enable latch. If a Page Erase function is given to an address that
The Page Erase function is entered by driving CS low, has been protected by the Block Protect bits (BP0,
followed by the instruction code (Figure 2-8), and BP1) then the sequence will be aborted and no erase
three address bytes. Any address inside the page to will occur.
be erased is a valid address.

FIGURE 2-8: PAGE ERASE SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 29 30 31
SCK

Instruction 24-bit Address

SI 0 1 0 0 0 0 1 0 23 22 21 20 2 1 0

High-Impedance
SO

DS21836D-page 14 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
2.9 SECTOR ERASE
The Sector Erase function will erase all bits (FFh) CS must then be driven high after the last bit if the
inside the given sector. A Write Enable (WREN) instruc- address or the Sector Erase will not execute. Once the
tion must be given prior to attempting a Sector Erase. CS is driven high, the self-timed Sector Erase cycle is
This is done by setting CS low and then clocking out started. The WIP bit in the STATUS register can be
the proper instruction into the 25XX1024. After all read to determine when the Sector Erase cycle is
eight bits of the instruction are transmitted, the CS complete.
must be brought high to set the write enable latch. If a SECTOR ERASE instruction is given to an address
The Sector Erase function is entered by driving CS that has been protected by the Block Protect bits (BP0,
low, followed by the instruction code (Figure 2-9), and BP1) then the sequence will be aborted and no erase
three address bytes. Any address inside the sector to will occur.
be erased is a valid address. See Table 2-3 for Sector Addressing.

FIGURE 2-9: SECTOR ERASE SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 29 30 31
SCK

Instruction 24-bit Address

SI 1 1 0 1 1 0 0 0 23 22 21 20 2 1 0

High-Impedance
SO

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 15

25AA1024/25LC1024
2.10 CHIP ERASE
The Chip Erase function will erase all bits (FFh) in the The CS pin must be driven high after the eighth bit of
array. A Write Enable (WREN) instruction must be given the instruction code has been given or the Chip Erase
prior to executing a Chip Erase. This is done by setting function will not be executed. Once the CS pin is
CS low and then clocking out the proper instruction driven high, the self-timed Chip Erase function begins.
into the 25XX1024. After all eight bits of the instruction While the device is executing the Chip Erase function
are transmitted, the CS must be brought high to set the WIP bit in the STATUS register can be read to
the write enable latch. determine when the Chip Erase function is complete.
The Chip Erase function is entered by driving the CS The Chip Erase function is ignored if either of the
low, followed by the instruction code (Figure 2-10) Block Protect bits (BP0, BP1) are not 0, meaning ¼,
onto the SI line. ½, or all of the array is protected.

FIGURE 2-10: CHIP ERASE SEQUENCE

CS

0 1 2 3 4 5 6 7
SCK

SI 1 1 0 0 0 1 1 1

High-Impedance
SO

DS21836D-page 16 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
2.11 DEEP POWER-DOWN MODE
Deep Power-Down mode of the 25XX1024 is its All instructions given during Deep Power-Down mode
lowest power consumption state. The device will not are ignored except the Read Electronic Signature
respond to any of the Read or Write commands while Command (RDID). The RDID command will release
in Deep Power-Down mode, and therefore it can be the device from Deep power-down and outputs the
used as an additional software write protection feature. electronic signature on the SO pin, and then returns
The Deep Power-Down mode is entered by driving CS the device to Standby mode after delay (TREL)
low, followed by the instruction code (Figure 2-11) onto Deep Power-Down mode automatically releases at
the SI line, followed by driving CS high. device power-down. Once power is restored to the
If the CS pin is not driven high after the eighth bit of the device, it will power-up in the Standby mode.
instruction code has been given, the device will not
execute Deep power-down. Once the CS line is driven
high, there is a delay (TDP) before the current settles
to its lowest consumption.

FIGURE 2-11: DEEP POWER-DOWN SEQUENCE

CS

0 1 2 3 4 5 6 7
SCK

SI 1 0 1 1 1 0 0 1

High-Impedance
SO

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 17

25AA1024/25LC1024
2.12 RELEASE FROM DEEP POWER- Release from Deep Power-Down mode and Read
DOWN AND READ ELECTRONIC Electronic Signature is entered by driving CS low,
followed by the RDID instruction code (Figure 2-12)
SIGNATURE
and then a dummy address of 24 bits (A23-A0). After
Once the device has entered Deep Power-Down the last bit of the dummy address is clocked in, the
mode all instructions are ignored except the release 8-bit Electronic signature is clocked out on the SO
from Deep Power-down and Read Electronic Signa- pin.
ture command. This command can also be used when After the signature has been read out at least once,
the device is not in Deep Power-down, to read the the sequence can be terminated by driving CS high.
electronic signature out on the SO pin unless another The device will then return to Standby mode and will
command is being executed such as Erase, Program wait to be selected so it can be given new instructions.
or Write STATUS register. If additional clock cycles are sent after the electronic
signature has been read once, it will continue to output
the signature on the SO line until the sequence is
terminated.

FIGURE 2-12: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE

CS

0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39
SCK

Instruction 24-bit Address

SI 1 0 1 0 1 0 1 1 23 22 21 20 2 1 0

High-Impedance Electronic Signature Out

SO 7 6 5 4 3 2 1 0
0 0 1 0 1 0 0 1
Manufacturers ID 0x29

Driving CS high after the 8-bit RDID command, but before the Electronic Signature has been transmitted, will still
ensure the device will be taken out of Deep Power-Down mode. However, there is a delay TREL that occurs before the
device returns to Standby mode (ICCS), as shown in Figure 2-13.

FIGURE 2-13: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE

CS

0 1 2 3 4 5 6 7 TREL
SCK

Instruction
SI 1 0 1 0 1 0 1 1

High-Impedance
SO

DS21836D-page 18 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
3.0 PIN DESCRIPTIONS The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
The descriptions of the pins are listed in Table 3-1. install the 25XX1024 in a system with WP pin grounded
and still be able to write to the STATUS register. The
TABLE 3-1: PIN FUNCTION TABLE WP pin functions will be enabled when the WPEN bit is
set high.
Name Pin Number Function
3.4 Serial Input (SI)
CS 1 Chip Select Input
The SI pin is used to transfer data into the device. It
SO 2 Serial Data Output receives instructions, addresses and data. Data is
WP 3 Write-Protect Pin latched on the rising edge of the serial clock.
VSS 4 Ground
3.5 Serial Clock (SCK)
SI 5 Serial Data Input
The SCK is used to synchronize the communication
SCK 6 Serial Clock Input between a master and the 25XX1024. Instructions,
HOLD 7 Hold Input addresses or data present on the SI pin are latched on
VCC 8 Supply Voltage the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.1 Chip Select (CS)
3.6 Hold (HOLD)
A low level on this pin selects the device. A high level
The HOLD pin is used to suspend transmission to the
deselects the device and forces it into Standby mode.
25XX1024 while in the middle of a serial sequence
However, a programming cycle which is already
without having to retransmit the entire sequence again.
initiated or in progress will be completed, regardless of
It must be held high any time this function is not being
the CS input signal. If CS is brought high during a
used. Once the device is selected and a serial
program cycle, the device will go into Standby mode as
sequence is underway, the HOLD pin may be pulled
soon as the programming cycle is complete. When the
low to pause further serial communication without
device is deselected, SO goes to the high-impedance
resetting the serial sequence. The HOLD pin must be
state, allowing multiple parts to share the same SPI
brought low while SCK is low, otherwise the HOLD
bus. A low-to-high transition on CS after a valid write
function will not be invoked until the next SCK high-to-
sequence initiates an internal write cycle. After power-
low transition. The 25XX1024 must remain selected
up, a low level on CS is required prior to any sequence
during this sequence. The SI, SCK and SO pins are in
being initiated.
a high-impedance state during the time the device is
3.2 Serial Output (SO) paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
The SO pin is used to transfer data out of the high while the SCK pin is low, otherwise serial
25XX1024. During a read cycle, data is shifted out on communication will not resume. Pulling the HOLD line
this pin after the falling edge of the serial clock. low at any time will tri-state the SO line.

3.3 Write-Protect (WP)

This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the
STATUS register is disabled. All other operations
function normally. When WP is high, all functions,
including writes to the nonvolatile bits in the STATUS
register, operate normally. If the WPEN bit is set, WP
low during a STATUS register write sequence will
disable writing to the STATUS register. If an internal
write cycle has already begun, WP going low will have
no effect on the write.

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 19

25AA1024/25LC1024
4.0 PACKAGING INFORMATION

4.1 Package Marking Information

8-Lead DFN Example:

XXXXXXX 5LC1024
T/XXXXX I/MF e3
YYWW 0328
NNN 1L7

8-Lead PDIP Example:

XXXXXXXX 25AA1024
T/XXXNNN I/P e3 1L7
YYWW 0328

8-Lead SOIJ Example:

XXXXXXXX 25LC1024
T/XXXXXX I/SM e3
YYWWNNN 07281L7

Legend: XX...X Part number or part number code

T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
e3 Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

* Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.

DS21836D-page 20 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024

8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S]
PUNCH SINGULATED
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D e
D1 b L
N N

E
E2
E1
EXPOSED
PAD

NOTE 1 1 2 2 1 NOTE 1
D2

TOP VIEW BOTTOM VIEW

φ

A A2

A1 A3
NOTE 2

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A – 0.85 1.00
Molded Package Thickness A2 – 0.65 0.80
Standoff A1 0.00 0.01 0.05
Base Thickness A3 0.20 REF
Overall Length D 4.92 BSC
Molded Package Length D1 4.67 BSC
Exposed Pad Length D2 3.85 4.00 4.15
Overall Width E 5.99 BSC
Molded Package Width E1 5.74 BSC
Exposed Pad Width E2 2.16 2.31 2.46
Contact Width b 0.35 0.40 0.47
Contact Length L 0.50 0.60 0.75
Contact-to-Exposed Pad K 0.20 – –
Model Draft Angle Top φ – – 12°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-113B

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 21

25AA1024/25LC1024

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

NOTE 1
E1

1 2 3

D
E

A A2

A1 L
c

e
b1 eB
b

Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-018B

DS21836D-page 22 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024

8-Lead Plastic Small Outline (SM) – Medium, 5.28 mm Body [SOIJ]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D
N

E1

1 2
e
b

c
A2 φ
A

β
A1 L

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 1.77 – 2.03
Molded Package Thickness A2 1.75 – 1.98
Standoff § A1 0.05 – 0.25
Overall Width E 7.62 – 8.26
Molded Package Width E1 5.11 – 5.38
Overall Length D 5.13 – 5.33
Foot Length L 0.51 – 0.76
Foot Angle φ 0° – 8°
Lead Thickness c 0.15 – 0.25
Lead Width b 0.36 – 0.51
Mold Draft Angle Top α – – 15°
Mold Draft Angle Bottom β – – 15°
Notes:
1. SOIJ, JEITA/EIAJ Standard, formerly called SOIC.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.

Microchip Technology Drawing C04-056B

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 23

25AA1024/25LC1024
APPENDIX A:

REVISION HISTORY

Revision C (02/2007)
Revised Features Section (Self-timed Erase and Write
Cycles); Revised Table 1-1 (Param. D012 and D13);
Table 1-2 (Param. 20-24); Revised Package Marking
Information; Replaced Package Drawings; Revised
Product ID System Section (SM package). Changed
PICmicro to PIC.

Revision D (07/2007)
Revised Features; Revised Tables 1-1 and 1-2 (added
Industrial temp. and revised parameters 22-23);
Replaced Package Drawings (Rev. AP); Revised
Product ID System; Changed Flash to EEPROM.

DS21836D-page 24 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design • Development Systems Information Line
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or field application engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 25

25AA1024/25LC1024
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response

From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N

Device: 25AA1024/25LC1024 Literature Number: DS21836D

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21836D-page 26 Preliminary © 2007 Microchip Technology Inc.

 25AA1024/25LC1024
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X – X /XX
Examples:
Device Tape & Reel Temp Range Package a) 25AA1024T-I/SM = 1 Mbit, 1.8V Serial
EEPROM, Industrial temp., Tape & Reel, SOIJ
package
b) 25AA1024T-I/MF = 1 Mbit, 1.8V Serial
EEPROM, Industrial temp., Tape & Reel, DFN
Device: 25AA1024 1 Mbit, 1.8V, 256-Byte Page SPI Serial EEPROM
package
25LC1024 1 Mbit, 2.5V, 256-Byte Page SPI Serial EEPROM
c) 25LC1024-I/P = 1 Mbit, 2.5V Serial EEPROM,
Tape & Reel: Blank = Standard packaging (tube) Industrial temp., P-DIP package
T = Tape & Reel
d) 25LC1024T-E/MF = 1 Mbit, 2.5V Serial
Temperature I = -40°C to+85°C EEPROM, Extended temp., Tape & Reel, DFN
Range: E = -40°C to+125°C package

Package: MF = Micro Lead Frame (6 x 5 mm body), 8-lead

P = Plastic DIP (300 mil body), 8-lead
SM = Plastic SOIJ (5.28 mm), 8-lead

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 27

25AA1024/25LC1024
NOTES:

DS21836D-page 28 Preliminary © 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
ensure that your application meets with your specifications.
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
MICROCHIP MAKES NO REPRESENTATIONS OR
registered trademarks of Microchip Technology Incorporated
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
QUALITY, PERFORMANCE, MERCHANTABILITY OR Embedded Control Solutions Company are registered
FITNESS FOR PURPOSE. Microchip disclaims all liability trademarks of Microchip Technology Incorporated in the
arising from this information and its use. Use of Microchip U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

© 2007 Microchip Technology Inc. Preliminary DS21836D-page 29

 WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
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Canada
Fax: 86-29-8833-7256
Tel: 905-673-0699
Fax: 905-673-6509

06/25/07

DS21836D-page 30 Preliminary © 2007 Microchip Technology Inc.