JAYPEE UNIVERSITY OF ENGINEERING &
TECHNOLOGY, GUNA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
A PRACTICAL WORK BOOK
of
COMPUTER ORGANIZATION & ARCHITECTURE
LAB (18B17CI414)
SUBMITTED
TO
Dr. Rahul Pachauri
NAME OF STUDENT : Achyut kumar Singh
ENROLL NO. : 211B017 BATCH : B1
BRANCH : CSE SESSION : 2021-2025
Name-Achyut Kumar Singh Enroll no.-211B017
INDEX
S. Date of
No. Aim of the experiment submission signature remarks
Name-Achyut Kumar Singh Enroll no.-211B017
EXPERIMENT#1
Aim: Designing of basic digital circuits using logic gates.
Exercise#1: Design two inputs and five outputs All-in-One logic gate circuit shown in Fig.1 using
Logisim simulator with (i) data width 1 (ii) data width 4.
Boolean Expressions Logic Diagram
C = ~ A
D = A.B
E = A+B
F = ~(A.B)
G = A⊕B
Truth Table
Name-Achyut Kumar Singh Enroll no.-211B017
Exercise#2: Design two inputs and one output All-in-One logic gate diagram shown in Fig.2 using
Logisim simulator with (i) data width 1 (ii) data width 8.
Boolean Expressions Logic Diagram
C = ~A ~B Y + ~A B X + A
~B X + A B ~Y
Karnaugh (K) Map
Exercise#3: Design a three-input majority detector combinational digital circuit using Logisim
simulator which shows output equal to 1 if the input variables have more 1's than 0's, the output is 0
otherwise.
Boolean Expressions Logic Diagram
X=BC+AC+AB
Karnaugh (K) Map
Name-Achyut Kumar Singh Enroll no.-211B017
Exercise#4: Design a combinational circuit with three inputs and three outputs. When the input is 0, 1,
2, or 3, the output is one greater than the input and when the input is 4, 5, 6, or 7, the output is one less
than the input. Display the input and output digits using Hex digit display with splitter.
Boolean Expressions Logic Diagram
C = not A
D = A.B
E = A+B
F = ~(A.B)
G = A⊕B
Truth Table
Name-Achyut Kumar Singh Enroll no.-211B017
EXPERIMENT#2
Aim: Design of binary adders and subtractors.
Exercise#1: Design half adder and half subtractor using logisim simulator.
Boolean Expressions Logic Diagram
Half adder: X=
~ab + a~b Y=
ab
Half subtractor: X=
~ab + a~b
Y= ~ab
Karnaugh (K) Map
Half adder:
Half subtractor:
Name-Achyut Kumar Singh Enroll no.-211B017
Exercise#2: 2 Design full adder using (i) basic gates only (ii) by adding half adder as sub circuit using
logisim.
Boolean Expressions Logic Diagram
Sum = ~A ~B C + ~A B ~C
+ A ~B ~C + A B C Carry=
BC+AC+AB
Karnaugh (K) Map
Name-Achyut Kumar Singh Enroll no.-211B017
Exercise#3: Design 4-bit binary adder using one half adder and 3-full adders as shown in Fig.
5. Use half adder and full adders as sub circuits in the design. Display both the input digits; output
digit and end carry digit using Hex digit display with splitter available in logisim simulator
Boolean Expressions Logic Diagram
S0 = (A0 + B0) (~A0 + ~B0)
S1= ~A0 ~A1 B1 + ~B0 ~A1 B1
+ ~A0 A1 ~B1 + ~B0 A1 ~B1 +
A0 B0 ~A1 ~B1 + A0 B0 A1 B1
S2= ~A0 ~A1 ~A2 B2 + ~A0 ~B1
~A2 B2 + ~B0 ~A1 ~A2 B2 +
~B0 ~B1 ~A2 B2 + ~A1 ~B1 ~A2 B2
+ ~A0 ~A1 A2 ~B2 + ~A0
~B1 A2 ~B2 + ~B0 ~A1 A2 ~B2
+ ~B0 ~B1 A2 ~B2 + ~A1 ~B1 A2
~B2 + A1 B1 ~A2 ~B2 + A1 B1 A2
B2 + A0 B0 B1 ~A2 ~B2 + A0 B0
B1 A2 B2 + A0 B0 A1
~A2 ~B2 + A0 B0 A1 A2 B2
Name-Achyut Kumar Singh Enroll no.-211B017
Exercise#4: Design 4-bit binary adder-subtractor using full adders as shown in Fig. 6. Use full adders
as sub circuits in the design. Display both the input digits, initial carry digit; output digit, and end carry
digit using Hex digit display with splitter available in logisim simulator.
Boolean Logic Diagram
Expressions
S0= ~A0 B0 + A0 ~B0
S1= ~C0 ~A0 ~A1 B1
+ ~B0 ~A1 B1 + ~C0
~A0 A1 ~B1 + ~B0 A1
~B1 + ~C0 A0 B0 ~A1
~B1 + ~C0 A0 B0 A1 B1
+ C0 ~A0 B0 ~A1
~B1 + C0 ~A0 B0 A1 B1
+ C0 A0 ~A1 B1 + C0
A0 A1 ~B1
S2= ~C0 ~A0 ~A1
~A2 B2 + ~C0 ~B0
~A1 ~A2 B2 + ~B0
~B1 ~A2 B2 + ~C0
~A0 ~A1 A2 ~B2 +
~C0 ~B0 ~A1 A2 ~B2
+ ~B0 ~B1 A2 ~B2 +
~A0 A1 ~B1 ~A2 B2 +
~A0 A1 ~B1 A2 ~B2 +
~C0 A1 B1 ~A2 ~B2 +
~C0 A1 B1 A2 B2 + A0
~A1 ~B1 ~A2 B2 + A0
~A1 ~B1 A2 ~B2 + A0
B0 ~A1 B1 ~A2
~B2 + A0 B0 ~A1 B1 A2
B2 + ~C0 A0 B0 A1 ~A2
~B2 + ~C0 A0 B0 A1 A2
B2 + C0
~A1 B1 ~A2 ~B2 + C0
~A1 B1
Name-Achyut Kumar Singh Enroll no.-211B017
EXPERIMENT#3
Exercise#1: Design an 8:1 multiplexer using two 4:1 multiplexers and one 2:1 multiplexer (shown in
Fig.1) Use both types of multiplexers as sub circuits in the design.
Boolean Logic Diagram
Expressions
h x2 ~x3 ~x4 + g x2
~x3 x4 + f x2 x3 ~x4 + e
x2 x3 x4 + d ~x2 ~x3
~x4 + c ~x2 ~x3 x4 + b
~x2 x3 ~x4 + a ~x2 x3
x4
Exercise#2: Design a 1:8 de-multiplexer using three 1:4 de-multiplexers. Use 1:4
de-multiplexers as sub circuits in the design.
Boolean Logic Diagram
Expressions
~b ~a c
Name-Achyut Kumar Singh Enroll no.-211B017
Exercise#3: Design quad to binary (4-to-2) encoder using logic gates. Display all four input digits using
seven segment displays and two output binary bits using hex displays available in logisim simulator
Truth Table Logic Diagram
Name-Achyut Kumar Singh Enroll no.-211B017
