Analog-to-Digital and

Digital-to-Analog Conversions
4.1 Introduction
• Recall that the binary number is made up
of binary digits (bits) in each digit
position of the binary number.
• Each bit can only have two values, 0 or 1.
• Each digit position has a weighted value
that is the binary digit value of 1 or 0
multiplied by the weighted value of the
digit position.
• If the bit is a 1 the digit position has the
weighted position value; if the bit is a 0,
the weighted position value is 0.
• The total value of the binary number is the
sum of all the weighted position values.
• As shown in Figure 4-1a, the binary digit
weighted digit position value increases by
2 times over the digit value to the right.
• This is very important to the design of
digital-to-analog converters (DACs) and
analog- to-digital converters (ADCs).
Figure 4-1 : Binary number and
Equivalent decimal
• The design of DACs and ADCs is based on
testing the value of the input quantity to see
if it is greater than the MSB value; if it is, is it
greater than the MSB value plus the
weighted digit position value of the next bit
to the right? If it is, is it greater than a total
of the previous bit values plus the weighted
digit position value of the next bit to the
right? The process continues until the input
is less than the sum of the weighted values.
• Then the last digit weighted position value is
not added but made equal to zero and a
weighted position value of a next bit to the
right is added and the total tested again.
• This process continues until the value is
determined or the LSB’s value is included
which indicates that the evaluation is
complete.
• In other words, as the input value is
tested, the digit values are added or they
are set at zero as the digit positions from
MSB to LSB are evaluated, and when the
LSB is reached it is the end of the
evaluation.
Decimal Equivalent of a Binary Number
• It is important to the A-to-D and D-to-A
process to know the decimal equivalent of
a binary number. Figure 4-1b summarizes
the evaluation process.
• It shows how the binary digit weighted
position value is multiplied by the bit value
at each bit position and the total of all bit
values summed to arrive at the decimal
value.
Digital Codes of ADC
• The discussion of ADCs and DACs starts by
examining the codes generated by an ADC as a
result of an analog input signal.
• Figure 4-2b shows the digital codes generated by a
4-bit analog-to-digital converter which has 16 codes
of four bits each that are generated as an analog
signal increases from 0 to 15/16 of full scale.
• As the signal increases 1/16 of full scale, the code
changes by a digital bit. As the analog signal,
shown in Figure 4-2a, varies in amplitude with time,
the digital code generated by the ADC changes to
represent the amplitude of the analog signal at the
time the signal was sampled.
• This is demonstrated by superimposing the
analog signal of Figure 4-2a, onto the ADC
transfer curve shown in Figure 4-2b. The
points of sampling are shown and numbered
from 1 through 16, and correspond to the
sampling points versus time shown in Figure
4-2a.
• The digital codes generated at each sampling
point in Figure 4-2b are listed in Figure 4-2c.
The digital code generated at a particular
sample is the code nearest the amplitude just
exceeded by the signal but not large enough
to generate the next code step.
• These codes from the sampling points
appear in sequence at the output of
the ADC to describe the analog signal.
Depending on the ADC, the digital
codes may be presented a bit at a time
in series, or all bits together in parallel
at specific times determined by a
timing network.
Figure 4-2: Converting AC signals to digital codes—A-to-
D conversion
• As shown in Figure 4-3, the digital data
from the ADC, represented in codes, is
manipulated by computing networks to
alter, modify and redefine the data, but it
emerges from the computing networks
again as a series of digital codes, again
timed by the timing network.
• The codes are presented to the DAC to be
converted back to an analog signal. The
circuit discussion begins with a DAC.
Figure 4-3: Computing network
manipulates digital data
A Resistor Network DAC
• Recall that in a digital code, the MSB’s
weighted binary digit position value is equal
to one-half the value of the full code value,
and that the next least significant bit is one-
half the MSB’s digit position value.
• This principle is used to design the DAC
shown in Figure 4-4. It is called a R/2R
ladder DAC.
• The circuit, shown in Figure 4-4a, is a
resistor network with a particular
combination of resistor values.
Figure 4-4: 4-bit R/2R ladder DAC
• From a reference voltage of VREF to ground,
there are resistors with 2R values for each bit
separated by resistors with R values, and
terminated in a resistor to ground with a 2R
value.
• The circuit is for a 4-bit DAC. A switch at the
end of each bit resistor of 2R value either
connects to ground or to the input of an
operational amplifier used as a summing
amplifier.
• If each bit in the code to be converted is a 0,
then each 2R resistor is connected to ground
and there is zero current into the summing
amplifier.
The Equivalent Resistance of the Network
• Looking at the right end of the network
• at the LSB leg, the equivalent resistance of
the 2R resistors in parallel is R.
• This equivalent resistance R in series with
the R between the second LSB leg equals
2R.
• This 2R parallels the 2R of the second LSB
leg to make an equivalent resistance of R.
This process continues so that the
equivalent resistance of the network
between VREF and ground is R.
The Digit-Position Currents
• When all bits are zero, all bit resistors are
connected to ground; with R = 10 kΩ and VREF
= 5V, the current into the network is 500 µA.
• The current into the MSB leg is 250 µA and the
current into the remaining network is 250 µA.
At the next lower significant bit, the 250 µA
divides into 125 µA down the next lower
significant bit leg and 125 µA to the remaining
network. The 125 µA divides into 62.5 µA down
the second LSB leg and 62.5 µA to the
remaining network. The 62.5 µA divides to
31.25 µA down the LSB leg and 31.25 µA to the
remaining network.
• Therefore, each current in the bit legs
is one half of the current in the bit
position to the left, just like the digit
position values in a binary number.
• Thus, the summing of the currents in
the digit position legs results in the
value of the binary number.
The Summing Amplifier
• Refer again to Figure 4-4a, when the code
bit is equal to 1, the bit leg current is
connected to a summing amplifier. For the
summing amplifier:
VOUT = −IFRF
• Where IF is the current into the inverting
input of the operational amplifier, and RF
is the feedback resistor from output to
input. The minus sign means the output is
180º out of phase from the input.
• Since,
IF = ID3 + ID2 + ID1 + ID0
• then
VOUT = –(ID3 + ID2 + ID1 + ID0) RF
• When the code is 0101, then
VOUT = –(ID2 + ID0) RF
• If ID2 = 125 µa and ID0 = 31.25 µa, then, with
RF = 20 kΩ
VOUT = –20(156.25) × 10–3
= –3.125V
• Here are two more examples:
A. the code 0001 results in:
VOUT = –(ID0) RF = –(31.25 µa) × 20 kΩ
= –625 × 10–3
= –0.625V
B. the code 1111 results in:
VOUT = –(ID3 + ID2 + ID1 + ID0) RF
= –(250 µa + 125 µa + 62.5 µa +31.25 µa) 20 kΩ
= –9375 × 10–3
= –9.375V
The codes and the output voltage at each step
are shown in Figure 4-4b.
• Check your answer with code and voltage
given in Figure 4-4b.
Analog-to-Digital Converters (ADC)
• One of the earliest ADCs was the counting
ADC shown in Figure 4-8. It is made up of a
binary counter that counts pulses from a
central clock.
• The counters binary output is fed to two
units—a DAC and a latch. Each unit has the
number of input or output bit lines to cover
the number of bits required from the ADC.
Figure 4-8: An 8-bit counting ADC
• The binary code input to the DAC
produces an analog voltage that feeds
one input of a comparator. The analog
input voltage to be converted to a digital
output is the other comparator input.
• When the input from the DAC is lower
than the analog input, the comparator will
be a high voltage (a digital 1); when the
input from the DAC is equal to or greater
than the analog input, the comparator
output is a low voltage (a digital 0).
• When the comparator output changes from a high
voltage to a low voltage, it triggers the latch to
latch in the binary values from the bit lines of the
counter. Thus, the output of the latch is the binary
code matching the value of the input analog
voltage.
• The A to D process works like this. The counter is
reset to a count of zero. The DAC output is zero as
a result. If the analog input voltage, Vin, is some
positive value, the comparator output will be a 1.
As the clock increments the counter, the output of
the DAC will increase in steps, each a small
positive voltage. If the DAC output is a lower
positive voltage than Vin, the counter continues to
count and increases the DAC output voltage until
it is greater than Vin.
• This triggers the comparator, its output
goes to 0 to latch in the binary code at the
output to the ADC and reset the counter.
Resetting the counter to zero causes the
comparator output to go to a 1 and the
ADC is ready for another conversion.
• One of the disadvantages of the counting
ADC is the time for conversion. The
conversion time can be as great as 2n – 1
clock cycles, where n is the number of
bits of the binary output of the ADC.
Successive Approximation Register
(SAR) ADC
• An improvement in conversion time
results when using a Successive
Approximation Register (SAR) ADC.
• As shown in Figure 4-9, the counter of
Figure 4-8 is replaced with logic,
register and latch circuits to make up
the SAR, one of the most popular
ADCs.
Figure 4-9: Successive approximation
ADC
• The SAR can have conversion times from
100 µS to 1 µS and up to 16 bits in
resolution. Semiconductor technologies of
bipolar, CMOS and combinations of both
have been used to design the SAR. The
SAR seems to be the design of choice for
the conversion time required because the
desired performance can be obtained at a
reasonable cost. In addition, system
throughput (speed) can be traded for
accuracy—increasing speed decreases
accuracy.
• The SAR gets its name from successively
comparing the input analog voltage to the
output of a DAC that has a binary-
weighted code at its input.
• The conversion process begins by setting
the MSB of the input to the DAC from the
SAR to a 1. All the other bits are set to 0.
• This produces an analog voltage at the
DAC output equal to one-half the full-
scale range of the DAC.
• At the comparator, as with the counting ADC,
the DAC output is compared to the input
analog voltage.
• If the input voltage is greater than the DAC
voltage, the comparator output is a 1 and the
SAR MSB is left at a 1, and the next most
significant bit input to the DAC is set to a 1.
• With the MSB and next significant bit set to a 1,
the output from the DAC will now be one-half
plus another one-quarter to equal three-
quarters of the full-scale range of the DAC.
• The sequence is shown in Figure 4-9b.
• The sequence continues to set the next
most significant bit to a 1 (all other bits
are zero) as long as the comparator
output is a 1. Each time a binary-
weighted voltage is added by the DAC
to its output—one eighth, one
sixteenth, one thirty- secondth, and so
on—the comparator output will be a 1
as long as the input voltage is greater
than the output of the DAC.
• When setting the next significant bit to a 1
causes the input voltage to be less than the
DAC output, the comparator output goes to
0. This results in setting the last significant
bit back to a 0 from a 1, reducing the DAC
output below the input voltage.
• But at the same time the next most
significant bit is set to a 1 and the DAC
output increased again; however, this time
only say one thirty- secondth of an
increment of voltage is added instead of the
one-sixteenth that was added at the bit
before.
• This is shown in Figure 4-9b.
• The successive approximation continues until all
bits are tested and the closest approximation is
obtained. The result is that the SAR output bit
either is set to a 1 or a 0 depending on the result
of the comparison of the output of the DAC and
the input voltage. The final digital code for Figure
4-9b is 11101010.
• The time to convert the input analog voltage to a
digital output is n clock cycles, much less than
the counting ADC. Figure 4-9b shows that after n
clock cycles all the bits have been tested and set
and the SAR output will be the digital output
code. The output can be taken in parallel or
shifted out as each comparison is made. This is
an additional advantage of the SAR ADC.
Highest Speed Conversions
• The highest speed conversions are made
with flash ADCs.
• The high speed is made possible by the use
of simultaneous comparisons of the analog
input voltage to references generated from a
resistor string.
• A block diagram of a flash ADC is shown in
Figure 4-14. For an n-bit flash converter,
there are 2n – 1 reference voltages and 2n – 1
comparators required.
Figure 5-14: Flash converter
• Thus, for an 8-bit flash converter, 255
comparators are required, and for a 10-
bit flash converter, 1023 comparators are
required. A high price is paid for the
speed advantage—high power, large
silicon area for the ICs, and high cost
contribute to the price that must be paid.
• The conversion process is rather simple.
The reference voltages are connected to
the minus input of each comparator and
are separated in value by one LSB.
• The analog input voltage is connected to the
plus input of each comparator. A simultaneous
comparison is made at each comparator. If
the input analog voltage on the plus input is
less than the reference voltage on the minus
input, the output of the comparator is a 0.
• The analog input voltage is connected to the
plus input of each comparator. A simultaneous
comparison is made at each comparator. If
the input analog voltage on the plus input is
less than the reference voltage on the minus
input, the output of the comparator is a 0.
• All the inputs of the input analog voltage
that are greater than their respective
resistor-string reference voltages will have
comparator outputs of a 1; all the inputs
that are less than their respective resistor-
string reference voltage will have
comparator outputs that are 0.
• The resultant digital code into the decoder
results in the equivalent binary output
code, for a given n-bit code, that represents
the value of the input analog voltage.