PIC18FXXK80 FAMILY

Flash Microcontroller Programming Specification

1.0 DEVICE OVERVIEW 2.1 Hardware Requirements
This document includes the programming specifications When programming with the ICSP, the PIC18FXXK80
for the following devices: family requires two programmable power supplies; one
for VDD and one for MCLR/VPP/RE3. Both supplies
• PIC18F25K80 • PIC18F26K80 should have a minimum resolution of 0.25V. Refer to
• PIC18LF25K80 • PIC18LF26K80 Section 6.0 “AC/DC Characteristics Timing
• PIC18F45K80 • PIC18F46K80 Requirements for Program/Verify Test Mode” for
additional hardware parameters.
• PIC18LF45K80 • PIC18LF46K80
• PIC18F65K80 • PIC18F66K80 2.1.1 LOW-VOLTAGE ICSP™
• PIC18LF65K80 • PIC18LF66K80 PROGRAMMING
In Low-Voltage ICSP mode, the PIC18FXXK80 family
2.0 PROGRAMMING OVERVIEW can be programmed using a VDD source in the operat-
ing range. The MCLR/VPP/RE3 pin does not have to be
The PIC18FXXK80 family of devices can be brought to a different voltage, but can instead, be left at
programmed using the In-Circuit Serial Programming™ the normal operating voltage. Refer to Section 6.0
(ICSP™) method. This programming specification “AC/DC Characteristics Timing Requirements for
applies to the PIC18FXXK80 family of devices in all Program/Verify Test Mode” for additional hardware
package types. parameters.

2.2 Pin Diagrams

The pin diagrams for the PIC18FXXK80 family are
shown in Figure 2-1 and Figure 2-2.

TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXXK80 FAMILY

During Programming
Pin Name
Pin Name Pin Type Pin Description

MCLR/VPP/RE3 VPP P Programming Enable

VDD(1) VDD P Power Supply
VSS(1) VSS P Ground
AVDD AVDD P Analog Power Supply
AVSS AVSS P Analog Ground
RB6 PGC I Serial Clock
RB7 PGD I/O Serial Data
VDDCORE/ VDDCORE P Regulated Power Supply for Microcontroller Core
VCAP VCAP I Filter Capacitor for On-Chip Voltage Regulator
Legend: I = Input, O = Output, P = Power
Note 1: All power supply (VDD) and ground (VSS) pins must be connected.

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PIC18FXXK80 FAMILY
FIGURE 2-1: PIC18FXXK80 FAMILY PIN DIAGRAMS

28-Pin QFN
The following devices are included in 28-pin QFN parts:
• PIC18F25K80
• PIC18F26K80
• PIC18LF25K80
• PIC18LF26K80

MCLR/VPP/RE3
RB7/PGD
RB6/PGC
RA0

RB5
RB4
RA1
28
27

25

22
26

24
23
RA2 1 21 RB3
RA3 2 20 RB2
VDDCORE/VCAP 3 19 RB1
RA5 4 PIC18F2XK80
18 RB0
VSS 5 17 VDD
RA7 6 16 VSS
RA6 7 15 RC7
14
10
11
12
13
8
9
RC0
RC1
RC2
RC3
RC4
RC5
RC6

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 PIC18FXXK80 FAMILY
FIGURE 2-2: PIC18F8XKXX FAMILY PIN DIAGRAMS

28-PIN PDIP/SOIC/SSOP
The following devices are included in 28-pin PDIP/SOIC/SSOP parts:
• PIC18F25K80
• PIC18F26K80
• PIC18LF25K80
• PIC18LF26K80

MCLR/VPP/RE3 1 28 RB7/PGD
RA0 2 27 RB6/PGC
RA1 3 26 RB5
RA2 4 25 RB4
RA3 5 24 RB3
VDDCORE/VCAP 6 23 RB2
RA5 7 22 RB1
PIC18F2XK80
VSS 8 21 RB0
RA7 9 20 VDD
RA6 10 19 VSS
RC0 11 18 RC7
RC1 12 17 RC6
RC2 13 16 RC5

RC3 14 15 RC4

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PIC18FXXK80 FAMILY
FIGURE 2-3: PIC18F8XKXX FAMILY PIN DIAGRAMS

40-PIN PDIP
The following devices are included in 40-pin PDIP parts:
• PIC18F45K80
• PIC18F46K80
• PIC18LF45K80
• PIC18LF46K80

MCLR/VPP/RE3 1 40 RB7/PGD
RA0 2 39 RB6/PGC
RA1 3 38 RB5
RA2 4 37 RB4

RA3 5 36 RB3
VDDCORE/VCAP 6 35 RB2
RA5 7 34 RB1
RE0 8 33 RB0
RE1 9 32 VDD
RE2 10 31 VSS
VDD 11
PIC18F4XK80 30 RD7
VSS 12 29 RD6
RA7 13 28 RD5
RA6 14 27 RD4
RC0 15 26 RC7
RC1 16 25 RC6
RC2 17 24 RC5
RC3 18 23 RC4
RD0 19 22 RD3
RD1 20 21 RD2

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 PIC18FXXK80 FAMILY
FIGURE 2-4: PIC18F8XKXX FAMILY PIN DIAGRAMS

44-PIN TQFP/QFN
The following devices are included in 44-pin TQFP/QFN parts:
• PIC18F45K80
• PIC18F46K80
• PIC18LF45K80
• PIC18LF46K80

RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
N/C
38
44
43
42
41

36
35
34
39

37
40
RC7 1 33 N/C
RD4 2 32 RC0
RD5 3 31 RA6
RD6 4 30 RA7
RD7 5 29 VSS
VSS 6 PIC18F4XK80 28 VDD
VDD 7 27 RE2
RB0 8 26 RE1
RB1 9 25 RE0
RB2 10 24 RA5
RB3 11 23 VDDCORE/VCAP
18
12
13
14
15

20
21
22
19
17
16
RB4
RB5

MCLR/VPP/RE3
RA0
RA1
RA2
RA3
N/C
N/C

RB6/PGC
RB7/PGD

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PIC18FXXK80 FAMILY
FIGURE 2-5: PIC18F8XKXX FAMILY PIN DIAGRAMS

64-PIN TQFP/QFN
The following devices are included in 64-pin TQFP/QFN parts:
• PIC18F65K80
• PIC18F66K80
• PIC18LF65K80
• PIC18LF66K80

RC6
RC5
RC4

RD3
RD2

RD1
RD0

RC3
RC2
RC1
RE7
RE6

RF7
RF6
VDD
VSS
58

53
64
63
62
61

56
55
54

51
50
49
59

57

52
60

48 RC0
RC7 1 47 RA6
RD4 2 RA7
46
RD5 3
45 RF5
RD6 4
44 RF4
RD7 5
43 VSS
RG0 6
42 AVSS
RG1 7
VSS 8 41 VDD
PIC18F6XK80 40 AVDD
AVDD 9
VDD 10 39 RE2

RG2 11 38 RE1

RG3 12 37 RE0

RB0 13 36 RF3
RB1 14 35 RF2
RB2 15 34 RA5
RB3 16 33 VDDCORE/VCAP
17

19
20
21

23

25
26
27
28

30
31
32
24

29
18

22
RB5
RF0
RG4
RF1
RB4

RE5

RE4
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RB6/PGC
RB7/PGD

VSS
VDD

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 PIC18FXXK80 FAMILY
2.3 On-Chip Voltage Regulator FIGURE 2-6: CONNECTIONS FOR THE
ON-CHIP REGULATOR
The PIC18FXXK80 device family is available with or
without an internal core voltage regulator. Regulator Enabled (PIC18FXXK80 Parts):
On the devices with a voltage regulator (“PIC18F” in the 5V(1)
part number), the regulator is always enabled. The reg- PIC18FXXK80
ulator input is taken from the microcontroller VDD pins. VDD
The output of the regulator is supplied internally to the
VDDCORE/VCAP pin. This pin simultaneously serves as VDDCORE/VCAP
both the regulator output and the microcontroller core
CF
power input pin. For these devices, a low-ESR (< 5Ω)
VSS
capacitor is required on the VCAP/VDDCORE pin to stabi-
lize the voltage regulator output voltage. The VCAP/
VDDCORE pin must not be connected to VDD and must
use a capacitor that is typically 10 F connected to Regulator Disabled (PIC18LFXXK80 Parts):
ground. 3.3V(1)
PIC18LFXXK80
On the devices that do not have a voltage regulator
(“PIC18LF” in the part number), power to the CPU core VDD
must be externally supplied through the microcontroller
VDD pins. VDDCORE/VCAP is internally connected to VDD. VDDCORE/VCAP(2)
A 0.1 µF capacitor should be connected to the VDDCORE/ CF
VCAP pin. Examples are shown in Figure 2-6. VSS
The specifications for core voltage and capacitance are
listed in Section 6.0 “AC/DC Characteristics Timing
Requirements for Program/Verify Test Mode”. Note 1: These are typical operating voltages. Refer
to Section 6.0 “AC/DC Characteristics
Timing Requirements for Program/Verify
Test Mode”.
2: When the regulator is disabled, VDDCORE/
VCAP must be connected to a 0.1 µF
capacitor.

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PIC18FXXK80 FAMILY
2.4 Memory Maps TABLE 2-2: IMPLEMENTATION OF CODE
MEMORY
For PIC18FX6K80 devices, the code memory space
extends from 000000h to 00FFFFh (64 Kbytes) in four Device Code Memory Size (Bytes)
16-Kbyte blocks. For PIC18FX5K80 devices, the code
PIC18F65K80
memory space extends from 000000h to 007FFFh
(32 Kbytes) in four 8-Kbyte blocks. Addresses, 0000h PIC18F45K80
through 07FFh or 0FFFh, however, define a “Boot PIC18F25K80
Block” region that is treated separately from Block 0. All 000000h-007FFFh (32K)
PIC18LF65K80
of these blocks define code protection boundaries
PIC18LF45K80
within the code memory space.
PIC18LF25K80
The size of the Boot Block in PIC18FXXK80 devices
can be configured as 1 or 2K words (see Table 5-3). PIC18F66K80
This is done through the BBSIZ bit in the Configuration PIC18F46K80
register, CONFIG4L (see Table 5-1). It is important to PIC18F26K80
note that increasing the size of the Boot Block 000000h-00FFFFh (64K)
PIC18LF66K80
decreases the size of Block 0.
PIC18LF46K80
PIC18LF26K80

FIGURE 2-7: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FXXK80 DEVICES(1)

000000h
Code Memory
01FFFFh

Device/Memory Size

PIC18FX6K80 PIC18FX5K80

BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 Address

Unimplemented
Read as ‘0’ Boot Boot Boot Boot 0000h
Block(2) Block(2) Block(2) Block(2)
2 KW Block 0 2 KW Block 0 0800h
Block 0 7 KW Block 0 3 KW 1000h
6 KW 2 KW 1FFFh
Block 1 Block 1 2000h
4 KW 4 KW 3FFFh
Block 1 Block 1 Block 2 Block 2 4000h
200000h 8 KW 8 KW 4 KW 4 KW 5FFFh
Block 3 Block 3 6000h
4 KW 4 KW 7FFFh
Block 2 Block 2 8000h
8 KW 8 KW BFFFh
Configuration Block 3 Block 3 C000h
and ID 8 KW 8 KW FFFFh
Space

3FFFFFh

Note 1: Sizes of memory areas are not to scale.

2: Boot block size is determined by the BBSIZ bit (CONFIG4L<4>).

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 PIC18FXXK80 FAMILY
In addition to the code memory space, there are three 2.4.1 MEMORY ADDRESS POINTER
blocks in the configuration and ID space that are
Memory in the address space, 0000000h to 3FFFFFh,
accessible to the user through table reads and table
is addressed via the Table Pointer register, which is
writes. Their locations in the memory map are shown in
comprised of three Pointer registers:
Figure 2-8.
• TBLPTRU, at RAM address 0FF8h
Users may store Identification (ID) information in eight
ID registers. These ID registers are mapped in • TBLPTRH, at RAM address 0FF7h
addresses, 200000h through 200007h. The ID loca- • TBLPTRL, at RAM address 0FF6h
tions read out normally, even after code protection is
applied. TBLPTRU TBLPTRH TBLPTRL
Locations, 300000h through 30000Dh, are reserved for Addr<21:16> Addr<15:8> Addr<7:0>
the Configuration bits. These bits select various device
options and are described in Section 5.0 “Configura-
The 4-bit command, ‘0000’ (core instruction), is used to
tion Word”. These Configuration bits read out normally,
load the Table Pointer prior to using many read or write
even after code protection.
operations.
Locations, 3FFFFEh and 3FFFFFh, are reserved for the
Device ID bits. These bits may be used by the program-
mer to identify what device type is being programmed
and are described in Section 5.0 “Configuration
Word”. These Device ID bits read out normally, even
after code protection.

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PIC18FXXK80 FAMILY
FIGURE 2-8: CONFIGURATION AND ID LOCATIONS FOR PIC18FXXK80 FAMILY DEVICES

000000h
Code Memory
01FFFFh ID Location 1 200000h
ID Location 2 200001h
ID Location 3 200002h
ID Location 4 200003h
ID Location 5 200004h
ID Location 6 200005h
Unimplemented
Read as ‘0’ ID Location 7 200006h
ID Location 8 200007h

CONFIG1L 300000h
CONFIG1H 300001h
CONFIG2L 300002h
CONFIG2H 300003h
1FFFFFh CONFIG3L 300004h
CONFIG3H 300005h
Configuration CONFIG4L 300006h
and ID CONFIG4H 300007h
Space CONFIG5L 300008h
CONFIG5H 300009h
CONFIG6L 30000Ah
2FFFFFh CONFIG6H 30000Bh
CONFIG7L 30000Ch
CONFIG7H 30000Dh

Device ID1 3FFFFEh

Device ID2 3FFFFFh

3FFFFFh

Note: Sizes of memory areas are not to scale.

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 PIC18FXXK80 FAMILY
2.5 High-Level Overview of the 2.6 Entering and Exiting High-Voltage
Programming Process ICSP Program/Verify Mode
Figure 2-9 shows the high-level overview of the As shown in Figure 2-11, entering High-Voltage ICSP
programming process. First, a Block Erase is performed Program/Verify mode requires two steps. First, voltage
for each block. Next, the code memory, ID locations and is applied to the MCLR pin. Second, a 32-bit key
data EEPROM are programmed. These memories are sequence is presented on PGD.
then verified to ensure that programming was successful. The programming voltage applied to MCLR is VIHH.
If no errors are detected, the Configuration bits are then VIHH must be applied to MCLR during the transfer of
programmed and verified. the key sequence. After VIHH is applied to MCLR, an
interval of at least P12 must elapse before presenting
FIGURE 2-9: HIGH-LEVEL the key sequence on PGD.
PROGRAMMING FLOW
The key sequence is a specific 32-bit pattern,‘0100
1101 0100 0011 0100 1000 0101 0000’ (more
Start easily remembered as 4D434850h in hexadecimal).
The device will enter Program/Verify mode only if the
sequence is valid. The Most Significant bit of the most
Perform Sequential
Block Erase
significant nibble must be shifted in first.
Procedure Once the key sequence is complete, Program/Verify
mode is entered, and the program memory can be
Program Memory accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
Program IDs Exiting Program/Verify mode is done by removing VIHH
from MCLR, as shown in Figure 2-13. The only require-
ment for exit is that an interval, P16, should elapse
between the last clock and the program signals on
Program Data EE
PGC and PGD before removing VIHH.

Verify Program

Verify IDs

Verify Data

Program
Configuration Bits

Verify
Configuration Bits

Done

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PIC18FXXK80 FAMILY
FIGURE 2-10: ENTERING LOW-VOLTAGE PROGRAM/VERIFY MODE

P13
P1
VIH VIH
MCLR

VDD
Program/Verify Entry Code = 4D434850h
0 1 0 0 1 ... 0 0 0 0
PGD
b31 b30 b29 b28 b27 b3 b2 b1 b0

PGC
P12 P2B
P2A

FIGURE 2-11: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE

P13
P1
MCLR VIHH

VDD
Program/Verify Entry Code = 4D434850h
0 1 0 0 1 ... 0 0 0 0
PGD
b31 b30 b29 b8 b27 b3 b2 b1 b0

PGC
P12 P2B
P2A

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 PIC18FXXK80 FAMILY
FIGURE 2-12: EXITING LOW-VOLTAGE Once the key sequence is complete, VIH, or usually
PROGRAM/VERIFY MODE VDD, must be applied to MCLR and held at that level for
as long as Program/Verify mode is to be maintained.
P16 P17 There is no minimum time requirement before present-
ing data on PGD. On successful entry, the program
MCLR/VPP/RE3 P1
memory can be accessed and programmed in serial
D041
fashion. While in the Program/Verify mode, all unused
I/Os are placed in the high-impedance state.
VDD Exiting Program/Verify mode is done by grounding the
MCLR again, as shown in Figure 2-12. The only
PGD requirement for exit is that an interval, P16, should
elapse between the last clock, and the program signals
PGC on PGC and PGD before grounding MCLR.

2.8 Serial Program/Verify Operation

PGD = Input
The PGC pin is used as a clock input pin, and the PGD
pin is used for entering command bits and data input/
FIGURE 2-13: EXITING HIGH-VOLTAGE output during serial operation. Commands and data are
PROGRAM/VERIFY MODE transmitted on the rising edge of PGC, latched on the
falling edge of PGC, and are Least Significant bit (LSb)
P16 P17 first.

MCLR/VPP/RE3 P1 2.8.1 4-BIT COMMANDS

D110 All instructions are 20 bits, consisting of a leading 4-bit
command, followed by a 16-bit operand, which
VDD depends on the type of command being executed. To
input a command, PGC is cycled four times. The com-
PGD mands needed for programming and verification are
shown in Table 2-3. Commands and data are entered
LSb first.
PGC
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data, or 8 bits of input data
PGD = Input
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Table 2-4. The 4-bit command
2.7 Entering and Exiting Low-Voltage and data are shown Most Significant bit (MSb) first. The
ICSP Program/Verify Mode command operand, or “Data Payload”, is shown as
As shown in Figure 2-10, entering Low-Voltage ICSP <LSB><MSB>. Figure 2-14 demonstrates how to serially
Program/Verify mode requires three steps: present a 20-bit command/operand to the device.

1. The MCLR pin is grounded.

2. A 32-bit key sequence is presented on PGD.
3. The MCLR pin is brought to VDD
The MCLR pin must be grounded during the transfer of
the key sequence. After MCLR is grounded, an interval
of at least P12 must elapse before presenting the key
sequence on PGD. The key sequence is a specific
32-bit pattern,‘0100 1101 0100 0011 0100 1000
0101 0000’ (more easily remembered as 4D434850h
in hexadecimal). The device will enter Program/Verify
mode only if the sequence is valid. The Most Significant
bit of the most significant nibble must be shifted in first.

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PIC18FXXK80 FAMILY
2.8.2 CORE INSTRUCTION TABLE 2-4: SAMPLE COMMAND
The core instruction passes a 16-bit instruction to the SEQUENCE
CPU core for execution. This is needed to set up 4-Bit Data
registers, as appropriate, for use with other commands. Core Instruction
Command Payload
1101 3C 40 Table Write,
TABLE 2-3: COMMANDS FOR
post-increment by 2
PROGRAMMING
4-Bit
Description
Command
Core Instruction (shift in 16-bit 0000
instruction)
Shift out TABLAT Register 0010
Table Read 1000
Table Read, Post-Increment 1001
Table Read, Post-Decrement 1010
Table Read, Pre-Increment 1011
Table Write 1100
Table Write, Post-Increment by 2 1101
Table Write, Start Programming, 1110
Post-Increment by 2
Table Write, Start Programming 1111

FIGURE 2-14: TABLE WRITE, POST-INCREMENT TIMING (‘1101’)

P2 P2A
P2B
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
PGC
P5 P5A

P4
LSB MSB
P3

PGD 1 0 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 n n n n

LSb MSb LSb 0 4 C 3 MSb

4-Bit Command 16-Bit Data Payload Fetch Next 4-Bit Command

PGD = Input

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 PIC18FXXK80 FAMILY
3.0 DEVICE PROGRAMMING The WREN bit must be set (EECON1<2> = 1) to
enable writes of any sort (e.g., erases) and this must be
Programming includes the ability to erase or write the done prior to initiating a write sequence. The FREE bit
various memory regions within the device. must be set (EECON1<4> = 1) in order to erase the
In all cases except ICSP Block Erase, the EECON1 program space being pointed to by the Table Pointer.
register must be configured in order to operate on a The erase or write sequence is initiated by setting the
particular memory region. WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit only be set immediately prior to a
When using the EECON1 register to act on code
program or erase.
memory, the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).

REGISTER 3-1: EECON1 REGISTER

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
(1)
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase/write cycle
(The operation is self-timed and the bit is cleared by hardware once the write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software.
The RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.

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PIC18FXXK80 FAMILY
3.1 ICSP Erase TABLE 3-2: ERASE BLOCK 0
3.1.1 ICSP BLOCK ERASE 4-Bit Data
Core Instruction
Command Payload
Erasing code or data EEPROM is accomplished by config-
0000 0E 3C MOVLW 3Ch
uring three Block Erase Control registers, located at 0000 6E F8 MOVWF TBLPTRU
3C0004h through 3C0006h. Code memory can only be 0000 0E 00 MOVLW 00h
erased, portions at a time. In order to erase the entire 0000 6E F7 MOVWF TBLPTRH
device, every block must be erased sequentially. Block 0000 0E 04 MOVLW 04h
Erase operations will also clear any code-protect settings 0000 6E F6 MOVWF TBLPTRL
1100 04 04 Write 04h to 3C0004h
associated with the memory block being erased. Erase 0000 0E 05 MOVLW 05h
options are detailed in Table 3-1. Data EEPROM is 0000 6E F6 MOVWF TBLPTRL
erased at the same time as all Block Erase commands. 1100 01 01 Write 01h to 3C0005h
In order to erase data EEPROM by itself, the first code 0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
sequence in Table 3-1 must be used. If the entire device 1100 80 80 Write 80h to 3C0006h to
is being erased, this code is not necessary. erase block 0
0000 00 00 NOP
TABLE 3-1: BLOCK ERASE OPERATIONS 0000 00 00 Hold PGD low until erase
Data completes
Description
(3C0006h:3C0004h)
Erase Data EEPROM 800004h TABLE 3-3: ERASE BLOCK 1
Erase Boot Block 800005h 4-Bit Data
Core Instruction
Erase Config Bits 800002h Command Payload
Erase Code EEPROM Block 0 800104h 0000 0E 3C MOVLW 3Ch
Erase Code EEPROM Block 1 800204h 0000 6E F8 MOVWF TBLPTRU
Erase Code EEPROM Block 2 800404h 0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
Erase Code EEPROM Block 3 800804h 0000 0E 04 MOVLW 04h
The actual Block Erase function is a self-timed operation. 0000 6E F6 MOVWF TBLPTRL
1100 04 04 Write 04h to 3C0004h
Once the erase has started (falling edge of the 4th PGC 0000 0E 05 MOVLW 05h
after the NOP command), serial execution will cease until 0000 6E F6 MOVWF TBLPTRL
the erase completes (Parameter P11). During this time, 1100 02 02 Write 02h to 3C0005h
PGC may continue to toggle, but PGD must be held low. 0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
The code sequence to erase the entire device is shown 1100 80 80 Write 80h to 3c0006h to
in Table 3-2 through Table 3-7 and the flowchart is erase block 1
shown in Figure 3-1. The code sequence to just erase 0000 NOP
data EEPROM is shown in Table 3-8. 0000 00 00 Hold PGD low until
00 00 erase completes
Note: A Block Erase is the only way to repro-
gram code-protect bits from an ON state
TABLE 3-4: ERASE BLOCK 2
to an OFF state.
4-Bit Data
Core Instruction
Command Payload

0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 04 MOVLW 04h
0000 6E F6 MOVWF TBLPTRL
1100 04 04 Write 04h to 3C0004h
0000 0E 05 MOVLW 05h
0000 6E F6 MOVWF TBLPTRL
1100 04 04 Write 04h to 3C0005h
0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
1100 80 80 Write 80h to 3C0006h to
erase block 2
NOP
0000 00 00 Hold PGD low until
0000 00 00 erase completes

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 PIC18FXXK80 FAMILY
TABLE 3-5: ERASE BLOCK 3 TABLE 3-7: ERASE CONFIGURATION
4-Bit Data FUSES
Core Instruction
Command Payload 4-Bit Data
Core Instruction
Command Payload
0000 0E 3C MOVLW 3Ch
0000 6E F8 MOVWF TBLPTRU 0000 0E 3C MOVLW 3Ch
0000 0E 00 MOVLW 00h 0000 6E F8 MOVWF TBLPTRU
0000 6E F7 MOVWF TBLPTRH 0000 0E 00 MOVLW 00h
0000 0E 04 MOVLW 04h 0000 6E F7 MOVWF TBLPTRH
0000 6E F6 MOVWF TBLPTRL 0000 0E 04 MOVLW 04h
1100 04 04 Write 04h to 3C0004h 0000 6E F6 MOVWF TBLPTRL
0000 0E 05 MOVLW 05h 1100 02 02 Write 02h to 3C0004h
0000 6E F6 MOVWF TBLPTRL 0000 0E 05 MOVLW 05h
1100 08 08 Write 08h to 3C0005h 0000 6E F6 MOVWF TBLPTRL
0000 0E 06 MOVLW 06h 1100 00 00 Write 00h to 3C0005h
0000 6E F6 MOVWF TBLPTRL 0000 0E 06 MOVLW 06h
1100 80 80 Write 80h to 3C0006h to 0000 6E F6 MOVWF TBLPTRL
erase block 3 1100 80 80 Write 80h to 3C0006h to
0000 00 00 NOP erase configuration fuses
0000 00 00 Hold PGD low until NOP
Erase completes 0000 00 00 Hold PGD low until
0000 00 00 Erase completes

TABLE 3-6: ERASE BOOT BLOCK

4-Bit Data TABLE 3-8: ERASE DATA EEPROM
Core Instruction
Command Payload 4-Bit Data
Core Instruction
Command Payload
0000 0E 3C MOVLW 3Ch
0000 6E F8 MOVWF TBLPTRU 0000 0E 3C MOVLW 3Ch
0000 0E 00 MOVLW 00h 0000 6E F8 MOVWF TBLPTRU
0000 6E F7 MOVWF TBLPTRH 0000 0E 00 MOVLW 00h
0000 0E 04 MOVLW 04h 0000 6E F7 MOVWF TBLPTRH
0000 6E F6 MOVWF TBLPTRL 0000 0E 04 MOVLW 04h
1100 05 05 Write 05h to 3C0004h 0000 6E F6 MOVWF TBLPTRL
0000 0E 05 MOVLW 05h 1100 04 04 Write 04h to 3C0004h
0000 6E F6 MOVWF TBLPTRL 0000 0E 05 MOVLW 05h
1100 00 00 Write 00h to 3C0005h 0000 6E F6 MOVWF TBLPTRL
0000 0E 06 MOVLW 06h 1100 00 00 Write 00h to 3C0005h
0000 6E F6 MOVWF TBLPTRL 0000 0E 06 MOVLW 06h
1100 80 80 Write 80h to 3C0006h to 0000 6E F6 MOVWF TBLPTRL
erase boot block 1100 80 80 Write 80h to 3C0006h to
0000 00 00 NOP erase Data EEPROM
0000 00 00 Hold PGD low until NOP
Erase completes 0000 00 00 Hold PGD low until
0000 00 00 Erase completes

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PIC18FXXK80 FAMILY
FIGURE 3-1: BLOCK ERASE FLOW
Start Write 05h
to 3C0004h
Write 04h
to 3C0004h Write 00h
to 3C0005h
Write 01h
to 3C0005h Write 80h to
3C0006h to Erase
Write 80h to Boot Block
3C0006h to Erase
Block 0 Delay P11 + P10
Time
Delay P11 + P10
Time Write 02h
to 3C0004h
Write 04h
to 3C0004h Write 00h
to 3C0005h
Write 02h
to 3C0005h Write 80h to
3C0006h to Erase
Write 80h to Config. Fuses
3C0006h to Erase
Block 1 Delay P11 + P10
Time
Delay P11 + P10
Time Done

Write 04h
to 3C0004h

Write 04h
to 3C0005h

Write 80h to
3C0006h to Erase
Block 2

Delay P11 + P10

Time

Write 04h
to 3C0004h

Write 08h
to 3C0005h

Write 80h to
3C0006h to Erase
Block 3

Delay P11 + P10

Time

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 PIC18FXXK80 FAMILY
FIGURE 3-2: BLOCK ERASE TIMING
P10
1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 1 2 3 4 1 2
PGC
P5 P5A P5 P5A P11

PGD 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n n

4-Bit Command 16-Bit 4-Bit Command 16-Bit 4-Bit Command Erase Time 16-Bit
Data Payload Data Payload Data Payload

PGD = Input

3.1.2 ICSP ROW ERASE The code sequence to Row Erase a PIC18FXXK80
family device is shown in Table 3-9. The flowchart
It is possible to erase one row (64 bytes of data)
shown in Figure 3-3 depicts the logic necessary to
provided the block is not code or write-protected. Rows
completely erase a PIC18FXXK80 family device. The
are located at static boundaries beginning at program
timing diagram that details the Start Programming
memory address, 000000h, extending to the internal
command and Parameters P9 and P10 is shown in
program memory limit (see Section 2.4 “Memory
Figure 3-4.
Maps”).
The Row Erase duration is externally timed and is Note: The TBLPTR register can point to any
controlled by PGC. After the WR bit in EECON1 is set, byte within the row intended for erase.
a NOP is issued, where the 4th PGC is held high for the
duration of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by Parameter P10 to allow high-voltage
discharge of the memory array.

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PIC18FXXK80 FAMILY
TABLE 3-9: SINGLE ROW ERASE CODE MEMORY CODE SEQUENCE
4-Bit
Data Payload Core Instruction
Command
Step 1: Direct access to code memory and enable writes.
0000 8E 7F BSF EECON1, EEPGD
0000 9C 7F BCF EECON1, CFGS
0000 84 7F BSF EECON1, WREN
Step 2: Point to first row in code memory.
0000 6A F8 CLRF TBLPTRU
0000 6A F7 CLRF TBLPTRH
0000 6A F6 CLRF TBLPTRL
Step 3: Enable erase and erase single row.
0000 88 7F BSF EECON1, FREE
0000 82 7F BSF EECON1, WR
0000 00 00 NOP – hold PGC high for time P9 and low for time P10.
Step 4: Repeat Step 3 with Address Pointer incremented by 64 until all rows are erased.

FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW

Start

Addr = 0
Configure
Device for
Row Erases

Start Erase Sequence

and Hold PGC High
for Time P9

Addr = Addr + 64

Hold PGC Low

for Time P10

All
No rows
done?

Yes

Done

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 PIC18FXXK80 FAMILY
3.2 Code Memory Programming The code sequence to program a PIC18FXXK80 family
device is shown in Table 3-11. The flowchart, shown in
Programming code memory is accomplished by first Figure 3-6, depicts the logic necessary to completely
loading data into the write buffer and then initiating a write a PIC18FXXK80 family device. The timing
programming sequence. The write and erase buffer diagram that details the Start Programming command,
sizes, shown in Table 3-10, can be mapped to any and Parameters P9 and P10 is shown in Figure 3-4.
location of the same size beginning at 000000h. The
actual memory write sequence takes the contents of Note: The TBLPTR register must point to the
this buffer and programs the proper amount of code same region when initiating the program-
memory that contains the Table Pointer. ming sequence as it did when the write
The programming duration is externally timed and is buffers were loaded.
controlled by PGC. After a Start Programming
command is issued (4-bit command, ‘1111’), a NOP is TABLE 3-10: WRITE AND ERASE
issued, where the 4th PGC is held high for the duration BUFFER SIZES
of the programming time, P9.
Write Buffer Size Erase Buffer
After PGC is brought low, the programming sequence All Devices
in Bytes Size in Bytes
is terminated. PGC must be held low for the time
specified by Parameter P10 to allow high-voltage PIC18FXXK80 64 64
discharge of the memory array.

FIGURE 3-4: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (‘1111’)
P10
1 2 3 4 1 2 3 4 5 6 15 16 1 2 3 4 1 2 3
PGC (1)
P9
P5 P5A

PGD 1 1 1 1 n n n n n n n n 0 0 0 0 0 0 0

4-Bit Command 16-Bit Data Payload 4-bit Command Programming Time 16-Bit
Data Payload
PGD = Input

Note 1: Use P9A for User ID and Configuration Word programming.

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PIC18FXXK80 FAMILY
FIGURE 3-5: ERASE AND WRITE BOUNDARIES

Panel 2
TBLPTR<5:0> = 63

64-byte Write Buffer

.
TBLPTR<21:16> = 1 .
.
.
.
Erase Region
TBLPTR<5:0> = 0 64 Bytes

Offset = TBLPTR<15:6>

Panel 1
TBLPTR<5:0> = 63
64-byte Write Buffer

.
TBLPTR<21:16> = 0 .
.
.
. Erase Region
64 Bytes
TBLPTR<5:0> = 0

Offset = TBLPTR<15:6>

Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.

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 PIC18FXXK80 FAMILY
3.2.1 PROGRAMMING
A maximum of 64 bytes can be programmed into the
block referenced by TBLPTR<21:6>. The panel that
will be written will automatically be enabled based on
the value of the Table Pointer.

TABLE 3-11: WRITE CODE MEMORY CODE SEQUENCE FOR PROGRAMMING

4-Bit
Data Payload Core Instruction
Command
Step 1: Direct access to code memory and enable writes.
0000 8E 7F BSF EECON1, EEPGD
0000 9C 7F BCF EECON1, CFGS
0000 84 7F BSF EECON1, WREN
Step 2: Point to row to be written.
0000 0E <Addr[21:16]> MOVLW <Addr[21:16]>
0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[15:8]> MOVLW <Addr[15:8]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL
Step 3: Load write buffer for panel. Repeat for all but the last two bytes. Any unused locations should be filled with
FFFFh.
1101 <MSB><LSB> Write 2 bytes and post-increment address by 2.
. . .
. . Repeat 31 times.
Step 4: Load write buffer for last two bytes.
. . .
1111 <MSB><LSB> Write 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9, low for time P10
To continue writing data, repeat Steps 3 and 4, where the Address Pointer is incremented by 64 at each iteration of
the loop.

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PIC18FXXK80 FAMILY
FIGURE 3-6: PROGRAM CODE MEMORY FLOW

Start

LoopCount = 0

Configure
Device for
Writes

Load 2 Bytes
to Write
Buffer at <Addr>

All
No bytes
LoopCount =
LoopCount + 1 written?

Yes
Start Write Sequence
and Hold PGC
High Until Done
and Wait P9

No All
locations
done?

Yes

Done

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 PIC18FXXK80 FAMILY
3.2.2 MODIFYING CODE MEMORY The appropriate number of bytes required for the erase
buffer must be read out of code memory (as described
The previous programming example assumed that the
in Section 4.2 “Verify Code Memory and ID Loca-
device had been erased entirely prior to programming
tions”) and buffered. Modifications can be made on this
(see Section 3.1.1 “ICSP Block Erase”). It may be the
buffer. Then, the block of code memory that was read
case, however, that the user wishes to modify only a
out must be erased and rewritten with the modified data
section of an already programmed device.
(see Section 3.2.1 “Programming”).
The WREN bit must be set if the WR bit in EECON1 is
used to initiate a write sequence.

TABLE 3-12: MODIFYING CODE MEMORY

4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to code memory.

Step 2: Read and modify code memory (see Section 4.1 “Read Code Memory, ID Locations and Configuration Bits”).
0000 8E 7F BSF EECON1, EEPGD
0000 9C 7F BCF EECON1, CFGS
Step 3: Set the Table Pointer for the block to be erased.
0000 0E <Addr[21:16]> MOVLW <Addr[21:16]>
0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[8:15]> MOVLW <Addr[8:15]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL
Step 4: Enable memory writes and set up an erase.
0000 84 7F BSF EECON1, WREN
0000 88 7F BSF EECON1, FREE
Step 5: Initiate erase.
0000 82 7F BSF EECON1, WR
0000 00 00 NOP - hold PGC high for time P9 and low for time P10.
Step 6: Direct access to configuration memory.
0000 8E 7F BSF EECON1, EEPGD
0000 8C 7F BSF EECON1, CFGS
0000 84 7F BSF EECON1, WREN
Step 7: Direct access to code memory and enable writes.
0000 8E 7F BSF EECON1, EEPGD
0000 9C 7F BCF EECON1, CFGS
Step 8: Load write buffer. The correct bytes will be selected based on the Table Pointer.
0000 0E <Addr[21:16]> MOVLW <Addr[21:16]>
0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[8:15]> MOVLW <Addr[8:15]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL
1101 <MSB><LSB> Write 2 bytes and post-increment address by 2.
. .
. . Repeat 31 times
. .
1111 <MSB><LSB> Write 2 bytes and start programming.
0000 00 00 NOP - hold PGC high for time P9 and low for time P10.
To continue modifying data, repeat Steps 2 through 8, where the Address Pointer is incremented by 64 bytes at each iteration of the
loop.
Step 9: Disable writes.
0000 94 7F BCF EECON1, WREN

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PIC18FXXK80 FAMILY
3.3 Data EEPROM Programming FIGURE 3-7: PROGRAM DATA FLOW
Data EEPROM is accessed, one byte at a time, via an Start
Address Pointer (register pair, EEADRH:EEADR) and
a Data Latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory Set Address
location, EEDATA with the data to be written and
initiating a memory write by appropriately configuring
the EECON1 register (Register 3-1). A byte write auto- Set Data
matically erases the location and writes the new data
(erase-before-write).
Enable Write
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must Start Write
be set (EECON1<2> = 1) to enable writes of any sort Sequence
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit No
WR bit (EECON1<1> = 1). clear?
The write begins on the falling edge of the 4th PGC Yes
after the WR bit is set. It ends when the WR bit is
cleared by hardware. No
Done?
After the programming sequence terminates, PGC must
still be held low for the time specified by Parameter P10 Yes
to allow high-voltage discharge of the memory array.
Done

FIGURE 3-8: DATA EEPROM WRITE TIMING

P10
1 2 3 4 1 2 15 16 1 2
PGC
P5 P5A P11A

PGD 0 0 0 0 n n

4-Bit Command BSF EECON1, WR Poll WR Bit, Repeat until Clear 16-Bit Data
(see below) Payload

PGD = Input

1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16
PGC
P5 P5A P5 P5A
Poll WR bit
0 0 0 0 0 0 0 0
PGD

4-Bit Command MOVF EECON1, W, 0 4-Bit Command MOVWF TABLAT Shift Out Data
(see Figure 4-4)
PGD = Input PGD = Output

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 PIC18FXXK80 FAMILY
TABLE 3-13: PROGRAMMING DATA MEMORY
4-Bit
Data Payload Core Instruction
Command
Step 1: Direct access to data EEPROM.
0000 9E 7F BCF EECON1, EEPGD
0000 9C 7F BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000 0E <Addr> MOVLW <Addr>
0000 6E 74 MOVWF EEADR
0000 OE <AddrH> MOVLW <AddrH>
0000 6E 75 MOVWF EEADRH
Step 3: Load the data to be written.
0000 0E <Data> MOVLW <Data>
0000 6E 73 MOVWF EEDATA
Step 4: Enable memory writes.
0000 84 7F BSF EECON1, WREN
Step 5: Initiate write.
0000 82 7F BSF EECON1, WR
Step 6: Poll WR bit, repeat until the bit is clear.
0000 50 7F MOVF EECON1, W, 0
0000 6E F5 MOVWF TABLAT
0000 00 00 NOP
0010 <MSB><LSB> Shift out data(1)
Step 7: Hold PGC low for time, P10.
Step 8: Disable writes.
0000 94 7F BCF EECON1, WREN
Repeat Steps 2 through 8 to write more data.
Note 1: See Figure 4-4 for details on shift out data timing.

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PIC18FXXK80 FAMILY
3.4 ID Location Programming Table 3-14 demonstrates the code sequence required
to write the ID locations.
The ID locations are programmed much like the code
memory. The ID registers are mapped in addresses, In order to modify the ID locations, refer to the method-
200000h through 200007h. These locations read out ology described in Section 3.2.2 “Modifying Code
normally even after code protection. Memory”. As with code memory, the ID locations must
be erased before being modified.
Note: The user only needs to fill the first 8 bytes
of the write buffer in order to write the ID
locations.

TABLE 3-14: WRITE ID SEQUENCE

4-Bit
Data Payload Core Instruction
Command
Step 1: Direct access to code memory and enable writes.
0000 8E 7F BSF EECON1, EEPGD
0000 9C 7F BCF EECON1, CFGS
Step 2: Load write buffer with 8 bytes and write.
0000 0E 20 MOVLW 20h
0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 00 MOVLW 00h
0000 6E F6 MOVWF TBLPTRL
1101 <MSB><LSB> Write 2 bytes and post-increment address by 2.
1101 <MSB><LSB> Write 2 bytes and post-increment address by 2.
1101 <MSB><LSB> Write 2 bytes and post-increment address by 2.
1111 <MSB><LSB> Write 2 bytes and start programming.
0000 00 00 NOP - hold PGC high for time P9 and low for time P10.

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3.5 Boot Block Programming 3.6 Configuration Bits Programming
The code sequence detailed in Table 3-11 should be Unlike code memory, the Configuration bits are
used, except that the address used in “Step 2” will be in programmed a byte at a time. The Table Write, Begin
the range of 000000h to 0007FFh, or 000000h to Programming 4-bit command (‘1111’) is used, but only
000FFFh, as defined by the BBSIZ bit in the 8 bits of the following 16-bit payload will be written. The
CONFIG4L register (see Table 5-1). LSB of the payload will be written to even addresses and
the MSB will be written to odd addresses. The code
sequence to program two consecutive configuration
locations is shown in Table 3-15.
Note: The address must be explicitly written for
each byte programmed. The addresses
can not be incremented in this mode.

TABLE 3-15: SET ADDRESS POINTER TO CONFIGURATION LOCATION

4-Bit
Data Payload Core Instruction
Command
Step 1: Enable writes and direct access to configuration memory.
0000 8E 7F BSF EECON1, EEPGD
0000 8C 7F BSF EECON1, CFGS
Step 2: Set Table Pointer for configuration byte to be written; write even/odd addresses.(1)
0000 0E 30 MOVLW 30h
0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 00 MOVLW 00h
0000 6E F6 MOVWF TBLPTRL
1111 <MSB ignored><LSB> Load 2 bytes and start programming.
0000 00 00 NOP - hold PGC high for time P9 and low for time P10.
0000 0E 01 MOVLW 01h
0000 6E F6 MOVWF TBLPTRL
1111 <MSB><LSB ignored> Load 2 bytes and start programming.
0000 00 00 NOP - hold PGC high for time P9A and low for time P10.
Note 1: Enabling the write protection of the Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of
the Configuration bits. Always write all of the Configuration bits before enabling the write protection for the
Configuration bits.

FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW

Start Start

Load Even Load Odd

Configuration Configuration
Address Address

Program Program
LSB MSB

Delay P9A and P10 Delay P9A and P10

Time for Write Time for Write

Done Done

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PIC18FXXK80 FAMILY
4.0 READING THE DEVICE The 4-bit command is shifted in, LSb first. The read is
executed during the next 8 clocks, then shifted out on
PGD during the last 8 clocks, LSb to MSb. A delay of
4.1 Read Code Memory, ID Locations
P6 must be introduced after the falling edge of the 8th
and Configuration Bits PGC of the operand to allow PGD to transition from an
Code memory is accessed, one byte at a time, via the input to an output. During this time, PGC must be held
4-bit command, ‘1001’ (table read, post-increment). low (see Figure 4-1). This operation also increments
The contents of memory pointed to by the Table Pointer the Table Pointer by one, pointing to the next byte in
(TBLPTRU:TBLPTRH:TBLPTRL) are serially output on code memory for the next read.
PGD. This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to reading the ID and Configuration registers.

TABLE 4-1: READ CODE MEMORY SEQUENCE

4-Bit
Data Payload Core Instruction
Command
Step 1: Set Table Pointer.
0000 0E <Addr[21:16]> MOVLW Addr[21:16]
0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[15:8]> MOVLW <Addr[15:8]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL
Step 2: Read memory and then shift out on PGD, LSb to MSb.
1001 00 00 TBLRD *+

FIGURE 4-1: TABLE READ, POST-INCREMENT INSTRUCTION TIMING (‘1001’)

1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
PGC
P5 P6 P5A

P14

PGD 1 0 0 1 LSb 1 2 3 4 5 6 MSb n n n n

Shift Data Out Fetch Next 4-Bit Command

PGD = Input PGD = Output PGD = Input

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 PIC18FXXK80 FAMILY
4.2 Verify Code Memory and The Table Pointer must be manually set to 200000h
ID Locations (base address of the ID locations) once the code
memory has been verified. The post-increment feature
The verify step involves reading back the code memory of the table read, 4-bit command may not be used to
space and comparing it against the copy held in the increment the Table Pointer beyond the code memory
programmer’s buffer. Memory reads occur a single byte space. In a 128-Kbyte device, for example, a
at a time, so two bytes must be read to compare post-increment read of address, 1FFFFh, will wrap the
against the word in the programmer’s buffer. Refer to Table Pointer back to 000000h, rather than point to the
Section 4.1 “Read Code Memory, ID Locations and unimplemented address, 020000h.
Configuration Bits” for implementation details of
reading code memory.

FIGURE 4-2: VERIFY CODE MEMORY FLOW

Start

Set TBLPTR = 0 Set TBLPTR = 200000h

Read Low Byte Read Low Byte

with Post-Increment with Post-Increment

Read High Byte Increment Read High Byte

with Post-Increment Pointer with Post-Increment

Does Does
No No
Word = Expect Failure, Word = Expect Failure,
Data? Report Data? Report
Error Error
Yes Yes

All All
No code memory No ID locations
verified? verified?

Yes Yes

Done

 2011 Microchip Technology Inc. DS39972B-page 31

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PIC18FXXK80 FAMILY
4.3 Verify Configuration Bits FIGURE 4-3: READ DATA EEPROM
FLOW
A configuration address may be read and output on
PGD via the 4-bit command, ‘1001’. Configuration data
is read and written in a byte-wise fashion, so it is not Start
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
Set
compared to the appropriate configuration data in the
Address
programmer’s memory for verification. Refer to
Section 4.1 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of Read
reading configuration data. Byte

4.4 Read Data EEPROM Memory

Move to TABLAT
Data EEPROM is accessed, one byte at a time, via an
Address Pointer (register pair, EEADRH:EEADR) and
a Data Latch (EEDATA). Data EEPROM is read by
loading EEADRH:EEADR with the desired memory Shift Out Data
location and initiating a memory read by appropriately
configuring the EECON1 register (Register 3-1). The
data will be loaded into EEDATA, where it may be No
serially output on PGD via the 4-bit command, ‘0010’ Done?
(Shift Out Data Holding register). A delay of P6 must be
Yes
introduced after the falling edge of the 8th PGC of the
operand to allow PGD to transition from an input to an Done
output. During this time, PGC must be held low (see
Figure 4-4).
The command sequence to read a single byte of data
is shown in Table 4-2.

TABLE 4-2: READ DATA EEPROM MEMORY

4-Bit
Data Payload Core Instruction
Command
Step 1: Direct access to data EEPROM.
0000 9E 7F BCF EECON1, EEPGD
0000 9C 7F BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000 0E <Addr> MOVLW <Addr>
0000 6E 74 MOVWF EEADR
0000 OE <AddrH> MOVLW <AddrH>
0000 6E 75 MOVWF EEADRH
Step 3: Initiate a memory read.
0000 80 7F BSF EECON1, RD
Step 4: Load data into the Serial Data Holding register.
0000 50 73 MOVF EEDATA, W, 0
0000 6E F5 MOVWF TABLAT
0000 00 00 NOP
0010 <MSB><LSB> Shift Out Data(1)
Note 1: The <LSB> is undefined; the <MSB> is the data.

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 PIC18FXXK80 FAMILY
FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TIMING (‘0010’)

1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
PGC
P5 P6 P5A

P14

PGD 0 1 0 0 LSb 1 2 3 4 5 6 MSb n n n n

Shift Data Out Fetch Next 4-Bit Command

PGD = Input PGD = Output PGD = Input

4.5 Verify Data EEPROM Given that Blank Checking is merely code and data
EEPROM verification with FFh expect data, refer to
A data EEPROM address may be read via a sequence Section 4.4 “Read Data EEPROM Memory” and
of core instructions (4-bit command, ‘0000’) and then Section 4.2 “Verify Code Memory and ID Locations”
output on PGD via the 4-bit command, ‘0010’ (TABLAT for implementation details.
register). The result may then be immediately com-
pared to the appropriate data in the programmer’s
FIGURE 4-5: BLANK CHECK FLOW
memory for verification. Refer to Section 4.4 “Read
Data EEPROM Memory” for implementation details of
reading data EEPROM. Start

4.6 Blank Check

Blank Check Device
The term, “Blank Check”, means to verify that the device
has no programmed memory cells. All memories must
be verified: code memory, data EEPROM, ID locations
and Configuration bits. The Device ID registers Is
device Yes
(3FFFFEh:3FFFFFh) should be ignored. Continue
blank?
A “blank” or “erased” memory cell will read as a ‘1’. So,
Blank Checking a device merely means to verify that all No
bytes read as FFh, except the Configuration bits.
Unused (reserved) Configuration bits will read ‘0’ (pro- Abort
grammed). Refer to Table 5-1 for blank configuration
expect data for the various PIC18FXXK80 family
devices.

 2011 Microchip Technology Inc. DS39972B-page 33

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PIC18FXXK80 FAMILY
5.0 CONFIGURATION WORD 5.1 ID Locations
The PIC18FXXK80 family of devices has several A user may store Identification (ID) information in eight
Configuration Words. These bits can be set or cleared ID locations, mapped in 200000h:200007h. It is recom-
to select various device configurations. All other mended that the most significant nibble of each ID be
memory areas should be programmed and verified Fh. In doing so, if the user code inadvertently tries to
prior to setting the Configuration Words. These bits execute from the ID space, the ID data will execute as
may be read out normally, even after read or code a NOP.
protection. See Table 5-1 for a list of Configuration bits
and Device IDs, and Table 5-3 for the Configuration bit
descriptions.

TABLE 5-1: CONFIGURATION BITS AND DEVICE IDs

Default/
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed
Value

300000h CONFIG1L — XINST — SOSCSEL1 SOSCSEL0 INTOSCSEL — RETEN -1-1 11-1

300001h CONFIG1H IESO FCMEN — PLLCFG FOSC3 FOSC2 FOSC1 FOSC0 00-0 1000
300002h CONFIG2L — BORPW1 BORPW0 BORV1 BORV0 BOREN1 BOREN0 PWRTEN -111 1111
300003h CONFIG2H — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 -111 1111
300005h CONFIG3H MCLRE — — — MSSPMSK T3CKMX(1,3) T0CKMX(1) CANMX 1--- 1111
300006h CONFIG4L DEBUG — — BBSIZ — — — STVREN 1--1 ---1
300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 ---- 1111
300009h CONFIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 ---- 1111
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----
30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 ---- 1111
30000Dh CONFIG7H — EBTRB — — — — — — -1-- ----
3FFFFEh DEVID1(2) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx
(2)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Only implemented in 64-pin devices.
2: See Register 28-13 in the “PIC18F66K80 Family Data Sheet” for DEVID1 values. DEVID registers are read-only and cannot be
programmed by the user.
3: This bit must be maintained as ‘0’ on 28-pin PIC18F2XK80 and 40/44-pin PIC18F4XK80 devices.

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 PIC18FXXK80 FAMILY
5.2 Device ID Word TABLE 5-2: DEVICE ID VALUE
The Device ID word (DEVID<2:1>) for the Device ID Value
Device
PIC18FXXK80 family of devices is located at DEVID2 DEVID1
3FFFFEh:3FFFFFh. These bits may be used by the
programmer to identify what device type is being PIC18F66K80 60h 111x xxxx
programmed and read out normally, even after code or PIC18F46K80 61h 000x xxxx
read protection. See Table 5-2 for a complete list of PIC18F26K80 61h 001x xxxx
Device ID values.
PIC18F65K80 61h 010x xxxx
PIC18F45K80 61h 011x xxxx
FIGURE 5-1: READ DEVICE ID WORD FLOW
PIC18F25K80 61h 100x xxxx
Start PIC18LF66K80 61h 110x xxxx
PIC18LF46K80 61h 111x xxxx
Set TBLPTR = 3FFFFE
PIC18LF26K80 62h 000x xxxx
Read Low Byte PIC18LF65K80 62h 001x xxxx
with Post-Increment PIC18LF45K80 62h 010x xxxx
PIC18LF25K80 62h 011x xxxx
Read High Byte
with Post-Increment Note: The ‘x’s in DEVID1 contain the device
revision code.
Done

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PIC18FXXK80 FAMILY
TABLE 5-3: PIC18FXXK80 FAMILY CONFIGURATION BIT DESCRIPTIONS
Configuration
Bit Name Description
Words
XINST CONFIG1L Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
SOSCSEL<1:0> CONFIG1L SOSC Power Selection and Mode Configuration bits
11 = High-power SOSC circuit selected
10 = Digital (SCLKI) mode
01 = Low-power SOSC circuit selected
00 = Reserved
INTOSCSEL CONFIG1L LF-INTOSC Low-Power Enable bit
1 = LF-INTOSC in High-Power mode during Sleep
0 = LF-INTOSC in Low-Power mode during Sleep
RETEN CONFIG1L VREG Sleep Enable bit
1 = Ultra low-power regulator is disabled. Regulator power in Sleep mode is controlled by
VREGSLP (WDTCON<7>).
0 = Ultra low-power regulator is enabled. Regulator power in Sleep mode is controlled by
SRETEN (WDTCON<4>).
IESO CONFIG1H Internal External Switchover bit
1 = Two-Speed Start-up is enabled
0 = Two-Speed Start-up is disabled
FCMEN CONFIG1H Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
PLLCFG CONFIG1H 4 x PLL Enable bit
1 = Oscillator is multiplied by 4
0 = Oscillator is used directly
FOSC<3:0> CONFIG1H Oscillator Selection bits
1101 = EC1, EC oscillator (low power, DC-160 kHz)
1100 = EC1IO, EC oscillator with CLKOUT function on RA6 (low power, DC-160 kHz)
1011 = EC2, EC oscillator (medium power, 160 kHz-16 MHz)
1010 = EC2IO, EC oscillator with CLKOUT function on RA6 (medium power, 160 kHz-16 MHz)
1001 = INTIO1 internal RC oscillator with CLKOUT function on RA6
1000 = INTIO2 internal RC oscillator
0111 = RC external RC oscillator
0110 = RCIO external RC oscillator with CKLOUT function on RA6
0101 = EC3, EC oscillator (high power, 16 MHz-64 MHz)
0100 = EC3IO, EC oscillator with CLKOUT function on RA6 (high power, 16 MHz-64 MHz)
0011 = HS1, HS oscillator (medium power, 4 MHz-16 MHz)
0010 = HS2, HS oscillator (high power, 16 MHz-25 MHz)
0001 = XT oscillator
0000 = LP oscillator
BORPWR<1:0> CONFIG2L BORMV Power Level bits
11 = ZPBORMV instead of BORMV is selected
10 = BORMV is set to high-power level
01 = BORMV is set to medium power level
00 = BORMV is set to low-power level
BORV<1:0> CONFIG2L Brown-out Reset Voltage bits
11 = VBOR set to 1.8V
10 = VBOR set to 2.0V
01 = VBOR set to 2.7V
00 = VBOR set to 3.0V
Note 1: The BBSIZ bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or
WRT0, EBTRB or EBTR0.
2: Available on PIC18F6XKXX devices only.
3: This bit must be maintained as ‘0’ on 28-pin PIC18F2XK80 and 40-pin PIC18F4XK80 devices.

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 PIC18FXXK80 FAMILY
TABLE 5-3: PIC18FXXK80 FAMILY CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
Bit Name Description
Words
BOREN<1:0> CONFIG2L Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset is enabled in hardware only and disabled in Sleep mode
(SBOREN is disabled)
01 = Brown-out Reset is enabled and controlled by software (SBOREN is enabled)
00 = Brown-out Reset is disabled in hardware and software
PWRTEN CONFIG2L Power-up Timer Enable bit
1 = PWRT is disabled
0 = PWRT is enabled
WDTPS<4:0> CONFIG2H Watchdog Timer Postscale Select bits
10101-11111: Reserved
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32,768
01110 = 1:16,384
01101 = 1:8,192
01100 = 1:4,096
01011 = 1:2,048
01010 = 1:1,024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
WDTEN<1:0> CONFIG2H Watchdog Timer Enable bits
11 = WDT is enabled in hardware; SWDTEN bit is disabled
10 = WDT is controlled with the SWDTEN bit setting
01 = WDT is enabled only while device is active and disabled in Sleep; SWDTEN bit is
disabled
00 = WDT is disabled in hardware; SWDTEN bit is disabled
MCLRE CONFIG3H MCLR Pin Enable bit
1 = MCLR pin is enabled, RE3 input pin is disabled
0 = RE3 input pin is enabled, MCLR pin is disabled
MSSPMSK CONFIG3H MSSP V3 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enable
0 = 5-Bit Address Masking mode enable
T3CKMX(2,3) CONFIG3H Timer3 Clock Input MUX bit
1 = Timer3 gets its clock input from the T1CKI input when T3CON(SOSCEN) = 0
0 = Timer3 gets its clock input from the T3CKI input when T3CON(SOSCEN) = 0
T0CKMX(2) CONFIG3H Timer0 Clock Input MUX bit
1 = Timer0 gets its clock input from the RB5/T0CKI pin
0 = Timer0 gets its clock input from the RG4/T0CKI pin
CANMX CONFIG3H ECAN MUX bit
1 = ECAN TX and RX pins are located on RB2 and RB3, respectively
0 = ECAN TX and RX pins are located on RC6 and RC7, respectively (28-pin and 44-pin
packages) or on RE5 and RE4, respectively (64-pin package)
Note 1: The BBSIZ bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or
WRT0, EBTRB or EBTR0.
2: Available on PIC18F6XKXX devices only.
3: This bit must be maintained as ‘0’ on 28-pin PIC18F2XK80 and 40-pin PIC18F4XK80 devices.

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PIC18FXXK80 FAMILY
TABLE 5-3: PIC18FXXK80 FAMILY CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
Bit Name Description
Words
DEBUG CONFIG4L Background Debugger Enable bit
1 = Background debugger is disabled, RB6 and RB7 are configured as general purpose
I/O pins
0 = Background debugger is enabled, RB6 and RB7 are dedicated to In-Circuit Debug
BBSIZ(1) CONFIG4L Boot Block Size Select bit
1 = 2K word Boot Block size
0 = 1K word Boot Block size
STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow is enabled
0 = Reset on stack overflow/underflow is disabled
CP3 CONFIG5L Code Protection bit (Block 3 code memory area)
1 = Block 3 is not code-protected
0 = Block 3 is code-protected
CP2 CONFIG5L Code Protection bit (Block 2 code memory area)
1 = Block 2 is not code-protected
0 = Block 2 is code-protected
CP1 CONFIG5L Code Protection bit (Block 1 code memory area)
1 = Block 1 is not code-protected
0 = Block 1 is code-protected
CP0 CONFIG5L Code Protection bit (Block 0 code memory area)
1 = Block 0 is not code-protected
0 = Block 0 is code-protected
CPD CONFIG5H Code Protection bit (Data EEPROM)
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
CPB CONFIG5H Code Protection bit (Boot Block memory area)
1 = Boot Block is not code-protected
0 = Boot Block is code-protected
WRT3 CONFIG6L Write Protection bit (Block 3 code memory area)
1 = Block 3 is not write-protected
0 = Block 3 is write-protected
WRT2 CONFIG6L Write Protection bit (Block 2 code memory area)
1 = Block 2 is not write-protected
0 = Block 2 is write-protected
WRT1 CONFIG6L Write Protection bit (Block 1 code memory area)
1 = Block 1 is not write-protected
0 = Block 1 is write-protected
WRT0 CONFIG6L Write Protection bit (Block 0 code memory area)
1 = Block 0 is not write-protected
0 = Block 0 is write-protected
WRTD CONFIG6H Write Protection bit (Data EEPROM)
1 = Data EEPROM is not write-protected
0 = Data EEPROM is write-protected
WRTB CONFIG6H Write Protection bit (Boot Block memory area)
1 = Boot Block is not write-protected
0 = Boot Block is write-protected
WRTC CONFIG6H Write Protection bit (Configuration registers)
1 = Configuration registers are not write-protected
0 = Configuration registers are write-protected
EBTR3 CONFIG7L Table Read Protection bit (Block 3 code memory area)
1 = Block 3 is not protected from table reads executed in other blocks
0 = Block 3 is protected from table reads executed in other blocks
Note 1: The BBSIZ bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or
WRT0, EBTRB or EBTR0.
2: Available on PIC18F6XKXX devices only.
3: This bit must be maintained as ‘0’ on 28-pin PIC18F2XK80 and 40-pin PIC18F4XK80 devices.

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 PIC18FXXK80 FAMILY
TABLE 5-3: PIC18FXXK80 FAMILY CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
Bit Name Description
Words
EBTR2 CONFIG7L Table Read Protection bit (Block 2 code memory area)
1 = Block 2 is not protected from table reads executed in other blocks
0 = Block 2 is protected from table reads executed in other blocks
EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area)
1 = Block 1 is not protected from table reads executed in other blocks
0 = Block 1 is protected from table reads executed in other blocks
EBTR0 CONFIG7L Table Read Protection bit (Block 0 code memory area)
1 = Block 0 is not protected from table reads executed in other blocks
0 = Block 0 is protected from table reads executed in other blocks
EBTRB CONFIG7H Table Read Protection bit (Boot Block memory area)
1 = Boot Block is not protected from table reads executed in other blocks
0 = Boot Block is protected from table reads executed in other blocks
DEV<10:3> DEVID2 Device ID bits
These bits are used with the DEV<2:0> bits in the DEVID1 register to
identify the part number.
DEV<2:0> DEVID1 Device ID bits
These bits are used with the DEV<10:3> bits in the DEVID2 register to
identify the part number.
REV<4:0> DEVID1 Revision ID bits
These bits are used to indicate the revision of the device.
Note 1: The BBSIZ bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or
WRT0, EBTRB or EBTR0.
2: Available on PIC18F6XKXX devices only.
3: This bit must be maintained as ‘0’ on 28-pin PIC18F2XK80 and 40-pin PIC18F4XK80 devices.

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PIC18FXXK80 FAMILY
5.3 Embedding Configuration Word 5.5 Checksum Computation
Information in the HEX File The checksum is calculated by summing the following:
To allow portability of code, a PIC18FXXK80 device • The contents of all code memory locations
programmer is required to read the Configuration Word • The Configuration Word, appropriately masked
locations from the hex file. If Configuration Word
• ID locations.
information is not present in the hex file, then a simple
warning message should be issued. Similarly, while The Least Significant 16 bits of this sum are the
saving a hex file, all Configuration Word information checksum.
must be included. An option to not include the Configu- Table 5-4 (starting on Page 41) describes how to
ration Word information may be provided. When calculate the checksum for each device. For these
embedding Configuration Word information in the hex examples, the ID memory has been set to ‘Use Unpro-
file, it should start at address, 300000h. tected Checksum’ in MPLAB IDE®. Please use this
Microchip Technology Inc. feels strongly that this value to determine the value of the ‘SUM(IDs)’ term for
feature is important for the benefit of the end customer. each appropriate code-protected example.
Note: The checksum calculation differs depend-
5.4 Embedding Data EEPROM ing on the code-protect setting. Since the
Information in the HEX File code memory locations read out differently
depending on the code-protect setting, the
To allow portability of code, a PIC18FXXK80 device
table describes how to manipulate the
programmer is required to read the data EEPROM
actual code memory values to simulate the
information from the hex file. If data EEPROM informa-
values that would be read from a protected
tion is not present, a simple warning message should
device. When calculating a checksum by
be issued. Similarly, when saving a hex file, all data
reading a device, the entire code memory
EEPROM information must be included. An option to
can simply be read and summed. The
not include the data EEPROM information may be
Configuration Word and ID locations can
provided. When embedding data EEPROM information
always be read.
in the hex file, it should start at address, F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.

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 PIC18FXXK80 FAMILY
TABLE 5-4: CHECKSUM COMPUTATION
0xAA at 0
Blank
Device Code-Protect Checksum and Max
Value
Address

None SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + 0x0490 0x03E6

SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=8F & 8F) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 0x145D 0x1412
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=8F & 8F) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18F66K80 (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0x845A 0x840F
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=8F & 8F) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x044E 0x0458
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=8F & 8F) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
None SUM(0000:0FFF) + SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + 0x8490 0x83E6
SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=8F & 8F) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + 0x9465 0x941A
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=8F & 8F) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18F65K80 (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0xC462 0xC417
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=8F & 8F) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x0456 0x0460
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=8F & 8F) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)

 2011 Microchip Technology Inc. DS39972B-page 41

Free Datasheet http://www.Datasheet-PDF.com/

PIC18FXXK80 FAMILY
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Blank
Device Code-Protect Checksum and Max
Value
Address

None SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + 0x048A 0x03E0

SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 0x1460 0x1406
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18F46K80 (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0x845D 0x8403
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x0451 0x044C
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
None SUM(0000:0FFF) + SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + 0x848A 0x83E0
SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + 0x9468 0x940E
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18F45K80 (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0xC465 0xC40B
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x0459 0x0454
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)

DS39972B-page 42  2011 Microchip Technology Inc.

Free Datasheet http://www.Datasheet-PDF.com/

 PIC18FXXK80 FAMILY
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Blank
Device Code-Protect Checksum and Max
Value
Address

None SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + 0x048A 0x03E0

SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 0x1460 0x1406
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18F26K80 (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0x845D 0x8403
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x0451 0x044C
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
None SUM(0000:0FFF) + SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + 0x848A 0x83E0
SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + 0x9468 0x940E
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18F25K80
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0xC465 0xC40B
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x0459 0x0454
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)

 2011 Microchip Technology Inc. DS39972B-page 43

Free Datasheet http://www.Datasheet-PDF.com/

PIC18FXXK80 FAMILY
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Blank
Device Code-Protect Checksum and Max
Value
Address

None SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + 0x0490 0x03E6

SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=8F & 8F) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 0x145D 0x1412
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=8F & 8F) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18LF66K80 (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0x845A 0x840F
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=8F & 8F) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x044E 0x0458
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=8F & 8F) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
None SUM(0000:0FFF) + SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + 0x8490 0x83E6
SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=8F & 8F) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + 0x9465 0x941A
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=8F & 8F) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18LF65K80 (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0xC462 0xC417
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=8F & 8F) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x0456 0x0460
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=8F & 8F) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)

DS39972B-page 44  2011 Microchip Technology Inc.

Free Datasheet http://www.Datasheet-PDF.com/

 PIC18FXXK80 FAMILY
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Blank
Device Code-Protect Checksum and Max
Value
Address

None SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + 0x048A 0x03E0

SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 0x1460 0x1406
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18LF46K80 (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0x845D 0x8403
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x0451 0x044C
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
None SUM(0000:0FFF) + SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + 0x848A 0x83E0
SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + 0x9468 0x940E
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18LF45K80 (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0xC465 0xC40B
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x0459 0x0454
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)

 2011 Microchip Technology Inc. DS39972B-page 45

Free Datasheet http://www.Datasheet-PDF.com/

PIC18FXXK80 FAMILY
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Blank
Device Code-Protect Checksum and Max
Value
Address

None SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + 0x048A 0x03E0

SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 0x1460 0x1406
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18LF26K80 (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0x845D 0x8403
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x0451 0x044C
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
None SUM(0000:0FFF) + SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + 0x848A 0x83E0
SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) +
(CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0F & 0F) + (CONFIG5H=C0 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40)
Boot Block SUM(1000:1FFF) + SUM(2000:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + 0x9468 0x940E
2K word (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) +
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=0F & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
PIC18LF25K80
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
Boot/Panel0/ SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + 0xC465 0xC40B
Panel1 (CONFIG2L=7F & 7F) + (CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) +
(CONFIG3H=89 & 89) + (CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) +
(CONFIG5L=0C & 0F) + (CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) +
(CONFIG6H=E0 & E0) + (CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)
All (CONFIG1L=5D & 5D) + (CONFIG1H=08 & DF) + (CONFIG2L=7F & 7F) + 0x0459 0x0454
(CONFIG2H=7F & 7F) + (CONFIG3L=00 & 00) + (CONFIG3H=89 & 89) +
(CONFIG4L=91 & 91) + (CONFIG4H=00 & 00) + (CONFIG5L=00 & 0F) +
(CONFIG5H=80 & C0) + (CONFIG6L=0F & 0F) + (CONFIG6H=E0 & E0) +
(CONFIG7L=0F & 0F) + (CONFIG7H=40 & 40) + SUM(IDs)

DS39972B-page 46  2011 Microchip Technology Inc.

Free Datasheet http://www.Datasheet-PDF.com/

 PIC18FXXK80 FAMILY
6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: 25C is recommended

Param
Sym Characteristic Min Max Units Conditions
No.
D110 VIHH High-Voltage Programming Voltage on VDD + 1.5 9 V
MCLR/VPP/RE3
D111 VDD Supply Voltage during Programming 2.1 5.5 V Row Erase/Write for “F” parts
2.7 5.5 V Block Erase operations for
“F” parts
2.1 3.6 V Row Erase/Write for “LF”
parts
2.7 3.6 V Block Erase operations for
“LF” parts
D112 IPP Programming Current on MCLR/VPP/RE3 — 600 A
D113 IDDP Supply Current during Programming — 3.0 mA
D031 VIL Input Low Voltage VSS 0.2 VDD V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA @ 4.5V
D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA @ 4.5V
D012 CIO Capacitive Loading on I/O Pin (PGD) — 50 pF To meet AC specifications
P1 TR MCLR/VPP/RE3 Rise Time to Enter — 1.0 s (Note 1)
Program/Verify mode
P2 TPGC Serial Clock (PGC) Period 100 — ns VDD = 5.0V
1 — s VDD = 2.0V
P2A TPGCL Serial Clock (PGC) Low Time 40 — ns VDD = 5.0V
400 — ns VDD = 2.0V
P2B TPGCH Serial Clock (PGC) High Time 40 — ns VDD = 5.0V
400 — ns VDD = 2.0V
P3 TSET1 Input Data Setup Time to Serial Clock  15 — ns
P4 THLD1 Input Data Hold Time from PGC 15 — ns
P5 TDLY1 Delay between 4-Bit Command and Command 40 — ns
Operand
P5A TDLY1A Delay between 4-Bit Command Operand and Next 40 — ns
4-Bit Command
P6 TDLY2 Delay between Last PGC  of Command Byte to 20 — ns
First PGC  of Read of Data Word
P9 TDLY5 PGC High Time (minimum programming time) 1 — ms Externally timed
P9A TDLY5A PGC High Time 5 — ms Configuration Word
programming time
P10 TDLY6 PGC Low Time after Programming 100 — s
(high-voltage discharge time)
Note 1: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) +
2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only)
where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For
specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device.

 2011 Microchip Technology Inc. DS39972B-page 47

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PIC18FXXK80 FAMILY
6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
Standard Operating Conditions
Operating Temperature: 25C is recommended

Param
Sym Characteristic Min Max Units Conditions
No.
P11 TDLY7 Delay to allow Self-Timed Data Write or 5 — ms
Block Erase to Occur
P11A TDRWT Data Write Polling Time 4 — ms
P12 THLD2 Input Data Hold Time from MCLR/VPP/RE3  250 — s
P13 TSET2 VDD Setup Time to MCLR/VPP/RE3  100 — ns
P14 TVALID Data Out Valid from PGC  10 — ns
P15 TDLY8 Delay between Last PGC  and MCLR/VPP/RE3  0 — s
P16 THLD3 MCLR/VPP/RE3 to VDD  — 100 ns
P17 THLD3 MCLR/VPP/RE3 to VDD — 100 ns
Note 1: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) +
2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only)
where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For
specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device.

DS39972B-page 48  2011 Microchip Technology Inc.

Free Datasheet http://www.Datasheet-PDF.com/

 PIC18FXXK80 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (March 2010)
Original programming specification for the
PIC18FXXK80 family devices.

Revision B (January 2011)

Updated Section 2.3 “On-Chip Voltage Regulator”
with correct capacitor information. Updated Table 5-4
and Section 6.0 “AC/DC Characteristics Timing
Requirements for Program/Verify Test Mode”. Minor
grammatical corrections made throughout text.

 2011 Microchip Technology Inc. DS39972B-page 49

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PIC18FXXK80 FAMILY
NOTES:

DS39972B-page 50  2011 Microchip Technology Inc.

Free Datasheet http://www.Datasheet-PDF.com/

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code
conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

ISBN: 978-1-60932-837-5

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2011 Microchip Technology Inc. DS39972B-page 51

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08/04/10

DS39972B-page 52  2011 Microchip Technology Inc.

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