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Chapter 1: Overview
Architectural Overview
The Spartan-3 generation architecture consists of five fundamental programmable
functional elements:
• Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that
implement logic plus storage elements used as flip-flops or latches. CLBs perform a
wide variety of logical functions as well as store data.
• Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the
internal logic of the device. IOBs support bidirectional data flow plus 3-state
operation. Supports a variety of signal standards, including several high-performance
differential standards. Double Data-Rate (DDR) registers are included.
• Block RAM provides data storage in the form of 18-Kbit dual-port blocks.
• Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the
product. The Spartan-3A DSP platform includes special DSP multiply-accumulate
blocks.
• Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions
for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.
These elements are organized as shown in Figure 1-1, using the Spartan-3A FPGA array as
an example. A dual ring of staggered IOBs surrounds a regular array of CLBs in the
Spartan-3 and Extended Spartan-3A family. The Spartan-3E family has a single ring of
inline IOBs. Each block RAM column consists of several 18-Kbit RAM blocks. Each block
RAM is associated with a dedicated multiplier. The DCMs are positioned with two at the
top and two at the bottom of the device, plus additional DCMs on the sides for the larger
devices.
The Spartan-3 generation features a rich network of traces that interconnect all five
functional elements, transmitting signals among them. Each functional element has an
associated switch matrix that permits multiple connections to the routing.
36 www.xilinx.com Spartan-3 Generation FPGA User Guide
UG331 (v1.8) June 13, 2011
