R
Extended Spartan-3A Family Features
• Up to eight Digital Clock Managers (DCMs)
• Clock skew elimination (delay locked loop)
• Frequency synthesis, multiplication, division
• High-resolution phase shifting
• Wide frequency range (5 MHz to over 300 MHz)
• Eight global clocks, plus abundant low-skew routing
• Eight additional clocks per each half of the device
• Additional clock inputs for pinout flexibility and differential clocks
• Configuration interface to low-cost Xilinx Platform Flash with JTAG
• Configuration interface to industry-standard PROMs
• Low-cost, space-saving SPI serial Flash PROM
• x8 or x8/x16 parallel NOR Flash PROM
• Configuration watchdog timer automatically recovers from configuration errors
• Unique ID (Device DNA) in each device useful for copy protection algorithms
• Device DNA authentication restricts copying
• MultiBoot automatic reconfiguration between two files
• Complete Xilinx ISE® and WebPACK™ development system support
• Low-cost Starter Kit development systems and advanced demo boards
• 32-bit MicroBlaze™ and 8-bit PicoBlaze™ embedded processor cores
• Fully compliant 32-/64-bit 66 MHz PCI support
• PCI Express PIPE endpoint and other IP cores
• Supported by major EDA partners
• Low-cost QFP and BGA packaging options
• Common footprints support easy density migration within each platform (except
designs using the FT256 package)
• Pb-free (RoHS) packaging options
• Automotive XA platform variants
Spartan-3AN Platform Additional Features
• Integrated robust configuration memory
• Saves board space
• Improves ease-of-use
• Simplifies design
• Reduces support issues
• Plentiful amounts of non-volatile memory available to the user
• Up to 11+ Mb available
• MultiBoot support
• Embedded processing and code shadowing
• Scratchpad memory
• Robust 100K Flash memory program/erase cycles per page
• 20 years Flash memory data retention
Spartan-3 Generation FPGA User Guide www.xilinx.com 33
UG331 (v1.8) June 13, 2011
