HMC1190LP6GE

v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
Typical Applications Features
The HMC1190LP6GE is Ideal for: Broadband Operation with no external matching
• M
 ultiband/Multi-standard Cellular BTS Diversity High-side and Low-side LO injection Operation
Receivers High Input IP3 of +24 dBm
TRANSCEIVERS - Rx RFICs

• GSM & 3G & LTE/WiMAX/4G Power Conversion Gain of 8.9 dB

• MIMO Infrastructure Receivers Input P1dB of 11 dBm
• Wideband Radio Receivers SSB Noise Figure of 9 dB
• Multiband Basestations & Repeaters 55 dBc Channel-to-Channel Isolation
Enable/Disable Mixer and PLLVCO independently
Functional Diagram

TE
Single-ended RF input ports
Maximum Phase Detector Rate: 100 MHz
Low Phase Noise: -110 dBc/Hz in Band Typical
PLL FOM:
-230 dBc/Hz Integer Mode, -227 dBc/Hz Frac-
tional Mode
< 180 fs Integrated RMS Jitter (1 kHz to 20 MHz)
LE LO Low Noise Floor: -165 dBc/Hz
Mixer Low Noise Floor: -161 dBc/Hz
Integrated VCO
External VCO Input, differential LO output
Exact Frequency Mode:
0 Hz Fractional Frequency Error
SO
Programmable RF Output Phase
Output Phase Synchronous Frequency Changes
Output Phase Synchronization
LO Output Mute Function
Compact Solution, 6x6 mm Leadless QFN Package
General Description
The HMC1190LP6GE is a high linearity broadband dual channel downconverting mixer with integrated PLL and VCO
B

optimized for multi-standard receiver applications that require a compact, low power design. Integrated wideband
limiting LO amplifiers enable the HMC1190LP6GE to achieve an unprecedented RF bandwidth of 700 MHz to 3500
MHz for applications including Cellular/3G, LTE/WiMAX/4G. Unlike conventional narrow-band downconverters, the
HMC1190LP6GE supports both high-side and low-side LO injection over all RF frequencies. The RF and LO input
ports are internally matched to 50 Ohms.
O

The HMC1190LP6GE features an integrated LO and RF baluns, enable control of IF and LO amplifiers and bias con-
trol interface to high linearity passive mixer cores. Balanced passive mixer combined with high-linearity IF amplifier
architecture provides excellent LO-to-RF, LO-to-IF, and RF-to-IF isolations. Low noise figure of 9 dB, and high IIP3
of +24 dBm allow the HMC1190LP6GE to be used in most demanding applications. External bias control pins enable
optimization of already low power dissipation of 2.34 W (typical). Fast enable control interface reduces power con-
sumption further in TDD applications.

External VCO input allows the HMC1190LP6GE to lock external VCOs, and enables cascaded LO architectures for
MIMO applications. Two separate Charge Pump (CP) outputs enable separate loop filters optimized for both integrated
and external VCOs, and seamless switching between integrated or external VCOs during operation. Programmable
RF output phase features can further phase adjust and synchronize multiple HMC1190LP6GE’s enabling scalable
MIMO and beam-forming radio architectures.

Additional features include configurable LO output mute function, Exact Frequency Mode that enables the
HMC1190LP6GE to generate fractional frequencies with 0 Hz frequency error, and the ability to synchronously change
frequencies without changing phase of the output signal that increases efficiency of digital pre-distortion loops. The
HMC1190LP6GE is housed in RoHS compliant compact 6x6 mm leadless QFN package.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
1 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Table 1. Electrical Specifications, (Unless Otherwise Specified, the Following Test

Conditions Were Used) TA = +25°C, IF Frequency = 150 MHz, LO Power is set to ‘3’ [1],
RF Input Power = -5 dBm (-5 dBm / tone for 2-tone IP3 tests, ∆f = 1MHz), LOVDD=3VR-
VDD=DVDD3V=CHIPEN= 3V, VDDCP=VCS1=VCS2=VBIASIF1=VBIASIF2=LOBIAS1=LO-

TRANSCEIVERS - Rx RFICs
BIAS2=VCC1=VCC2=VGATE1=VGATE2=5V, VGATE = 4.8V.
Parameter Typical Units
Mixer Core RF Input Frequency Range 700 - 3500 MHz
Mixer Core IF Output Frequency Range 50 - 350 MHz
RF=1900 RF=2200 RF=2700

TE
RF=900 MHz[2]
MHz[3] MHz [3] MHz [3]
Conversion Gain 9.3 [5] 8.4 [5] 8.1 [5] 7.1 [5] dB
IP3 (Input) 24.5 24 23.5 23.5 dBm
Noise Figure (SSB) 8.5 9.2 9.5 10 dB
1 dB Compression (Input) 10.7 11.4 11.2 12 dBm
LO leakage @ RF port -67 -58 -59 -58 dBm
RF to IF Isolation
Channel to Channel Isolation [4]
+2RF-2LO Response
+3RF-3LO Response
[1] LO Power Level can be adjusted using Reg 16h.
LE 40
53
68
69
46
49
67
68
45
48
70
74
52
48
72
78
dB
dBc
dBc
dBc

[2] High Side LO injection, VGATE1,2 = 5V

[3] Low Side LO injection, VGATE1,2 = 4.8V
SO
[4] RF1 input power= -5 dBm, measurement taken from IF2 output. RF2 and IF1 ports are terminated with 50 Ohms.
[5] Balun losses at IF output ports are de-embedded.

Table 2. DC Power Supply Specifications

Parameter Min. Typ. Max. Units.
B

5 V Supply Rails (VDDCP, VCS1, VCS2, VDDLS, VBIASIF1, VBIASIF2, LOBIAS1, LOBIAS2, VCC1, +4.8 +5 +5.2 V
VCC2) 348 [1] mA
VGATE1, VGATE2 +4.5 +5 +5.2 V
O

+3.1 +3.3 +3.5 V

3.3 V Supply Voltage (LOVDD, 3VRVDD, DVDD3V, VCCPD, VCCPS, VCCHF)
198 mA
VDDIF (5 V) 160 mA
VCS1 + VCS2 (5 V) 3.3 4.2 mA
Mixer Core Supply Currents VBIASIF1 + VBIASIF2 (5 V) 24 28 mA
when IF1EN and IF2EN are
Enabled VGATE1, VGATE2 8 9.2 mA
LOBIAS1 + LOBIAS2 (5 V) 4.6 5.6 mA
LOVDD (3.3 V) 140 148 mA

[1] LO Frequency=2400 MHz, LO_MIX Power and LO_OUT Power set to ‘3’, LO_MIX and LO_OUT is differential and LO_OUT is off. When LO_OUT
enabled in differential mode the bias current increases by 34 mA (Typ.)

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 2
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Table 2. DC Power Supply Specifications

Parameter Min. Typ. Max. Units.
TRANSCEIVERS - Rx RFICs

Charge Pump (VDDCP, +5 V) +VCCLS 6 mA

LO_OUT differential, LO_MIXER off [1]

5 V Supplies (VDDLS, VCC1, VCC2, VDDCP) 148 mA
3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 58 mA

LO_OUT single-ended, LO_MIXER off [1]

5 V Supplies (VDDLS, VCC1, VCC2, VDDCP) 131 mA

TE
3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 58 mA

LO_OUT off, LO_MIXER differential [1]

5 V Supplies (VDDLS, VCC1, VCC2, VDDCP) 148 mA
PLL/VCO Core Supply 3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 58 mA
Currents when CHIPEN is
Enabled LO_OUT off, LO_MIXER single-ended [1]
5 V Supplies (VDDLS, VCC1, VCC2, VDDCP) 131 mA
3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 58 mA

LE
LO_OUT differential, LO_MIXER differential [1]
5 V Supplies (VDDLS, VCC1, VCC2, VDDCP)
3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD)

LO_OUT single-ended, LO_MIXER single-ended [1]

5 V Supplies (VDDLS, VCC1, VCC2, VDDCP)
182
58

150
mA
mA

mA
3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 58 mA
SO
VCCPD, VCCPS, VCCHF, DVDD3V, 3VRVDD (+3.3V) 58 64 mA

VDDIF (5V) 0 mA
VCS1 + VCS2 (5V) 4 mA
Mixer Core Supply Currents VBIASIF1 + VBIASIF2 (5V) 3.5 mA
when IF1EN and IF2EN are
Disabled VGATE1 + VGATE2 (5V) 4 mA
LOBIAS1 + LOBIAS2 (5V) 5.5 mA
LOVDD (3.3 V) 4 mA
B

PLL/VCO Core Supply VDDCP, VCC1, VCC2, VDDLS (5V) [1] 3 mA

Currents when CHIPEN is
Disabled 3VRVDD, DVDD3V, VCCPD, VCCPS, VCCHF (3.3V) [1] 1 mA

[1] LO Frequency=2400 MHz, LO_MIX and LO_OUT outputs set to maximum gain.
O

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
3 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Table 3. PLL & VCO Specifications

Parameter Conditions Min. Typ. Max. Units
Logic Inputs

TRANSCEIVERS - Rx RFICs
Logic High 1.2 V

Logic Low 0.6 V

Input Current +/- 1 uA

Input Capacitance 2 pF

LO Output Characteristics

TE
LO Output Frequency 50 4100 MHz

VCO Frequency at PLL Input 2000 4100 MHz

VCO Fundamental Frequency 2000 4100 MHz

VCO Output Divider

VCO Output Divider Range 1, 2, 4, ... 60, 62 1 62

PLL RF Divider Characteristics

19-Bit N Divider Range

Phase Detector (PD)

LE Integer

Fractional

Fractional Mode
16

20

DC
524287

524283

100 MHz
PD Frequency
Integer Mode DC 100 MHz
SO
Harmonics

fo Mode at 4000 MHz 2nd / 3rd / 4th -30/-22/-32 dBc

VCO Output Divider

VCO RF Divider Range 1,2,4,6,8,... 62 1 62

PLL RF Divider Characteristics

19-Bit N-Divider Range (Integer) Max = 219 - 1 16 524,287

Fractional nominal divide ratio

19-Bit N-Divider Range (Fractional) 20 524,283
B

varies (-3 / +4) dynamically max

REF Input Characteristics

Max Ref Input Frequency 350 MHz

Ref Input Voltage AC Coupled 1 2 3.3 Vpp

O

Ref Input Capacitance 5 pF

14-\Bit R-Divider Range 1 16,383

VCO Open Loop Phase Noise at fo @ 4 GHz

10 kHz Offset -78 dBc/Hz

100 kHz Offset -108 dBc/Hz

1 MHz Offset -134.5 dBc/Hz

10 MHz Offset -156 dBc/Hz

100 MHz Offset -167 dBc/Hz

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 4
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Table 3. PLL & VCO Specifications

Parameter Conditions Min. Typ. Max. Units
VCO Open Loop Phase Noise at fo @ 3 GHz/2 = 1.5 GHz
TRANSCEIVERS - Rx RFICs

10 kHz Offset -83 dBc/Hz

100 kHz Offset -113 dBc/Hz

1 MHz Offset -139.5 dBc/Hz

10 MHz Offset -165.5 dBc/Hz

100 MHz Offset -167 dBc/Hz

TE
Figure of Merit

Floor Integer Mode Normalized to 1 Hz -230 dBc/Hz

Floor Fractional Mode Normalized to 1 Hz -227 dBc/Hz

Flicker (Both Modes) Normalized to 1 Hz -268 dBc/Hz

VCO Characteristics

VCO Tuning Sensitivity at 3862 MHz Measured at 2.5 V 15 MHz/V

VCO Tuning Sensitivity at 3643 MHz

VCO Tuning Sensitivity at 3491 MHz

VCO Tuning Sensitivity at 3044 MHz

VCO Tuning Sensitivity at 2558 MHz

LE Measured at 2.5 V

Measured at 2.5 V

Measured at 2.5 V

Measured at 2.5 V
14.5

16.2

14.6

15.4
MHz/V

MHz/V

MHz/V

MHz/V

VCO Tuning Sensitivity at 2129 MHz Measured at 2.5 V 14.8 MHz/V

VCO Supply Pushing Measured at 2.5 V 2 MHz/V

SO

Table 4. Enable/Disable Settling Time Specifications

Parameter Conditions Min. Typ. Max. Units
Enable Settling Time Mixer Core Enabled 140 ns
Disable Settling Time Mixer Core Disabled 110 ns
B
O

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
5 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 1. Conversion Gain vs. VGATE [1] [2] Figure 2. Input IP3 vs. VGATE [1]
12 31

29

TRANSCEIVERS - Rx RFICs
10
CONVERSION GAIN (dB)

27
8
25

IIP3(dBm)
6 23

21
4
19

TE
2
17

0 15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

4.7 V 4.9 V 4.7 V 4.9 V

4.8 V 5.0 V 4.8 V 5 .0V

Figure 3. +2RF -2LO Response vs. VGATE[1]

100

90
LE Figure 4. +3RF -3LO Response vs. VGATE[1]
100

90
+2RF-2LO RESPONSE (dBc)

+3RF-3LO RESPONSE (dBc)

80 80

70 70
SO
60 60

50 50

40 40
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

4.7V 4.9V 4.7V 4.9V

B

4.8V 5.0V 4.8V 5.0V

Figure 5. Noise Figure vs. VGATE [1]

O

20

18

16
NOISE FIGURE (dB)

14

12

10

4
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz)

4.7V 4.9V
4.8V 5.0V

[1] VGATE is bias voltage for passive mixer cores (VGATE1 and VGATE2 pins). Refer to pin description table.
[2] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 6
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 6. Conversion Gain vs. High Side LO Figure 7. Input IP3 vs. High Side LO
& Low Side LO @ VGATE=4.8V [1] & Low Side LO @ VGATE=4.8V
12 31

29
TRANSCEIVERS - Rx RFICs

10
CONVERSION GAIN (dB)

27
8
25

IIP3 (dBm)
6 23

21
4
19

TE
2
17

0 15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

High Side LO Low Side LO High Side LO Low Side LO

Figure 8. RF/IF Isolation vs. Temperature

@ VGATE=4.8V
80

70
LE Figure 9. LO Leakage @ VGATE=4.8V
0

-20
60
LEAKAGE (dBm)
ISOLATION (dB)

50
-40
SO
40

30
-60

20

10 -80
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

+25C +85C -40C @ RF PORT @ IF PORT

B

Figure 10. Conversion Gain vs. LO Drive @

VGATE=4.8V [1] Figure 11. LO Drive @ VGATE=4.8V
O

12 31

29
10
CONVERSION GAIN (dB)

27
8
25
IIP3(dBm)

6 23

21
4
19
2
17

0 15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

LO Power Set to 0 LO Power Set to 2 LO Power Set to 0 LO Power Set to 2

LO Power Set to 1 LO Power Set to 3 LO Power Set to 1 LO Power Set to 3

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
7 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 12. +2RF -2LO Response vs. Figure 13. +3RF -3LO Response vs.
LO Drive @ VGATE=4.8V LO Drive @ VGATE=4.8V
100 100

TRANSCEIVERS - Rx RFICs
90 90
+2RF-2LO RESPONSE (dBc)

+3RF-3LO RESPONSE (dBc)

80 80

70 70

60 60

TE
50 50

40 40
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

LO Power Set to 0 LO Power Set to 2 LO Power Set to 0 LO Power Set to 2

LO Power Set to 1 LO Power Set to 3 LO Power Set to 1 LO Power Set to 3

Figure 14. RF Input Return Loss Figure 15. IF Output Return Loss
@ VGATE=4.8V [1]
0

-5
LE @ VGATE=4.8V [1]
0

-5
RETURN LOSS (dB)

RETURN LOSS (dB)

-10

-15
-10
SO
-20

-25
-15

-30

-35 -20
0.1 0.7 1.2 1.8 2.3 2.9 3.4 4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
FREQUENCY (GHz) FREQUENCY (GHz)

+25 C +85 C -40 C +25 C +85 C -40 C

B

Figure 16. Input P1dB vs. Temperature

@ VGATE=4.8V
O

20

15
P1dB (dBm)

10

0
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz)

+25C +85C -40C

[1] LO input Frequency = 1700MHz, LO power = 0 dBm.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 8
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 17. Conversion Gain vs. Figure 18. Input IP3 vs.
Temperature @ VGATE=5.0V [1] Temperature @ VGATE=5.0V
12 31

29
TRANSCEIVERS - Rx RFICs

10
CONVERSION GAIN (dB)

27
8
25

IIP3(dBm)
6 23

21
4
19

TE
2
17

0 15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

Figure 19. +2RF -2LO Response vs. Figure 20. +3RF -3LO Response vs.
Temperature @ VGATE=5.0V
100

90
LE Temperature @ VGATE=5.0V
100

90
+2RF-2LO RESPONSE (dBc)

+3RF-3LO RESPONSE (dBc)

80 80

70 70
SO
60 60

50 50

40 40
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

B

Figure 21. Noise Figure vs.

Temperature @ VGATE=5.0V
O

20

18

16
NOISE FIGURE (dB)

14

12

10

4
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz)

+25C +85C -40C

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
9 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 22. Conversion Gain vs. Figure 23. Input IP3 vs.
Temperature @ VGATE=4.9V [1] Temperature @ VGATE=4.9V
12 31

29

TRANSCEIVERS - Rx RFICs
10
CONVERSION GAIN (dB)

27
8
25

IIP3(dBm)
6 23

21
4
19

TE
2
17

0 15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

Figure 24. +2RF -2LO Response vs. Figure 25. +3RF -3LO Response vs.
Temperature @ VGATE=4.9V
100

90
LE Temperature @ VGATE=4.9V
100

90
+2RF-2LO RESPONSE (dBc)

+3RF-3LO RESPONSE (dBc)

80 80

70 70
SO
60 60

50 50

40 40
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

B

Figure 26. Noise Figure vs.

Temperature @ VGATE=4.9V
O

20

18

16
NOISE FIGURE (dB)

14

12

10

4
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz)

+25C +85C -40C

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 10
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 27. Conversion Gain vs. Figure 28. Input IP3 vs.
Temperature @ VGATE=4.8V [1] Temperature @ VGATE=4.8V
12 31

29
TRANSCEIVERS - Rx RFICs

10
CONVERSION GAIN (dB)

27
8
25

IIP3(dBm)
6 23

21
4
19

TE
2
17

0 15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

Figure 29. +2RF -2LO Response vs. Figure 30. +3RF -3LO Response vs.
Temperature @ VGATE=4.8V
100

90
LE Temperature @ VGATE=4.8V
100

90
+2RF-2LO RESPONSE (dBc)

+3RF-3LO RESPONSE (dBc)

80 80

70 70
SO
60 60

50 50

40 40
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

B

Figure 31. Noise Figure vs.

Temperature @ VGATE=4.8V
O

20

18

16
NOISE FIGURE (dB)

14

12

10

4
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz)

+25C +85C -40C

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
11 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 32. Conversion Gain vs. Figure 33. Input IP3 vs.
Temperature @ VGATE=4.7V [1] Temperature @ VGATE=4.7V
12 31

29

TRANSCEIVERS - Rx RFICs
10
CONVERSION GAIN (dB)

27
8
25

IIP3(dBm)
6 23

21
4
19

TE
2
17

0 15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

Figure 34. +2RF -2LO Response vs. Figure 35. +3RF -3LO Response vs.
Temperature @ VGATE=4.7V
100

90
LE Temperature @ VGATE=4.7V
100

90
+2RF-2LO RESPONSE (dBc)

+3RF-3LO RESPONSE (dBc)

80 80

70 70
SO
60 60

50 50

40 40
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

B

Figure 36. Noise Figure vs.

Temperature @ VGATE=4.7V
O

20

18

16
NOISE FIGURE (dB)

14

12

10

4
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz)

+25C +85C -40C

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 12
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 37. Channel to Channel Isolation vs. Figure 38. Channel to Channel Isolation vs.
VGATE IF Frequency
70 60
TRANSCEIVERS - Rx RFICs

65 55
ISOLATION (dB)

ISOLATION (dB)
60 50

55 45

50 40

TE
45 35

40 30
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

4.7 V 4.9 V IF=50MHz IF=250MHz

4.8 V 5.0 V IF=100MHz IF=300MHz
IF=150MHz IF=350MHz
IF=200MHz

Figure 39. Conversion Gain,

Channel Matching @ VGATE=4.8V [1]
12
LE Figure 40. Input IP3,
Channel Matching @ VGATE=4.8V
31

29
10
CONVERSION GAIN (dB)

27
8
25
SO
IIP3(dBm)

6 23

21
4
19
2
17

0 15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)
B

CHANNEL 1 CHANNEL 2 CHANNEL 1 CHANNEL 2

Figure 41. Conversion Gain vs. Figure 42. Input IP3 vs.
Vdd @ VGATE=4.8V [1] Vdd @ VGATE=4.8V
O

12 31

29
10
CONVERSION GAIN (dB)

27
8
25
IIP3(dBm)

6 23

21
4
19
2
17

0 15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)
VDD_IF=4.75V, VDD_LO=2.85V
VDD_IF=4.75V, VDD_LO=2.85V
VDD_IF=5.00V, VDD_LO=3.00V
VDD_IF=5.00V, VDD_LO=3.00V
VDD_IF=5.25V, VDD_LO=3.45V
VDD_IF=5.25V, VDD_LO=3.45V

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
13 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 43. Conversion Gain vs. IF Frequency Figure 44. IIP3 vs. IF Frequency
@ LO=850 MHz, VGATE=4.8V [1] @ LO=850 MHz, VGATE=4.8V
12 31

29

TRANSCEIVERS - Rx RFICs
10
CONVERSION GAIN (dB)

27
8
25

IIP3(dBm)
6 23

21
4
19

TE
2
17

0 15
0 100 200 300 400 500 600 700 0 100 200 300 400 500 600 700
FREQUENCY (MHz) FREQUENCY (MHz)

+25C +85C -40C +25C +85C -40C

Figure 45. Conversion Gain vs. IF Frequency

@ LO=1800 MHz, VGATE=4.8V [1]
12
LE Figure 46. IIP3 vs. IF Frequency
@ LO=1800 MHz, VGATE=4.8V
31

29
10
CONVERSION GAIN (dB)

27
8
25
SO
IIP3(dBm)

6 23

21
4
19
2
17

0 15
0 100 200 300 400 500 600 700 0 100 200 300 400 500 600 700
FREQUENCY (MHz) FREQUENCY (MHz)
B

+25C +85C -40C +25C +85C -40C

O

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 14
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
Figure 48. Auxiliary LO Output,
Figure 47. Auxiliary LO Output, Fractional Mode Closed Loop Phase Noise
Open Loop Phase Noise @ 3600 MHz @3600 MHz with various divider ratios [1]
-40 -80

-60
TRANSCEIVERS - Rx RFICs

-100
PHASE NOISE(dBc/Hz)

PHASE NOISE(dBc/Hz)
-80

-120
-100

-120
-140

-140
-160

TE
-160

-180 -180
1 10 100 1000 10000 100000 1 10 100 1000 10000 100000
OFFSET (KHz) OFFSET (KHz)
Div1 Div8 Div62
Div2 Div16
Div4 Div32

Figure 50. Auxiliary LO Output,

Figure 49. Auxiliary LO Output,
Open Loop Phase Noise @ 4100 MHz
-40

-60
LE Fractional Mode Closed Loop Phase Noise
@4100 MHz with various divider ratios [1]

-100
-80
PHASE NOISE(dBc/Hz)

PHASE NOISE(dBc/Hz)

-80

-120
-100
SO
-120
-140

-140
-160
-160

-180 -180
1 10 100 1000 10000 100000 1 10 100 1000 10000 100000
OFFSET (KHz) OFFSET (KHz)
Div1 Div8 Div62
Div2 Div16
B

Div4 Div32

Figure 51. Auxiliary LO Output,

Fractional Mode Closed Loop Phase Noise
@ 3300 MHz with various divider ratios [2]
O

-80

-100
PHASE NOISE(dBc/Hz)

-120

-140

-160

-180
1 10 100 1000 10000 100000
OFFSET (KHz)
Div1 Div8 Div62
Div2 Div16
Div4 Div32

[1] Using 122.88 MHz clock input, 61.44 MHz PFD, 2.5 mA CP, 174 uA Leakage.
[2] Using 100 MHz clock input, 50MHz PFD, 2.5 mA CP, 174 uA Leakage

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
15 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 52. Auxiliary LO Output, Figure 53. Auxiliary LO Output,

Open Loop Phase Noise vs. Frequency Open Loop Phase Noise vs. Temperature
-40 -100

-110
-60

TRANSCEIVERS - Rx RFICs
100 kHz Offset
PHASE NOISE(dBc/Hz)

-120
-80

PHASE NOISE (dBc/Hz)

-130
1 MHz Offset
-100
-140
-120
-150

-140
-160

TE
-160 -170

100 MHz Offset

-180 -180
1 10 100 1000 10000 100000 30 100 300 1000 4000

OFFSET (KHz) FREQUENCY (MHz)

3862.4 MHz 3044 MHz 27 C 85 C -40 C

3643.33 MHz 2558 MHz
3491.74 MHz 2129.4 MHz

Figure 54. Auxiliary LO Output Power

vs Temperature [1]
15

10
LE Figure 55. Integrated RMS Jitter [2]
INTEGRATED JITTER (ps)

0.25
0.3
OUTPUT POWER (dBm)

0.2
5
SO
0.15

0
0.1

-5
0.05

-10 0
100 1000 0 500 1000 1500 2000 2500 3000 3500 4000
OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz)

27C 85C -40C -40 C 27 C 85 C

B

Figure 57. Reference Input Sensitivity,

Figure 56. Typical VCO Sensitivity Square Wave, 50 Ω [3]
80 -220

70
O

-222

60
-224
KVCO (MHz/V)

50
FOM (dBc/Hz)

-226
40
-228
30
-230
20

10 -232

0 -234
0 1 2 3 4 5 -15 -12 -9 -6 -3 0 3
TUNING VOLTAGE (V)
REFERENCE POWER (dBm)
ML core, Tuning Cap 15 H core, Tuning Cap 7
14 MHz Square Wave 50 MHz Square Wave
MH core, Tuning Cap 7 CL core, Tuning Cap 15
25 MHz Square Wave 100 MHz Square Wave
L core, Tuning Cap 15 CH core, Tuning Cap 15

[1] Both Aux. LO and MOD LO Gain Set to ‘3’ (Max Level), both Aux. LO and MOD LO Buffer Enabled, measured from Auxiliary LO Port.
[2] RMS Jitter data is measured in fractional mode using 50 MHz reference frequency, from 1 kHz to 100 MHz integration bandwidth.
[3] Measured from a 50 Ω source with a 100 Ω external resistor termination. See PLL with Integrated RF VCOs Operating Guide Reference Input
Stage section for more details. Full FOM performance up to maximum 3.3 Vpp input voltage.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 16
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 58. Reference Input Sensitivity,

Sinusoid Wave, 50 Ω [1] Figure 59. Figure of Merit for PLL/VCO
-200 -200

NORMALIZED PHASE NOISE (dBc/Hz)

-205
TRANSCEIVERS - Rx RFICs

-210
-210
Typ FOM vs Offset
-215
FOM (dBc/Hz)

-220
FOM Floor
-220 FOM 1/f Noise

-225 -230

TE
-230

-235 -240
2 3 4 5 6
10 10 10 10 10
-20 -15 -10 -5 0 5
REFERENCE POWER (dBm) OFFSET (Hz)

14 MHz sin 50 MHz sin

25 MHz sin 100 MHz sin

Figure 60. Fractional-N Spurious Figure 61. Fractional-N Spurious

Performance @ 2646.96 MHz
Exact Frequency Mode ON [2]
-40

-60
LE Performance @ 2646.96 MHz
Exact Frequency Mode OFF [2]
-40

-60
PHASE NOISE(dBc/Hz)

PHASE NOISE(dBc/Hz)

-80 -80

-100 -100
SO
-120 -120

-140 -140

-160 -160

-180 -180
1 10 100 1000 10000 100000 1 10 100 1000 10000 100000
OFFSET (KHz) OFFSET (KHz)
B

Figure 63. Closed Loop Phase Noise With

Figure 62. Forward Transmission Gain [3] External VCO HMC384LP4E @ 2200 MHz
O

-40
20
FORWARD TRANMISSION GAIN (dB)

-60
S21 EXT-IN LO OUT DIFFERENTIAL OUTPUT
15
PHASE NOISE(dBc/Hz)

-80

10 -100

-120
5
-140
S21 EXT-IN LO OUT SINGLE-ENDED OUTPUT
0 -160

-180
-5
1 10 100 1000 10000
400 800 1200 1600 2000 2400 2800
OFFSET (KHz)
OUTPUT FREQUENCY (MHz)

[1] Measured from a 50 Ω source with a 100 Ω external resistor termination. See PLL with Integrated RF VCOs Operating Guide Reference Input Stage
section for more details. Full FOM performance up to maximum 3.3 Vpp input voltage.
[2] 122.88 MHz clock input, PFD = 61.44 MHz, Channel Spacing = 240 KHz.
[3] S21 from Ext_VCO (pin 43, 44) in and LO (pin32, 33) out.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
17 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Figure 64. Auxiliary LO Differential Output Figure 65. Auxiliary LO Single Ended Output
Return Loss Return Loss
0 0

TRANSCEIVERS - Rx RFICs
-5 -5
RETURN LOSS (dB)

RETURN LOSS (dB)

-10 -10

-15 -15

-20 -20

TE
-25 -25

-30 -30
100 1000 100 1000
OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz)

LE
SO

Table 5. Loop Filter Configuration

Loop Filter C1 C2 C3 C4 R2 R3 R4
Loop Filter Design
BW (kHz) (pF) (nF) (pF) (pF) (kΩ) (kΩ) (kΩ)
B
O

156 180 6.8 47 47 2.2 1 1

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 18
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Table 6. Harmonics of LO Table 7. MxN Spurious @ IF Port

nLO Spur @ RF Port nLO
TRANSCEIVERS - Rx RFICs

LO Freq. (GHz) 1 2 3 4 mRF 0 1 2 3 4

0.7 -65 -45 -67 -63 0 xx -44 -52 -52 -55
1.1 -80 -55 -64 -67 1 -49 0 -44 -17 -52
1.5 -59 -58 -65 -62 2 -87 -45 -72 -50 -80
1.9 -59 -54 -72 -64 3 -88 -62 -88 -71 -87
2.3 -60 -59 -73 -63 4 -85 -85 -88 -88 -87

TE
2.7 -59 -58 -82 -55 RF Freq. = 0.9 GHz @-5 dBm
LO Freq. = 0.8 GHz @ Max. level
3.1 -60 -58 -77 -48
All values in dBc below IF power level (1RF - 1LO).
3.5 -53 -63 -73 -48
LO = Max. level
All values in dBm measured at RF port.

Table 8. MxN Spurious @ IF Port

nLO
LE Table 9. MxN Spurious @ IF Port
nLO
mRF 0 1 2 3 4 mRF 0 1 2 3 4
0 xxx -44 -49 -64 -49 0 xxx -44 -47 -65 -53
SO
1 -54 0 -43 -28 -65 1 -58 0 -46 -40 -68
2 -83 -49 -76 -57 -84 2 -80 -60 -75 -67 -85
3 -87 -72 -86 -88 -85 3 -82 -82 -86 -83 -85
4 -83 -83 -85 -85 -87 4 -84 -82 -85 -85 -87
RF Freq. = 1.9 GHz @-5 dBm RF Freq. = 2.5 GHz @-5 dBm
LO Freq. = 1.8 GHz @ Max. level LO Freq. = 2.4 GHz @Max. level
All values in dBc below IF power level (1RF - 1LO). All values in dBc below IF power level (1RF - 1LO).
B
O

Table 10. Truth Table [1]

CHIPEN
PLL/VCO
(V)
LOW OFF
HIGH ON

[1] IF and LO amplifiers can be disabled through SPI bus. See `Enabling/Disabling Mixer Features` application section.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
19 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Table 11. Absolute Maximum Ratings Table 12. Recommended Operating Conditions
RF Input Power (VBIASIF1,2= +5V, VDDCP, VCS1, VCS2, VBIASIF1, VBIASIF2,LO-
+20 dBm
LOVDD=3.0V) BIAS1,LOBIAS2,VCC1,VCC2,VGATE1,VGATE2,VD- 5.0 V

TRANSCEIVERS - Rx RFICs
DLS
VBIASIF1,2, LOVDD 6V
LOVDD, 3VRVDD, DVDD3V, VCCPD, VCCPS,
VGATE1,2, VDDCP, VCS1, VCS2, +3.3 V
-0.3V to +5.5V VCCHF
LOVDD
Operating Temperature -40 to +85°C
3VRVDD, DVDD3V -0.3V to +3.6V
Max. Channel Temperature 150°C

TE
Thermal Resistance
3.3°C/W
(channel to ground paddle)
Storage Temperature -65 to 150°C
Operating Temperature -40 to +85°C
ESD Sensitivity (HBM) Class 1B

Outline Drawing LE
SO
B

NOTES:
1. PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC SILICA AND
SILICON IMPREGNATED.
O

2. LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY.

3. LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN
4. DIMENSIONS ARE IN INCHES [MILLIMETERS].
5. LEAD SPACING TOLERANCE IS NON-CUMULATIVE.
6. CHARACTERS TO BE HELVETICA MEDIUM, .025 HIGH, WHITE INK, OR LASER MARK
LOCATED APPROX. AS SHOWN.
7. P
 AD BURR LENGTH SHALL BE 0.15mm MAX. PAD BURR HEIGHT SHALL BE 0.05mm
MAX.
8. PACKAGE WARP SHALL NOT EXCEED 0.05mm
9. A LL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF
GROUND.
10. REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN.

Package Information
Part Number Package Body Material Lead Finish MSL Rating [2] Package Marking [1]
H1190
HMC1190LP6GE RoHS-compliant Low Stress Injection Molded Plastic 100% matte Sn MSL1
XXX
[1] 4-Digit lot number XXXX
[2] Max peak reflow temperature of 260 °C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 20
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Table 13. Pin Descriptions

Pin Number Function Description
1 VDDCP Power Supply for charge pump analog section.
TRANSCEIVERS - Rx RFICs

2 BIAS External bypass decoupling for precision bias circuits.

3,4 CP1,CP2 Charge Pump Outputs.
5 3VRVDD Reference supply, 3.3 V nominal.
6 XREFP Reference Input. DC bias is generated internally. Normally AC coupled externally.

7 DVDD3V DC Power Supply for Digital (CMOS) Circuitry, 3.3 V nominal.

TE
Bias control pins for IF amplifiers. Connect to 5V supply through 590 Ohms resistors. Refer to
8,23 VCS1, VCS2
application section for proper values of resistors to adjust IF amplifier current.
9 IF1_N

10 IF1_P
Differential IF outputs. Connect to 5V supply through choke inductors. See application circuit.
21 IF2_P

22 IF2_N

11, 20

12, 19

13, 18
VBIASIF1, VBI-
ASIF2
VGATE1,
VGAET2

RF1, RF2
LE Supply voltage pin for IF amplifier’s bias circuits.
Connect to 5V supply through filtering.

Bias pins for mixer cores. Set from 4.7V to 5.0V for operating frequency band.

RF input pins of the mixer, internally matched to 50 Ohms. RF input pins require off chip DC
blocking capacitors. See application circuit.
LO_BIAS2, Bias control pins for LO Amplifiers. Connect to 5V supply through 270 Ohms resistors. Refer to
14, 17
LO_BIAS1 application section for proper values of resistors to adjust LO amplifier current.
SO
15,24 RSV Reserved for internal use.Should be left floating.
3V bias supply for LO Drive stages. Refer to application circuit for appropriate filtering and bias
16 LOVDD
generation information.
25 CHIP_EN Chip Enable. Connect to logic high for normal operation.

26 LON Negative LO output used for single-ended, differential, or dual output mode.
Positive LO output used for differential or dual outputs only. While it can drive a separate load from
27 LOP
LO_N, it cannot be used when LO_N is disabled.
B

28 VCC1 VCO Analog supply1, 5.0V nominal.

29 VCC2 VCO Analog Supply 2, 5.0V nominal.

30 VTUNE VCO Varactor. Tuning Port Input.

31 SEN PLL Serial Port Enable (CMOS) Logic Input.

O

32 SDI PLL Serial Port Data (CMOS) Logic Input.

33 SCK PLL Serial Port Clock (CMOS) Logic Input.

34 LD/SDO Lock Detect, or Serial Data, or General Purpose (CMOS) Logic Output (GPO).

35 EXT_VC0_N External VCO negative input

36 EXT_VCO_P External VCO positive input.

37 VCCHF Analog supply, 3.3 V nominal

38 VCCPS Analog supply, Prescaler, 3.3 V nominal

39 VCCPD Analog supply, Phase Detector, 3.3 V nominal

40 VDDLS Analog supply, Charge Pump, 5.0 V nominal

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
21 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Evaluation PCB

TRANSCEIVERS - Rx RFICs
TE
LE
SO

The circuit board used in the application should use RF circuit design techniques. Signal lines should have
50 Ohm impedance while the package ground leads and exposed paddle should be connected directly to the
ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and
bottom ground planes. The evaluation circuit board shown is available from Hittite upon request.
B

Evaluation PCB Schematic

To view this Evaluation PCB Schematic please visit www.hittite.com and choose HMC1190LP6GE from the
O

“Search by Part Number” pull down menu to view the product splash page.

Table 14. Evaluation Order Information

Item Contents Part Number

Evaluation PCB Only HMC1190LP6GE Evaluation PCB Eval01-HMC1190LP6G [1]

HMC1190LP6GE Evaluation PCB

USB Interface Board
Evaluation Kit 6’ USB A Male to USB B Female Cable EKIT01-HMC1190LP6G [2]
CD ROM (Contains User Manual, Evaluation PCB Schematic, Evaluation Software,
Hittite PLL Design Software)

[1] Reference this number when ordering Evaluation PCB Only

[2] Reference this number when ordering an HMC1190LP6GE Evaluation KIt

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 22
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

1.0 Theory of Operation

The block diagram of HMC1190LP6GE PLL with Integrated VCO is shown in Figure 66
TRANSCEIVERS - Rx RFICs

TE
LE
Figure 66. HMC1190LP6GE PLL VCO Block Diagram
SO

1.1 PLL Overview

The PLL divides down the VCO output to the desired comparison frequency via the N-divider (integer value
set in Reg 03h, fractional value set in Reg 04h), compares the divided VCO signal to the divided reference
signal (reference divider set in Reg 02h) in the Phase Detector (PD), and drives the VCO tuning voltage
via the Charge Pump (CP) (configured in Reg 09h) to the VCO subsystem. Some of the additional PLL
subsystem functions include:
B

• Delta Sigma configuration (Reg 06h)

• Exact Frequency Mode (Configured in Reg 0Ch, Reg 06h,Reg 03h, and Reg 04h)
• Lock Detect (LD) Configuration (Reg 07h to configure LD, and Reg 0Fh to configure LD_SDO output
pin)
O

• External CEN pin used as hardware enable pin.

Typically, only writes to the divider registers (integer part Reg 03h, fractional part Reg 04h,VCO Divide
Ratio part Reg 04h) are required for HMC1190LP6GE output frequency changes.
Divider registers of the PLL (Reg 03h, and Reg 04h), set the fundamental frequency (2050 MHz to 4100
MHz) of the VCO. Output frequencies ranging from 33 MHz to 2050 MHz are generated by tuning to the
appropriate fundamental VCO frequency (2050 MHz to 4100 MHz) by programming N divider (Reg 03h,
and Reg 04h), and programming the output divider (divide by 1/2/4/6.../60/62, programmed in Reg 16h) in
the VCO register.
For detailed frequency tuning information and example, please see “1.3.7 Frequency Tuning” section.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
23 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

1.2 VCO Overview

The VCO consists of a capacitor switched step tuned VCO and an output stage. In typical operation, the
VCO is programmed with the appropriate capacitor switch setting which is executed automatically by the

TRANSCEIVERS - Rx RFICs
PLL AutoCal state machine if AutoCal is enabled (Reg 0Ah[11] = 0, see section “1.2.1 VCO Calibration” for
more information). The VCO tunes to the fundamental frequency (2050 MHz to 4100 MHz), and is locked
by the CP output from the PLL subsystem. The VCO controls the output stage of the HMC1190LP6GE
enabling configuration of:
• VCO Output divider settings configured in Reg 16h (divide by 2/4/6...60/62 to generate frequencies

TE
from 33 MHz to 2050 MHz, or divide by 1 to generate fundamental frequencies between 2050 MHz
and 4100 MHz)
• Output gain settings (Reg 16h[7:6], Reg 16h[9:8])
• Single-ended or differential output operation (Reg 17h[9:8])
• Always Mute (Reg 16h[5:0])
• Mute when unlock (Reg 17h[7])

1.2.1 VCO Calibration

1.2.1.1 VCO Auto-Calibration (AutoCal)

LE
The HMC1190LP6GE uses a step tuned type VCO. A step tuned VCO is a VCO with a digitally selectable
capacitor bank allowing the nominal center frequency of the VCO to be adjusted or ‘stepped’ by switching
in/out VCO tank capacitors. A step tuned VCO allows the user to center the VCO on the required output
frequency while keeping the varactor tuning voltage optimized near the mid-voltage tuning point of the
SO
HMC1190LP6GE’s charge pump. This enables the PLL charge pump to tune the VCO over the full range
of operation with both a low tuning voltage and a low tuning sensitivity (kvco).
The VCO switches are normally controlled automatically by the HMC1190LP6GE using the Auto-Calibration
feature. The Auto-Calibration feature is implemented in the internal state machine. It manages the selection
of the VCO sub-band (capacitor selection) when a new frequency is programmed. The VCO switches may
also be controlled directly via register Reg 15h for testing or for other special purpose operation.
To use a step tuned VCO in a closed loop, the VCO must be calibrated such that the HMC1190LP6GE
B

knows which switch position on the VCO is optimum for the desired output frequency. The HMC1190LP6GE
supports Auto-Calibration (AutoCal) of the step tuned VCO. The AutoCal fixes the VCO tuning voltage at
the optimum mid-point of the charge pump output, then measures the free running VCO frequency while
searching for the setting which results in the free running output frequency that is closest to the desired
phase locked frequency. This procedure results in a phase locked oscillator that locks over a narrow
O

voltage range on the varactor. A typical tuning curve for a step tuned VCO is shown in Figure 67.Note how
the tuning voltage stays in a narrow range over a wide range of output frequencies such as fast frequency
hopping.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 24
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
5

TUNE VOLTAGE AFTER CALIBRATION (V)

4

3
TRANSCEIVERS - Rx RFICs

fmin fmax
0
1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900 4100 4300

TE
VCO FREQUENCY(MHz)

Calibrated at 85C, Measured at 85C

Calibrated at 85C, Measured at -40C
Calibrated at -40C, Measured at -40C
Calibrated at -40C, Measured at 85C
Calibrated at 27C, Measured at 27C

Figure 67.Typical VCO Tuning Voltage After Calibration

The calibration is normally run automatically once for every change of frequency. This ensures optimum
selection of VCO switch settings vs. time and temperature. The user does not normally have to be concerned
LE
about which switch setting is used for a given frequency as this is handled by the AutoCal routine. The
accuracy required in the calibration affects the amount of time required to tune the VCO. The calibration
routine searches for the best step setting that locks the VCO at the current programmed frequency, and
ensures that the VCO will stay locked and perform well over it’s full temperature range without additional
calibration, regardless of the temperature that the VCO was calibrated at.
Auto-Calibration can also be disabled allowing manual VCO tuning. Refer to section 1.2.1.5 for a descrip-
tion of manual tuning.
SO

1.2.1.2 Auto-reLock on Lock Detect Failure

It is possible by setting Reg 0Ah[17] to have the VCO subsystem automatically re-run the calibration
routine and re-lock itself if Lock Detect indicates an unlocked condition for any reason. With this option the
system will attempt to re-Lock only once.

1.2.1.3 VCO AutoCal on Frequency Change

B

Assuming Reg 0Ah[11]=0, the VCO calibration starts automatically whenever a frequency change is
requested. If it is desired to rerun the AutoCal routine for any reason, at the same frequency, simply rewrite
the frequency change with the same value and the AutoCal routine will execute again without changing
final frequency.
O

1.2.1.4 VCO AutoCal Time & Accuracy

The VCO frequency is counted for Tmmt, the period of a single AutoCal measurement cycle.
n
Tmmt = Txtal · R · 2 (EQ 1)

n is set by Reg 0Ah[2:0] and results in measurement periods which are multiples of the PD
period, TxtalR.
R is the reference path division ratio currently in use, Reg 02h
Txtal is the period of the external reference (crystal) oscillator.

The VCO AutoCal counter will, on average, expect to register N counts, rounded down (floor) to the nearest
integer, every PD cycle.

N is the ratio of the target VCO frequency, fvco, to the frequency of the PD, fpd, where N can

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
25 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
be any rational number supported by the N divider.
N is set by the integer (Nint = Reg 03h) and fractional (Nfrac = Reg 04h) register contents
24
N = Nint + Nfrac / 2 (EQ 2)

TRANSCEIVERS - Rx RFICs
The AutoCal state machine runs at the rate of the FSM clock, TFSM, where the FSM clock frequency cannot
be greater than 50 MHz.
m
TFSM = Txtal · 2 (EQ 3)
m is 0, 2, 4 or 5 as determined by Reg 0Ah[14:13]
The expected number of VCO counts, V, is given by

TE
n
V = floor (N · 2 ) (EQ 4)

The nominal VCO frequency measured, fvcom, is given by

n
fvcom = V · fxtal / (2 · R) (EQ 5)
where the worst case measurement error, ferr , is:

LE ferr ≈ ±fpd / 2
n+1
(EQ 6)
SO

Figure 68. VCO Calibration

A 5-bit step tuned VCO, for example, nominally requires 5 measurements for calibration, worst case 6
measurements, and hence 7 VSPI data transfers of 20 clock cycles each. Total calibration time, worst
case, is given by:
B

n
Tcal = k128TFSM + 6TPD 2 + 7 · 20TFSM (EQ 7)

or equivalently
O

n m
Tcal = Txtal (6R · 2 + (140+(3 · 128)) · 2 ) (EQ 8)
For guaranteed hold of lock, across temperature extremes, the resolution should be better than
1/8th the frequency step caused by a VCO sub-band switch change. Better resolution settings will show
no improvement.

1.2.1.4.1VCO AutoCal Example

The HMC1190LP6GE must satisfy the maximum fpd limited by the two following conditions:
a. N ≥ 16 (fint), N ≥ 20.0 (ffrac), where N = f VCO/ fpd
b. fpd ≤ 100 MHz

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 26
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Suppose the HMC1190LP6GE output frequency is to operate at 2.01 GHz. Our example crystal frequency
is fxtal = 50 MHz, R=1, and m=0 (Figure 68), hence TFSM = 20 ns (50 MHz). Note, when using AutoCal, the
maximum AutoCal Finite State Machine (FSM) clock cannot exceed 50 MHz (see Reg 0Ah[14:13]). The
FSM clock does not affect the accuracy of the measurement, it only affects the time to produce the result.
TRANSCEIVERS - Rx RFICs

This same clock is used to clock the 16 bit VCO serial port.
If time to change frequencies is not a concern, then one may set the calibration time for maximum accuracy,
and therefore not be concerned with measurement resolution.
Using an input crystal of 50 MHz (R=1 and fpd=50 MHz) the times and accuracies for calibration using
(EQ 6) and (EQ 8) are shown in Table 15 Where minimal tuning time is 1/8th of the VCO band spacing.

TE
Across all VCOs, a measurement resolution better than 800 kHz will produce correct results. Setting
m = 0, n = 5, provides 781 kHz of resolution and adds 8.6 µs of AutoCal time to a normal frequency hop.
Once the AutoCal sets the final switch value, 8.64 µs after the frequency change command, the fractional
register will be loaded, and the loop will lock with a normal transient predicted by the loop dynamics. Hence
as shown in this example that AutoCal typically adds about 8.6 µs to the normal time to achieve frequency
lock. Hence, AutoCal should be used for all but the most extreme frequency hopping requirements.

Table 15. AutoCal Example with Fxtal = 50 MHz, R = 1, m = 0

Control Value
Reg0Ah[2:0]
0
1
n

0
1
LE 2n

1
2
Tmmt
(µs)
0.02
0.04
Tcal
(µs)
4.92
5.04
Ferr Max

± 25 MHz
± 12.5 MHz
2 2 4 0.08 5.28 ± 6.25 MHz
3 3 8 0.16 5.76 ± 3.125 MHz
SO
4 5 32 0.64 8.64 ± 781 kHz
5 6 64 1.28 12.48 ± 390 kHz
6 7 128 2.56 20.16 ± 195 kHz
7 8 256 5.12 35.52 ± 98 kHz

1.2.1.5 Manual VCO Calibration for Fast Frequency Hopping

B

If it is desirable to switch frequencies quickly it is possible to eliminate the AutoCal time by calibrating
the VCO in advance and storing the switch number vs frequency information in the host. This can be
done by initially locking the HMC1190LP6GE on each desired frequency using AutoCal, then reading,
and storing the selected VCO switch settings. The VCO switch settings are available in Reg 15h[8:1] after
every AutoCal operation. The host must then program the VCO switch settings directly when changing
O

frequencies. Manual writes to the VCO switches are executed immediately as are writes to the integer and
fractional registers when AutoCal is disabled. Hence frequency changes with manual control and AutoCal
disabled, requires a minimum of two serial port transfers to the HMC1190LP6GE, once to set the VCO
switches, and once to set the PLL frequency.
If AutoCal is disabled Reg 0Ah[11]=1, the VCO will update its registers with the value written via Reg
15h[8:1] immediately.

1.2.2 Registers required for Frequency Changes in Fractional Mode

A large change of frequency, in fractional mode (Reg 06h[11]=1), may require Main Serial Port writes to:
1. The integer register intg, Reg 03h (only required if the integer part changes)
2. Manual VCO Tuning Reg 15h only required for manual control of VCO if Reg 0Ah[11]=1 (AutoCal
disabled)

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
27 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

3. VCO Divide Ratio and Gain Register

• Reg 16h[5:0] is required to change the VCO Output Divider value if needed.
• Reg 16h[10:6] is required to change the Output Gain if needed.
4. The fractional register, Reg 04h. The fractional register write triggers AutoCal if Reg 0Ah[11]=0, and

TRANSCEIVERS - Rx RFICs
is loaded into the Delta Sigma modulator automatically after AutoCal runs. If AutoCal is disabled, Reg
0Ah[11]=1, the fractional frequency change is loaded into the Delta Sigma modulator immediately
when the register is written with no adjustment to the VCO.
Small steps in frequency in fractional mode, with AutoCal enabled (Reg 0Ah[11]=0), usually only require a
single write to the fractional register. Worst case, 3 Main Serial Port transfers to the HMC1190LP6GE could
be required to change frequencies in fractional mode. If the frequency step is small and the integer part of

TE
the frequency does not change, then the integer register is not changed. In all cases, in fractional mode, it
is necessary to write to the fractional register Reg 04h for frequency changes.

1.2.3 Registers Required for Frequency Changes in Integer Mode

A change of frequency, in integer mode (Reg 06h[11]=0), requires Main Serial Port writes to:
1. VCO register
•
•
2. The integer register Reg 03h.
•
LE
Reg 15h only required for manual control of VCO if Reg 0Ah[11]=1 (AutoCal disabled)
Reg 16h is required to change the VCO Output Divider value if needed

In integer mode, an integer register write triggers AutoCal if Reg 0Ah[11]=0, and is loaded into
the prescaler automatically after AutoCal runs. If AutoCal is disabled, Reg 0Ah[11]=1, the integer
frequency change is loaded into the prescaler immediately when written with no adjustment
to the VCO. Normally changes to the integer register cause large steps in the VCO frequency,
hence the VCO switch settings must be adjusted. AutoCal enabled is the recommended method
SO
for integer mode frequency changes. If AutoCal is disabled (Reg 0Ah[11]=1), a prior knowledge of
the correct VCO switch setting and the corresponding adjustment to the VCO is required before
executing the integer frequency change.

1.2.4 VCO Output Mute Function

The HMC1190LP6GE features an intelligent output mute function with the capability to disable the VCO
output while maintaining the PLL and VCO subsystems fully functional. The mute function is automatically
controlled by the HMC1190LP6GE, and provides a number of mute control options including:
B

1. Always mute (Reg 16h[5:0] = 0d). This mode is used for manual mute control.
2. Automatically mute the outputs during VCO calibration (Reg 17h[7] = 1) that occurs during output
frequency changes.
O

This mode can be useful in eliminating any out of band emissions during freqeuncy changes, and ensuring
that the system emits only desired frequencies. It is enabled by writing Reg 17h[7] = 1. Typical isolation
when the HMC1190LP6GE is muted is always better than 60 dB, and is ~ 30 dB better than disabling the
output buffers of the HMC1190LP6GE via Reg 17h[5:4].

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 28
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.1 PLL Overview

2.1.1 Charge Pump (CP) & Phase Detector (PD)

TRANSCEIVERS - Rx RFICs

The Phase detector (PD) has two inputs, one from the reference path divider and one from the RF path
divider. When in lock these two inputs are at the same average frequency and are fixed at a constant
average phase offset with respect to each other. We refer to the frequency of operation of the PD as fpd.
Most formulae related to step size, delta-sigma modulation, timers etc., are functions of the operating
frequency of the PD, fpd. fpd is also referred to as the comparison frequency of the PD.
The PD compares the phase of the RF path signal with that of the reference path signal and controls the

TE
charge pump output current as a linear function of the phase difference between the two signals. The
output current varies linearly over a full ±2π radians (±360°) of input phase difference.

2.1.1.1 Charge Pump

A simplified diagram of the charge pump is shown in Figure 69. The CP consists of 4 programmable
current sources, two controlling the CP Gain (Up Gain Reg 09h[13:7], and Down Gain Reg 09h[6:0]) and

LE
two controlling the CP Offset, where the magnitude of the offset is set by Reg 09h [20:14], and the direction
is selected by Reg 09h [21]=1 for up and Reg 09h [22]=1 for down offset.
CP Gain is used at all times, while CP Offset is only recommended for fractional mode of operation.
Typically the CP Up and Down gain settings are set to the same value (Reg 09h[13:7] = Reg 09h[6:0]).
SO
B
O

Figure 69. Charge Pump Gain & Offset Control

2.1.1.1.1 Charge Pump Gain

Charge pump Up and Down gains are set by Reg 09h[13:7] and Reg 09h[6:0] respectively. The current gain
of the pump in Amps/radian is equal to the gain setting of this register divided by 2π.
Typical CP gain setting is set to 2 to 2.5 mA, however lower values can also be used. Values < 1 mA may
result in degraded Phase Noise performance.
For example, if both Reg 09h[13:7] and Reg 09h[6:0] are set to ‘50d’ the output current of each pump will
be 1 mA and the phase frequency detector gain kp = 1 mA/2π radians, or 159 µA/rad.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
29 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.1.1.1.2 Charge Pump Phase Offset

In Integer Mode, the phase detector operates with zero offset. The divided reference signal and the divided
VCO signal arrive at the phase detector inputs at the same time. Integer mode does not require any CP

TRANSCEIVERS - Rx RFICs
Offset current. When operating in Integer Mode simply disable CP offset in both directions (Up and down),
by writing Reg 09h[22:21] = ‘00’b and set the CP Offset magnitude to zero by writing Reg 09h[20:14]= 0.
In Fractional Mode CP linearity is of paramount importance. Any non-linearity degrades phase noise and
spurious performance.
In fractional mode, these non-linearities are eliminated by operating the PD with an average phase offset,
either positive or negative (either the reference or the VCO edge always arrives first at the PD ie. leads).

TE
A programmable CP offset current source is used to add DC current to the loop filter and create the desired
phase offset. Positive current causes the VCO to lead, negative current causes the reference to lead.
The CP offset is controlled via Reg 09h[20:14]. The phase offset is scaled from 0 degrees, that is the
reference and the VCO path arrive in phase, to 360 degrees, where they arrive a full cycle late.
The specific level of charge pump offset current Reg 09h[20:14] is provided in (EQ 9). It is also plotted in
Figure 70 vs. PD frequency for typical CP Gain currents.

where:
LE ( )
Required CP Offset = min  4.3 × 10−9 × FPD × ICP ,0.25 × ICP 
 
(EQ 9)

FPD: Comparison frequency of the Phase Detector (Hz)

ICP: is the full scale current setting (A) of the switching charge pump (set in Reg 09h[6:0], [13:7]
SO
700
CP Current = 2.5 mA
RECOMMENDED OFFSET CURRENT (uA)

600

500
CP Current = 2 mA
400

300
B

200 CP Current = 1 mA

100

0
O

0 20 40 60 80 100
PHASE DETECTOR FREQUENCY (MHz)

Recommended CP offset current vs PD frequency for typical

CP gain currents. Calculated using (EQ 9)
The required CP offset current should never exceed 25 % of the programmed CP current. It is recommended
to enable the Up Offset and disable the Down Offset by writing Reg 09h[22:21] = ‘10’b.
Operation with CP offset influences the required configuration of the Lock Detect function. Refer to the
description of Lock Detect function in section 1.3.5.
When operating with PD frequency >=80MHz, the CP Offset current should be disabled for the frequency
change and then re-enabled after the PLL has settled. If the CP Offset current is enabled during a frequency
change it may not lock.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 30
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.1.1.2 Phase Detector Functions

Phase detector register Reg 0Bhallows manual access to control special phase detector features.
Setting Reg 0Bh[5] = 0, masks the PD up output, which prevents the charge pump from pumping up.`
TRANSCEIVERS - Rx RFICs

Setting (Reg 0Bh[6]) = 0, masks the PD down output, which prevents the charge pump from pumping
down.
Clearing both Reg 0Bh[5] and Reg 0Bh[6] tri-states the charge pump while leaving all other functions
operating internally.
PD Force UP Reg 0Bh[9] = 1 and PD Force DN Reg 0Bh[10] = 1 allows the charge pump to be forced up

TE
or down respectively. This will force the VCO to the ends of the tuning range which can be useful in VCO
testing.

2.1.2 Reference Input Stage

LE
SO

Figure 70. Reference Path Input Stage

The reference buffer provides the path from an external reference source (generally crystal based) to
the R divider, and eventually to the phase detector. The buffer has two modes of operation controlled by
Reg 08h[21]. High Gain (Reg 08h[21] = 0), recommended below 200 MHz, and High frequency (Reg 08h[21]
B

= 1), for 200 to 350 MHz operation. The buffer is internally DC biased, with 100 Ω internal termination. For
50 Ω match, an external 100 Ω resistor to ground should be added, followed by an AC coupling capacitor
(impedance < 1 Ω), then to the XREFP pin of the part.
At low frequencies, a relatively square reference is recommended to keep the input slew rate high. At higher
O

frequencies, a square or sinusoid can be used. The following table shows the recommended operating
regions for different reference frequencies. If operating outside these regions the part will normally still
operate, but with degraded reference path phase noise performance.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
31 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Table 16. Reference Sensitivity Table

Square Input Sinusoidal Input
Reference Input Slew > 0.5V/ns Recommended Swing (Vpp) Recommended Power Range (dBm)

TRANSCEIVERS - Rx RFICs
Frequency
Recommended Min Max Recommended Min Max
(MHz)
< 10 YES 0.6 2.5 x x x
10 YES 0.6 2.5 x x x
25 YES 0.6 2.5 ok 8 15

TE
50 YES 0.6 2.5 YES 6 15
100 YES 0.6 2.5 YES 5 15
150 ok 0.9 2.5 YES 4 12
200 ok 1.2 2.5 YES 3 8

Input referred phase noise of the PLL when operating at 50 MHz is between -148 and -150 dBc/Hz at 10
kHz offset depending upon the mode of operation. The input reference signal should be 10 dB better than

2.1.3
LE
this floor to avoid deg­radation of the PLL noise contribution. It should be noted that such low levels are only
necessary if the PLL is the dominant noise contributor and these levels are required for the system goals.

Reference Path ’R’ Divider

The reference path “R” divider is based on a 14-bit counter and can divide input signals by values from 1
to 16,383 and is controlled via Reg 02h.
SO
2.1.4 RF Path ’N’ Divider
The main RF path divider is capable of average divide ratios between 219-5 (524,283) and 20 in fractional
mode, and 219-1 (524,287) to 16 in integer mode.

2.1.5 Lock Detect

The Lock Detect (LD) function indicates that the HMC1190LP6GE is indeed generating the desired
B

frequency. It is enabled by writing Reg 07h[11]=1. The HMC1190LP6GE provides LD indicator in one of
two ways:
• As an output available on the LD_SDO pin of the HMC1190LP6GE, (Configuration is required to use
the LD_SDO pin for LD purpose, for more information please see “1.8 Serial Port Open Mode” and
“1.3.5.3 Configuring LD_SDO Pin for LD Output” section).
O

• Or reading from Reg 12h[1], where Reg 12h[1] = 1 indicates locked and Reg 12h[1] = 0 indicates an
unlocked condition.
The LD circuit expects the divided VCO edge and the divided reference edge to appear at the PD within a
user specified time period (window), repeatedly. Either signal may arrive first, only the difference in arrival
times is significant. The arrival of the two edges within the designated window increments an internal
counter. Once the count reaches and exceeds a user specified value (Reg 07h[2:0]) the HMC1190LP6GE
declares lock.
Failure in registering the two edges in any one window resets the counter and immediately declares an
un-locked condition. Lock is deemed to be reestablished once the counter reaches the user specified
value (Reg 07h[2:0]) again.

2.1.5.1 Lock Detect Configuration

Optimal spectral performance in fractional mode requires CP current and CP offset current configuration
discussed in detail in section “1.3.1”.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 32
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

These settings in Reg 09h impact the required LD window size in fractional mode of operation. To function,
the required lock detect window size is provided by (EQ 10).

ICP Offset (
A)
TRANSCEIVERS - Rx RFICs

 1 
 + 2.66 × 10−9 (
sec )
+ 
 FPD ()Hz × ICP ( A) FPD ()
Hz 
LD Window (
seconds )
=  in Fractional Mode
2 (EQ 10)
1
LD Window (
seconds )
= in Integer Mode
2 × FPD
where:

TE
FPD: is the comparison frequency of the Phase Detector
ICP Offset : is the Charge Pump Offset Current Reg 09h[20:14]
ICP: is the full scale current setting of the switching charge pump Reg 09h[6:0], or Reg 09h[13:7]
If the result provided by (EQ 10) is equal to 10 ns Analog LD can be used (Reg 07h[6] = 0). Otherwise
Digital LD is necessary Reg 07h[6] = 1.
Table 17 provides the required Reg 07h settings to appropriately program the Digital LD window size. From
Table 17, simply select the closest value in the “Digital LD Window Size” columns to the one calculated in

LD Timer Speed
Reg07[9:8]
LE
(EQ 10) and program Reg 07h[9:8] and Reg 07h[7:5] accordingly.

Table 17. Typical Digital Lock Detect Window

Digital Lock Detect Window Size
Nominal Value (ns)
Fastest 00 6.5 8 11 17 29 53 100 195
01 7 8.9 12.8 21 36 68 130 255
SO
10 7.1 9.2 13.3 22 38 72 138 272
Slowest 11 7.6 10.2 15.4 26 47 88 172 338
LD Timer Divide Setting
000 001 010 011 100 101 110 111
Reg07[7:5]

2.1.5.2 Digital Window Configuration Example

Assuming, fractional mode, with a 50 MHz PD and
B

• Charge Pump gain of 2 mA (Reg 09h[13:7] = 64h, Reg 09h[6:0] = 64h),

• Down Offset (Reg 09h[22:21] = ‘10’b)
• Offset current magnitude of +400 µA (Reg 09h[20:14] = 50h)
Applying (EQ 11), the required LD window size is:
O

 0.4 x10−3 ( A) 1 
 + 2.66 × 10−9 (
sec )
+  (EQ 11)
 50 × 106 ()
Hz × 2 x10 −3
()
A 50 × 10 6
()
Hz 
LD Window ( 
seconds ) =  13.33 nsec
2

Locating the Table 17 value that is closest to the (EQ 11) result, in this case 13.3 ≈ 13.33. To set the Digital
LD window size, simply program Reg 07h[9:8] = ‘10’b and Reg 07h[7:5] = ‘010’b according to Table 17.
There is always a good solution for the lock detect window for a given operating point. The user should
understand however that one solution does not fit all operating points. As observed from (EQ 11), If charge
pump offset or PD frequency are changed significantly then the lock detect window may need to be
adjusted.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
33 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.1.5.3 Configuring LD_SDO Pin for LD Output

Setting Reg 0Fh[4:0]=1 will display the Lock Detect Flag on LD_SDO pin of the HMC1190LP6GE. If
locked, LD_SDO will be high. As the name suggests, LD_SDO pin is multiplexed between LD and SDO

TRANSCEIVERS - Rx RFICs
(Serial Data Out) signals. Hence LD is available on the LD_SDO pin at all times except when a serial port
read is requested, in which case the pin reverts temporarily to the Serial Data Out pin, and returns to the
Lock Detect Flag after the read is completed.
LD can be made available on LD_SDO pin at all times by writing Reg 0Fh[6] = 1. In that case the
HMC1190LP6GE will not provide any read-back functionality because the SDO signal is not available.

TE
2.1.6 Cycle Slip Prevention (CSP)
When changing VCO frequency and the VCO is not yet locked to the reference, the instantaneous
frequencies of the two PD inputs are different, and the phase difference of the two inputs at the PD varies
rapidly over a range much greater than ±2π radians. Since the gain of the PD varies linearly with phase
up to ±2π, the gain of a conventional PD will cycle from high gain, when the phase difference approaches
a multiple of 2π, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. The
output current from the charge pump will cycle from maximum to minimum even though the VCO has not
yet reached its final frequency. LE
The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the
cycle. This can make the VCO frequency actually reverse temporarily during locking. This phenomena is
known as cycle slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically.
Cycle Slipping increases the time to lock to a value greater than that predicted by normal small signal
Laplace analysis.
The HMC1190LP6GE PD features an ability to reduce cycle slipping during frequency tunning. The Cycle
SO
Slip Preven­tion (CSP) feature increases the PD gain during large phase errors.

2.1.7 Frequency Tuning

HMC1190LP6GE VCO subsystem always operates in fundamental frequency of operation (2050 MHz
to 4100 MHz). The HMC1190LP6GE generates frequencies below its fundamental frequency (33 MHz
to 2050 MHz) by tuning to the appropriate fundamental frequency and selecting the appropriate Output
Divider setting (divide by 2/4/6.../60/62) in Reg 16h[5:0].
B

The HMC1190LP6GE automatically controls frequency tuning in the fundamental band of operation, for
more information see “1.2.1 VCO Calibration”.
To tune to frequencies below the fundamental frequency range (<2050 MHz) it is required to tune the
HMC1190LP6GE to the appropriate fundamental frequency, then select the appropriate output divider
O

setting (divide by 2/4/6.../60/62) in Reg 16h[5:0].

2.1.7.1 Integer Mode

The HMC1190LP6GE is capable of operating in integer mode. For Integer mode set the following registers
a. Disable the Fractional Modulator, Reg 06h[11]=0
b. Bypass the Modulator circuit, Reg 06h[7]=1
In integer mode the VCO step size is fixed to that of the PD frequency. Integer mode typically has 3 dB
lower phase noise than fractional mode for a given PD operating frequency. Integer mode, however, often
requires a lower PD frequency to meet step size requirements. The fractional mode advantage is that
higher PD frequencies can be used, hence lower phase noise can often be realized in fractional mode.
Charge Pump offset should be disabled in integer mode Reg 09h[22:14] = 0h.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 34
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.1.7.1.1 Integer Frequency Tuning

In integer mode the digital Δ∑ modulator is shut off and the N divider (Reg 03h) may be programmed to any
integer value in the range 16 to 219-1. To run in integer mode configure Reg 06h as described, then program
TRANSCEIVERS - Rx RFICs

the integer portion of the frequency as explained by (EQ 12), ignoring the fractional part.
a. Disable the Fractional Modulator, Reg 06h[11] = 0
b. Bypass the delta-sigma modulator Reg 06h[7] = 1
c. To tune to frequencies (<2050 MHz), select the appropriate output divider valueReg 16h[5:0].

2.1.7.2 Fractional Mode

TE
The HMC1190LP6GE is placed in fractional mode by setting the following registers:
a. Enable the Fractional Modulator, Reg 06h[11]=1
b. Connect the delta sigma modulator in circuit, Reg 06h[7]=0

2.1.7.2.1 Fractional Frequency Tuning

This is a generic example, with the goal of explaining how to program the output frequency. Actual variables
are dependant upon the reference in use. LE
The HMC1190LP6GE in fractional mode can achieve frequencies at fractional multiples of the reference.
The frequency of the HMC1190LP6GE, fvco, is given by

fxtal
fvco = (Nint + Nfrac) = fint + ffrac (EQ 12)
R
SO
fout = fvco / k (EQ 13)

Where:
fout is the output frequency after any potential dividers.
k is 1 for fundamental, or k = 2,4,6,…58,60,62 depending on the selected output
divider value (Reg 16h[5:0])
Nint is the integer division ratio, Reg 03h, an integer number between 20 and
B

524,284
Nfrac is the fractional part, from 0.0 to 0.99999...,Nfrac=Reg 04h/224
R is the reference path division ratio, Reg 02h
O

fxtal is the frequency of the reference oscillator input

fpd is the PD operating frequency, fxtal /R

As an example:
fout 1402.5 MHz
k 2
fvco 2,805 MHz
fxtal = 50 MHz
R =1
fpd = 50 MHz
Nint = 56
Nfrac = 0.1

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
35 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Reg 04h = round(0.1 x 224) = round(1677721.6) = 1677722

50e6 1677722

TRANSCEIVERS - Rx RFICs
f VCO = (56 + ) = 2805 MHz + 1.192 Hz error (EQ 14)
1 224

f VCO
fout = = 1402.5 MHz + 0.596 Hz error (EQ 15)
2

TE
In this example the output frequency of 1402.5 MHz is achieved by programming the 19-bit binary value
of 56d = 38h into intg_reg in Reg 03h, and the 24-bit binary value of 1677722d = 19999Ah into frac_reg in
Reg 04h. The 0.596 Hz quantization error can be eliminated using the exact frequency mode if required.
In this example the VCO output fundamental 2805 MHz is divided by 2 (Reg 16h[5:0] = 2h) = 1402.5 MHz.

2.1.7.2.2 Exact Frequency Tuning

LE
Due to quantization effects, the absolute frequency precision of a fractional PLL is normally limited by
the number of bits in the fractional modulator. For example, a 24 bit fractional modulator has frequency
resolution set by the phase detector (PD ) comparison rate divided by 224. The value 224 in the denominator
is sometimes referred to as the modulus. Hittite PLLs use a fixed modulus which is a binary number. In
some types of fractional PLLs the modulus is variable, which allows exact frequency steps to be achieved
with decimal step sizes. Unfortunately small steps using small modulus values results in large spurious
outputs at multiples of the modulus period (channel step size). For this reason Hittite PLLs use a large
fixed modulus. Normally, the step size is set by the size of the fixed modulus. In the case of a 50 MHz PD
SO
rate, a modulus of 224 would result in a 2.98 Hz step resolution, or 0.0596 ppm. In some applications it is
necessary to have exact frequency steps, and even an error of 3 Hz cannot be tol­erated.
Fractional PLLs are able to generate exact frequencies (with zero frequency error) if N can be
exactly represented in binary (eg. N = 50.0,50.5,50.25,50.75 etc.). Unfortunately, some common
frequencies cannot be exactly represented. For example, Nfrac = 0.1 = 1/10 must be approximated as
round((0.1 x 224)/ 224 ) ≈ 0.100000024. At fPD = 50 MHz this translates to 1.2 Hz error. Hittite’s exact
frequency mode addresses this issue, and can eliminate quantization error by programming the channel
step size to FPD/10 in Reg 0Ch to 10 (in this example). More generally, this feature can be used whenever
B

the desired frequency, f VCO, can be exactly represented on a step plan where there are an integer number
of steps (<224) across integer-N boundaries. Mathematically, this situation is satisfied if:

 fPD 
mod  fgcd  0=
O

=
fVCOk where fgcd gcd(fVCO1, fPD ) and fgcd ≥  24 
(EQ 16)
  2
 

Where:
gcd stands for Greatest Common Divisor
fN = maximum integer boundary frequency < f VCO1
fPD = frequency of the Phase Detector
and f VCOk are the channel step frequencies where 0 < k < 224-1, As shown in Figure 71.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 36
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
TRANSCEIVERS - Rx RFICs

TE
Figure 71. Exact Frequency Tuning
Some fractional PLLs are able to achieve this by adjusting (shortening) the length of the Phase Accumulator
(the denominator or the modulus of the Delta-Sigma modulator) so that the Delta-Sigma modulator phase
LE
accumulator repeats at an exact period related to the interval frequency (f VCOk - f VCO(k-1)) in Figure 71.
Consequently, the shortened accumulator results in more frequent repeating patterns and as a result often
leads to spurious emissions at multiples of the repeating pattern period, or at harmonic frequencies of
f VCOk - f VCO(k-1). For example, in some applications, these intervals might represent the spacing between
radio channels, and the spurious would occur at multiples of the channel spacing.
The Hittite method on the other hand is able to generate exact frequencies between adjacent integer-N
boundaries while still using the full 24 bit phase accumulator modulus, thus achieving exact frequency
SO
steps with a high phase detector comparison rate, which allows Hittite PLLs to maintain excellent phase
noise and spurious performance in the Exact Frequency Mode.

2.1.7.2.3Using Hittite Exact Frequency Mode

If the constraint in (EQ 16) is satisfied, HMC1190LP6GE is able to generate signals with zero frequency error
at the desired VCO frequency. Exact Frequency Mode may be re-configured for each target frequency, or
be set-up for a fixed fgcd which applies to all channels.
B

2.1.7.2.4 Configuring Exact Frequency Mode For a Particular Frequency

1. Calculate and program the integer register setting Reg 03h = NINT = floor(f VCO/fPD), where the
floor function is the rounding down to the nearest integer. Then the integer boundary frequency
O

fN = NINT ∙ fPD
2. Calculate and program the exact frequency register value Reg 0Ch = fPD/fgcd, where
fgcd = gcd(f VCO,fPD)  24 
 2 (
fVCOk − fN )

3. Calculate and program the fractional register setting Reg 04h NFRAC = ceil  fPD , where ceil
 
is the ceiling function meaning “round up to the nearest integer.”  

Example: To configure the HMC1190LP6GE for exact frequency mode at fVCO = 2800.2 MHz where Phase
Detector (PD) rate fPD = 61.44 MHz Proceed as follows:
Check (EQ 16) to confirm that the exact frequency mode for this f VCO is possible.
 fPD 
=fgcd gcd(fVCO , fPD ) and fgcd ≥  
 224 
 

( )
fgcd = gcd 2800.2 × 106 ,61.44 × 106 = 120 × 103 >
61.44 × 106
224
= 3750

Since (EQ 16) is satisfied, the HMC1190LP6GE can be configured for exact frequency mode at
f VCO = 2800.2 MHz as follows:

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
37 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

f   2800.2 × 106 
1. NINT = Reg 03h = floor  VCO
=1 floor  = =
 45d 2Dh
   61.44 × 106 
 fPD   

fPD 61.44 × 106 61.44 × 106

TRANSCEIVERS - Rx RFICs
2. Reg 0Ch = = = = 3072 =d C00h
(
gcd (
fVCOk +1 − fVCOk )
, fPD ) ( 3
gcd 100 × 10 ,61.44 × 10 6 20000
)
3. To program Reg 04h, the closest integer-N boundary frequency fN that is less than the
desired VCO frequency f VCO must be calculated. fN = fPD ∙ NINT. Using the current example:
fN =fPD × NINT =45 × 61.44 × 106 =2764.8 MHz.

TE
Reg04h ceil 
Then=
 224 f
( 
VCO − fN 
=
 24
)
2
ceil 
(
2800.2 × 106 − 2764.8 × 106 
= =
 9666560
)
d 938000h

 fPD   61.44 × 106 
   

3.1.7.2.1 Hittite Exact Frequency Channel Mode

If it is desirable to have multiple, equally spaced, exact frequency channels that fall within
LE
the same interval (ie. fN ≤ f VCOk < fN+1) where f VCOk is shown in Figure 71 and 1 ≤ k ≤ 224,
it is possible to maintain the same integer-N (Reg 03h) and exact frequency register (Reg 0Ch) settings
and only update the fractional register (Reg 04h) setting. The Exact Frequency Channel Mode is possible
if (EQ 16) is satisfied for at least two equally spaced adjacent frequency channels, i.e. the channel step
size.
To configure the HMC1190LP6GE for Exact Frequency Channel Mode, initially and only at the beginning,
integer (Reg 03h) and exact frequency (Reg 0Ch) registers need to be programmed for the smallest f VCO
SO
frequency (f VCO1 in Figure 71), as follows:
1. Calculate and program the integer register setting Reg 03h = NINT = floor(f VCO1/fPD), where f VCO1 is
shown in Figure 71 and corresponds to minimum channel VCO frequency. Then the lower integer
boundary frequency is given by fN = NINT ∙ fPD.
2. Calculate and program the exact frequency register value Reg 0Ch = fPD/fgcd,
where fgcd = gcd((f VCOk+1 - f VCOk),fPD) = greatest common divisor of the desired equidistant channel
spacing and the PD frequency ((f VCOk+1 - f VCOk) and fPD).
B

Then, to switch between various equally spaced intervals (channels) only the fractional register (Reg 04h)
needs to be programmed to the desired VCO channel frequency f VCOk in the following manner:

 (
 224 f 
VCOk − fN  )
Reg 04h = NFRAC = ceil 
O

fPD  where fN = floor(f VCO1/fPD), and f VCO1, as shown in Figure 71, represents
 
 
the smallest channel VCO frequency that is greater than fN.

Example: To configure the HMC1190LP6GE for Exact Frequency Mode for equally spaced intervals of
100 kHz where first channel (Channel 1) = f VCO1 = 2800.200 MHz and Phase Detector (PD) rate fPD =
61.44 MHz proceed as follows:
First check that the exact frequency mode for this f VCO1 = 2800.2 MHz (Channel 1)
and f VCO2 = 2800.2 MHz + 100 kHz = 2800.3 MHz (Channel 2) is possible.
 fPD  f 
=
fgcd1 gcd(fVCO1, fPD ) and fgcd1 ≥  fgcd 2 gcd(fVCO2 , fPD ) and fgcd 2 ≥  PD
 and= 
 224   224 
   

( )
fgcd1 = gcd 2800.2 × 106 ,61.44 × 106 = 120 × 103 >
61.44 × 106
224
= 3750

2800.3 × 10 ,61.44 × 10 )
=gcd ( 6 6 3 61.44 × 106
fgcd 2 =20 × 10 > =3750
224

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 38
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

If (EQ 16) is satisfied for at least two of the equally spaced interval (channel) frequencies f VCO1,f VCO2 ,f VCO3 ,...
f VCON, as it is above, Hittite Exact Frequency Channel Mode is possible for all desired channel frequencies,
and can be configured as follows:
TRANSCEIVERS - Rx RFICs

f   6 
VCO1  floor  2800.2 × 10=
1. Reg 03h = floor  =
 fPD   61.44 × 106 
=
 45d 2Dh
   
fPD 61.44 × 106 61.44 × 106
2. Reg 0Ch = = = = 3072 =d C00h
gcd ((
fVCOk +1 − fVCOk )
, fPD ) ( 3
gcd 100 × 10 ,61.44 × 10 6 20000
)
where (f VCOk+1 - f VCOk) is the desired channel spacing (100 kHz in this example).

TE
3. To program Reg 04h the closest integer-N boundary frequency fN that is less than the smallest
channel VCO frequency f VCO1 must be calculated. fN = floor(f VCO1/fPD). Using the current example:

 2800.2 × 106 
fN =fPD × floor   =45 × 61.44 × 106 =2764.8 MHz Then
 61.44 × 106 
 

=Reg 04h ceil

= 
(VCO1 − fN )
 224 f

f


 for channel 1 where fVCO1 2800.2 MHz


 24
2
= ceil 
PD 


(
LE
2800.2 × 106 − 2764.8 × 106 
61.44 × 106
= =
 9666560d 938000h
)
 
 
4. To change from channel 1 (f VCO1 = 2800.2 MHz) to channel 2 (f VCO2 = 2800.3 MHz), only
Reg 04h needs to be programmed, as long as all of the desired exact frequencies f VCOk (Figure 71)
SO
fall between the same integer-N boundaries (fN < f VCOk < fN+1). In that case

Reg 04h = ceil 

 24
2 (
2800.3 × 106 − 2764.8 × 106 
= =
 9693867
)
d 93EAABh , and so on.
 61.44 × 106 
 

4.1.1 Seed Register

B

The start phase of the fractional modulator digital phase accumulator (DPA) may be set to any desired
phase relative to the reference frequency, The phase is programmed in Reg 1Ah, and Exact Frequency
Mode is required. Phase = 2π x Reg1Ah/(224) via the seed register Reg 1Ah[23:0]. The HMC1190LP6GE
will automatically reload the start phase (seed value) into the DPA every time a new fractional frequency is
selected. Certain zero or binary seed values may cause spurious energy correlation at specific frequencies.
O

For most cases a random, or non zero, non-binary start seed is recommended.

4.1 Soft Reset & Power-On Reset

The HMC1190LP6GE features a hardware Power on Reset (POR). All chip registers will be reset to default
states approximately 250 µs after power up.
The PLL subsystem SPI registers may also be soft reset by an SPI write to register Reg 00h.

4.2 Power Down Mode

Power down the HMC1190LP6GE by pulling CEN pin (pin 17) low (assuming no SPI overrides(Reg
01h[0]=1)). This will result in all analog functions and internal clocks disabled. Current consumption will
typically drop below 10 µA in Power Down state. The serial port will still respond to normal communication
in Power Down mode.
It is possible to ignore the CEN pin, by setting Reg 01h[0]=0. Control of Power Down Mode then comes
from the serial port register Reg 01h[1].
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
39 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

It is also possible to leave various blocks on when in Power Down (see Reg 01h), including:
a. Internal Bias Reference Sources Reg 01h[2]
b. PD Block Reg 01h[3]

TRANSCEIVERS - Rx RFICs
c. CP Block Reg 01h[4]
d. Reference Path Buffer Reg 01h[5]
e. VCO Path buffer Reg 01h[6]
f. Digital I/O Test pads Reg 01h[7]

To mute the output but leave the PLL and VCO locked please refer to 1.2.4 section.

TE
4.3 General Purpose Output (GPO) Pin
The PLL shares the LD_SDO (Lock-Detect/Serial Data Out) pin to perform various functions. While the
pin is most commonly used to read back registers from chip via the SPI, it is also capable of exporting a
variety of signals and real time test waveforms (including Lock Detect). It is driven by a tri-state CMOS
driver with ~200 Ω Rout. It has logic associated with it to dynamically select whether the driver is enabled,
and to decide which data to export from the chip.
LE
In its default configuration, after power-on-reset, the output driver is disabled, and only drives during
appropriately addressed SPI reads. This allows it to share the output with other devices on the same bus.
The pin driver is enabled if the chip is addressed - ie. The last 3 bits of SPI cycle = ‘000’b before the
rising edge of SEN. If SEN rises before SCK has clocked in an ‘invalid’ (non-zero) chip -address, the
HMC1190LP6GE will start to drive the bus.
The BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER will naturally switch away from the
SO
GPO data and export the SDO during an SPI read. To prevent this automatic data selection, and always
select the GPO signal, set “Prevent AutoMux of SDO” (Reg 0Fh[6] = 1). The phase noise performance at
this output is poor and uncharacterized. The GPO output should not be toggling during normal operation
because it may degrade the spectral performance.
Note that there are additional controls available, which may be helpful if sharing the bus with other devices:
• To disable the driver completely, set Reg 08h[5] = 0 (it takes precedence over all else).
• To disable either the pull-up or pull-down sections of the driver, Reg 0Fh[8] = 1 or Reg 0Fh[9] = 1
B

respectively.
Example Scenarios:
• Drive SDO during reads, tri-state otherwise (to allow bus-sharing)
• No action required.
O

• Drive SDO during reads, Lock Detect otherwise

• Set GPO Select Reg 0Fh [4:0] = ‘00001’b (which is default)
• Set “Prevent GPO driver disable” (Reg 0Fh[7] = 1)
• Always drive Lock Detect
• Set “ Prevent AutoMux of SDO” Reg 0Fh[6] = 1
• Set GPO Select Reg 0Fh[4:0]= 00001 (which is default)
• Set “Prevent GPO driver disable” (Reg 0Fh[7] = 1))
The signals available on the GPO are selected in Reg 0Fh[4:0].

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 40
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

4.4 Chip Identification

The chip id information may be read by reading the content of read only register, chip_ID in Reg 00h.
For HMC1190LP6GE, chip id is C7701Ah.
TRANSCEIVERS - Rx RFICs

4.5 SERIAL PORT Overview

The SPI protocol has the following general features:
a. 3-bit chip address , enable the use of up to 8 devices connected to the serial bus
b. Simultaneous Write/Read during the SPI cycle

TE
c. 5-bit address space
d. 3 wire for Write Only capability, 4 wire for Read/Write capability
Typical serial port operation can be run with SCLK at speeds up to 50 MHz.

4.5.1 Serial Port WRITE Operation

AVDD = DVDD = 3V, AGND = DGND = 0V

Table 18. SPI WRITE Timing Characteristics

Parameter
t1
t2
t3
LE Conditions
SDI setup time to SCLK Rising Edge
SCLK Rising Edge to SDI hold time
SEN low duration
Min.
3
3
10
Typ. Max Units
ns
ns
ns
t4 SEN high duration 10 ns
t5 SCLK 32 Rising Edge to SEN Rising Edge 10 ns
SO
t6 Recovery Time 10 ns
Max Serial port Clock Speed 50 MHz

A typical WRITE cycle is shown in Figure 72.

a. The Master (host) places 24-bit data, d23:d0, MSB first, on SDI on the first 24 falling edges of SCLK.
b. the slave (HMC1190LP6GE) shifts in data on SDI on the first 24 rising edges of SCLK
c. Master places 5-bit register address to be written to, r4:r0, MSB first, on the next 5 falling edges of SCLK
(25-29)
d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29).
B

e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32). Hittite
reserves chip address a2:a0 = 000 for HMC1190LP6GE.
f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCLK.
O

h. Slave registers the SDI data on the rising edge of SEN.

i. Master clears SEN to complete the WRITE cycle.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
41 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

TRANSCEIVERS - Rx RFICs
TE
Figure 72. Serial Port Timing Diagram - WRITE

4.5.2 Serial Port READ Operation

A typical READ cycle is shown in Figure 73.
LE
In general, the LD_SDO line is always active during the WRITE cycle. During any SPI cycle LD_SDO will
contain the data from the current address written in Reg 00h[4:0]. If Reg 00h[4:0] is not changed then the
same data will always be present on LD_SDO when an Open Mode cycle is in progress. If it is desired to
READ from a specific address, it is necessary in the first SPI cycle to write the desired address to Reg
00h[4:0], then in the next SPI cycle the desired data will be available on LD_SDO.
SO
An example of the two cycle procedure to read from any address follows:
a. The Master (host), on the first 24 falling edges of SCLK places 24-bit data, d23:d0, MSB first, on SDI
as shown in Figure 73. d23:d5 should be set to zero. d4:d0 = address of the register to be READ on
the next cycle.
b. the slave (HMC1190LP6GE) shifts in data on SDI on the first 24 rising edges of SCK
c. Master places 5-bit register address , r4:r0, (the READ ADDRESS register), MSB first, on the next 5
falling edges of SCK (25-29). r4:r0=00000.
B

d. Slave shifts the register bits on the next 5 rising edges of SCK (25-29).
e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCK (30-32). Chip
address is always ‘000’b.
f. Slave shifts the chip address bits on the next 3 rising edges of SCK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCK.
O

h. Slave registers the SDI data on the rising edge of SEN.

i. Master clears SEN to complete the the address transfer of the two part READ cycle.
j. If one does not wish to write data to the chip during the second cycle, then it is recommended to
simply rewrite the same contents on SDI to Register zero on the READ back part of the cycle.
k. Master places the same SDI data as the previous cycle on the next 32 falling edges of SCK.
l. Slave (HMC1190LP6GE) shifts the SDI data on the next 32 rising edges of SCK. On these same
edges, the slave places the desired read data (ie. data from the address specified in Reg 00h[4:0] of
the first cycle) on LD_SDO which automatically switches to SDO mode from LD mode, disabling the
LD output.
m. Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock
Detect on LD_SDO.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 42
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Table 19. SPI Read Timing Characteristics

Parameter Conditions Min. Typ. Max Units
t1 SDI setup time to SCK Rising Edge 3 ns
TRANSCEIVERS - Rx RFICs

t2 SCK Rising Edge to SDI hold time 3 ns

t3 SEN low duration 10 ns
t4 SEN high duration 10 ns
t5 SCK Rising Edge to SDO time 8.2ns+0.2ns/pF ns
t6 Recovery TIme 10 ns
t7 SCK 32 Rising Edge to SEN Rising Edge 10 ns

TE
LE
SO
B
O

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
43 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

TRANSCEIVERS - Rx RFICs
TE
LE
SO
B
O

Figure 73. Serial Port Timing Diagram - READ

For more information on using the GPO pin while in SPI Mode please see section 1.8 Serial Port Overview

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 44
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.0 PLL Register Map

2.1 Reg 00h ID Register (Read Only) DEFAULT C7701A h
TRANSCEIVERS - Rx RFICs

Bit Type Name Width Default Description

[23:0] RO chip_ID 24 C7701A Chip ID Number

2.2 Reg 00h Open Mode Read Address/RST Strobe Register (Write Only)
Bit Type Name Width Default Description
[4:0] WO Read Address 5 - (WRITE ONLY) Read Address for next cycle

TE
[5] WO Soft Reset 1 - (WRITE ONLY) Soft Reset - (set to 0 during operation)
[23:6] WO Not Defined 18 - Not Defined (set to write 0h)

2.3 Reg 01h Chip Enable Register DEFAULT 3h

Bit Type Name Width Default Description
1 = Chip enable via CHIP_EN pin, Reg 01h[0]=1 and
CHIP_EN pin low places the HMC1190LP6GE in Power
Down Mode
[0] R/W Chip Enable Pin Select
LE 1 1
0 = Chip enable via SPI - Reg 01h[0] = 0, CHIP_EN pin
ignored (see Power Down Mode description for more
details)
Controls Chip Enable (Power Down) if Reg 01h[0] =0
Reg 01h[0]=0 and Reg 01h[1]=1 - chip is enabled, CHIP_
EN pin don’t care
[1] R/W SPI Chip Enable 1 1
Reg 01h[0]=0 and Reg 01h[1]=0 - chip disabled, CHIP_EN
pin don’t care
SO
(see Power Down Mode description for more information)
keeps internal bias generators on, ignores Chip enable
[2] R/W Keep Bias On 1 0
control
[3] R/W Keep PFD Pn 1 0 keeps PFD circuit on, ignores Chip enable control
[4] R/W Keep CP On 1 0 keeps Charge Pump on, ignores Chip enable control
keeps Reference buffer block on, ignores Chip enable
[5] R/W Keep Reference Buffer ON 1 0
control
[6] R/W Keep VCO on 1 0 keeps VCO divider buffer on, ignores Chip enable control
B

[7] R/W Keep GPO Driver ON 1 0 keeps GPO output Driver ON, ignores Chip enable control
[9:8] R/W Reserved 2 0 reserved

2.4 Reg 02h REFDIV Register DEFAULT 1h

O

Bit Type Name Width Default Description

Reference Divider ’R’ Value (EQ 8)
[13:0] R/W rdiv 14 1 min 1
max max 214-1 = 3FFFh = 16383d

2.5 Reg 03h Frequency Register - Integer Part DEFAULT 19h

Bit Type Name Width Default Description
Divider Integer part, used in all modes, see (EQ 10)

Fractional Mode
min 20d
25d
[18:0] R/W Integer Setting 19 max 219 - 4 = 7FFFCh = 524,284d
19h
Integer Mode
min 16d
max 219-1 = 7FFFFh = 524,287d

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
45 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.6 Reg 04h Frequency Register - Fractional Part DEFAULT 0h

Bit Type Name Width Default Description
Divider Fractional part (24 bit unsigned) see Fractional

TRANSCEIVERS - Rx RFICs
Frequency
Tuning
Fractional Division Value = Reg4[23:0]/2^24
[23:0] R/W Fractional Setting 24 0
Used in Fractional Mode only

min 0
max 224-1 = FFFFFFh = 16,777,215d

TE
2.7 Reg 05h Reserved
Bit Type Name Width Default Description
[23:0] R/W Reserved 24 0 Reserved

2.8 Reg 06h Delta Sigma Modulator Register DEFAULT 30F0Ah

BIT

[1:0]

[3:2]
TYPE

R/W

R/W
NAME

Reserved

DSM Order
LEWidth

2
Default

2
Reserved, Program to 0h
DESCRIPTION

Select the Delta Sigma Modulator Type

0: 1st order
1: 2nd Order
2: 3rd Order - Recommended
3: Reserved
SO
0: Normal SPI Load - all register load on rising edge of SEN
1: Synchronous SPI - registers Reg 03h, Reg 04h , Reg 1Ah wait
to load synchronously on the next internal clock cycle.

Normally (When this bit is 0) SPI writes into the internal state
machines/counters happen asynchronously relative to the internal
[4] R/W Synchronous SPI Mode 1 0
clocks. This can create freq/phase disturbances if writing register
3, 4 or 1A. When this bit is enabled, the internal SPI registers are
loaded synchronously with the internal clock. This means that
the data in the SPI shifter should be held constant for at least 2
PFD clock periods after SEN is asserted to allow this retiming to
B

happen cleanly.
Exact Frequency Mode 1: Exact Frequency Mode Enabled
[5] R/W 1 0
Enable 0: Exact Frequency Mode Disabled
[6] R/W Reserved 1 0 Reserved
O

0: Use Modulator, Required for Fractional Mode,

1: Bypass Modulator, Required for Integer Mode
Note: When enabled fractional modulator output is ignored, but
[7] R/W Fractional Bypass 1 0
fractional modulator continues to be clocked if Reg 06h[11] =1.
This feature can be used to test the isolation of the digital frac-
tional modulator from the VCO output in integer mode.
1: loads the modulator seed (start phase) whenever the fractional
register (Reg 04h) is written
[8] R/W Autoseed EN 1 1
0: when fractional register (Reg 04h) write changes frequency,
modulator starts at previous value (phase)
[10:9] R/W Reserved 2 3 Reserved
Delta Sigma Modulator 0: Disable DSM, used for Integer Mode
[11] R/W 1 1
Enable 1: Enable DSM Core, required for Fractional Mode
48d
[23:12] R/W Reserved 12 Reserved
30h

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 46
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.9 Reg 07h Lock Detect Register DEFAULT 200844 h

Bit Type Name Width Default Description
lock detect window
TRANSCEIVERS - Rx RFICs

sets the number of consecutive counts of divided VCO that

must land inside the Lock Detect Window to declare LOCK
0: 5
1: 32
[2:0] R/W lkd_wincnt_max 3 4 2: 96
3: 256
4: 512
5: 2048

TE
6: 8192
7: 65535
[10:3] R/W Reserved 8 8 Reserved
0: LD disable
[11] R/W LD Enable 1 1
1: LD enable
[19:12] R/W Reserved 8 0 Reserved
0 to 1 transition triggers the training. Lock Detect Training

[20]

[21]
R/W

R/W
Lock Detect Training

CSP Enable
LE 9

1
0

1
is only required after changing Phase Detector frequency.
After changing PD frequency a toggle Reg 07h[20] from 0
to 1 retrains the Lock Detect.
Cycle Slip Prevention enable.
When enabled, if the phase error becomes larger than
approx 70% of the PFD period, the charge-pump gain is
increased by approx 6mA for the duration of the cycle..
[23:22] R/W Reserved 2 0 Reserved
SO
2.10 Reg 08h Analog EN Register DEFAULT 1BFFF h
Bit Type Name Width Default Description
[4:0] R/W Reserved 5 31d Reserved
0 - Pin LD_SDO disabled
1 - and RegFh[7]=1 , Pin LD_SDO is always driven, this is
GPO(General Purpose Output Pin required for use of GPO port
[5] R/W 1 1d
Enable)
1 - and RegFh[7]=0 LDO_SPI is off if chip address
B

not equal to ‘000’b, allowing a shared SPI with other

compatible parts
[9:6] R/W Reserved 4 15d Reserved
0: VCO Buffer and Prescaler Bias Disable
VCO Buffer and Prescaler
[10] R/W 1 1d 1: VCO Buffer and Prescaler Bias Enable
O

Bias Enable
Only applies to External VCO
[20:11] R/W Reserved 10 55d Reserved
[21] R/W High Frequency Reference 1 0 Program to 1 for XTAL > 200 MHz, 0 otherwise
Output Logic Level on LD/SDO pin
[22] R/W SDO Output Level 1 0d 0: 1.8 V Logic Levels
1: DVDD3V Logic Level
[23] R/W Reserved 1 0d Reserved

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
47 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.11 Reg 09h Charge Pump Register DEFAULT 547264 h

Bit Type Name Width Default Description
Charge Pump DN Gain Control 20 µA√step

TRANSCEIVERS - Rx RFICs
Affects fractional phase noise and lock detect settings
0d = 0 µA
100d
[6:0] R/W CP DN Gain 7 1d = 20 µA
64h
2d = 40 µA
...
127d = 2.54mA Default 2mA
Charge Pump UP Gain Control 20 µA per step

TE
Affects fractional phase noise and lock detect settings
0d = 0 µA
100d
[13:7] R/W CP UP Gain 7 1d = 20 µA
64h
2d = 40 µA
...
127d = 2.54mA Default 2mA
Charge Pump Offset Control 5 µA/step
Affects fractional phase noise and lock detect settings
0d = 0 µA
[20:14]

[21]
[22]
R/W

R/W
R/W
Offset Magnitude

Offset UP enable
Offset DN enable
LE 7

1
1
81d

0
1
1d = 5 µA
2d = 10 µA
...
127d = 635 µA Default 405µA
Sets Direction of Reg 09h[20:14] Up, 0- UP Offset Off
Sets Direction of Reg 09h[20:14] Down, 0- DN Offset Off
Only recommended with external VCOs and Active Loop
Filters. When enabled the HMC1190LP6GE increases CP
[23] R/W HiK charge pump Mode 1 0
SO
current by 3 mA, thereby improving phase noise perfor-
mance, and increasing loop bandwidth
B
O

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 48
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.12 Reg 0Ah VCO AutoCal Configuration Register DEFAULT 2046 h

Bit Type Name Width Default Description
Used by internlan AutoCal state machine
TRANSCEIVERS - Rx RFICs

R Divider Cycles
0-1
1-2
2-4
3-8
[2:0] R/W Vtune Resolution 3 6d 4 - 32
5 - 64
6 - 128

TE
7 - 256
div cycles for frequency measurement. Measurement
should last > 4 µsec.
Note: 1 does not work if R divider = 1.
[10:3] R/W Reserved 8 16d Reserved
0 = AutoCal Enabled
[11] R/W AutoCal Disable 1 0
1 = AutoCal disabled
[12] R/W Reserved 1 0 Reserved

[14:13] R/W FSM/VSPI Clock Select

LE 2 1
Set the AutoCal FSM and VSPI Clock (50 MHz maximum)
0: Input Crystal Reference
1: Input Crystal Reference/4
2: Input Crystal Reference/16
3: Input Crystal Reference/32
[16:15] R/W Reserved 2 0 Reserved
0: Does not attempt to relock if lock is lost
[17] R/W Auto relock - one Try 1 0 1: Attempts to relock if Lock Detect fails for any reason.
SO
Only tries once.
[23:18] R/W Reserved 5 0 Reserved
B
O

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
49 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.13 Reg 0Bh PD/CP Register DEFAULT 78061 h

BIT TYPE NAME Width Default DESCRIPTION

[3:0] R/W Reserved 4 1 Reserved

TRANSCEIVERS - Rx RFICs
Inverts the PD polarity (program to 0)
0- Use with a positive tuning slope VCO and Passive Loop Filter
(default when using internal VCO)
[4] R/W PD Phase Select 1 0
1- Use with a Negative Slope VCO or with an inverting Active Loop
Filter with a Positive Slope VCO (Only recommended when using an
External VCO, and an active loop filter)

TE
[5] R/W PD Up Output Enable 1 1 Enables the PD UP output, see also Reg 0Bh[9]
[6] R/W PD Down Output Enable 1 1 Enables the PD DN output, see also Reg 0Bh[10]
[8:7] R/W Reserved 2 0 Reserved, Program to 0d.

[9] R/W Force CP UP 1 0 Forces CP UP output on if CP is not forced down - Use for Test only

[10] R/W Force CP DN 1 0 Forces CP DN output on if CP is not forced up - Use for Test only

Force CP MId Rail - Use for Test only (if Force CP UP or Force CP
[11] R/W Force CP Mid Rail 1 0

[23:12] R/W Reserved

LE 12 120d
78h
DN are enabled they have precedence)

Reserved.

2.14 Reg 0Ch Exact Frequency Register

SO
BIT TYPE NAME Width Default DESCRIPTION

Comparison Frequency divided by the correction rate. Must be

an integer. Frequencies at exactly the correction rate will have
zero frequency error. Only works in modulator Mode B(3rd order
recommended modulator type in Reg06[3:2]). Reg 0Ch must be 0 if
[23:0] R/W Number of Channels per Fpd 24 0 using ohter DSM type
0: Disabled
1: Invalid
≥ 2 valid
B

max 224-1 = FFFFFFh = 16,777,215d

O

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 50
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.15 Reg 0Fh GPO Register

BIT TYPE NAME Width Default DESCRIPTION

Select signal to be output to SDO pin when enabled

TRANSCEIVERS - Rx RFICs

DEFAULT LOCK DETECT

0: Data from Reg0F[5]

1: Lock Detect Output
2. Lock Detect Trigger
3: Lock Detect Window Output
4: Ring Osc Test

TE
5. Pullup Hard from CSP
6. PullDN hard from CSP
7. Reserved
8: Reference Buffer Output
9: Ref Divider Output
10: VCO divider Output
11. Modulator Clock from VCO divider
12. Auxiliary Clock
[4:0] R/W GPO 5 1
13. Aux SPI Clock
14. Aux SPI Enable
LE 15. Aux SPI Data Out
16. PD DN
17. PD UP
18. SD3 Clock Delay
19. SD3 Core Clock
20. AutoStrobe Integer Write
21. Autostrobe Frac Write
22. Autostrobe Aux SPI
23. SPI Latch Enable
SO
24. VCO Divider Sync Reset
25. Seed Load Strobe
26.-29 Not Used
30. SPI Output Buffer En
31. Soft RSTB

[5] R/W GPO Test Data 1 0 1 - GPO Test Data when GPO_Select = 0

1- Outputs GPO data only

[6] R/W Prevent Automux SDO 1 0
0- Automuxes between SDO and GPO data

[7] R/W Reserved 1 0 Reserved

B

Program to 1 if external pull-ups are used on the SDO line

[8] R/W Disable PFET 1 0
(Prevents conflicts on the SPI bus)

Program to 1 if external pull-downs are used on the SDO line

[9] R/W Disable NFET 1 0
(Prevents conflicts on the SPI bus)
O

[23:10] R/W Reserved 14 0 Reserved

2.16 Reg 10h Tuning Register DEFAULT 80 h

BIT TYPE NAME Width Default DESCRIPTION

VCO selection resulting from AutoCalibration.

16d
[7:0] R VCO Tune Curve 8 0- maximum frequency
10h
‘1111 1111’b- minimum frequency

Indicates if the VCO tuning is in process

[8] R VCO Tuning Busy 1 0 1- Busy
0- Not Busy

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
51 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.17 Reg 11h SAR Register (Read Only)

BIT TYPE NAME Width Default DESCRIPTION

219 - 1d

TRANSCEIVERS - Rx RFICs
[18:0] R SAR Error Magnitude Count 19 SAR Error Magnitude Count
7FFFFh

SAR Error Sign

[19] R SAR Error Sign 1 0 0: positive
1: negative

[23:20] R Reserved 4 0 Reserved

TE
2.18 Reg 12h GPO/LD Register (Read Only)
BIT TYPE NAME Width Default DESCRIPTION

[0] R GPO Out 1 0 GPO Output

[1] R Lock Detect Out 1 0 Lock Detect Output

[23:2] R Reserved 22 7h Reserved

2.19
BIT
Reg 13h BIST Register (Read Only)
TYPE NAME
LE
Width Default

4697d
DESCRIPTION

[16:0] R Reserved 16 Reserved

1259h
SO
B
O

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 52
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.20 Reg 14h Auxiliary SPI Register

BIT TYPE NAME Width Default DESCRIPTION

1- Use the 3 outputs as an SPI port

TRANSCEIVERS - Rx RFICs

[0] R/W Aux SPI Mode 1 0

0- Use the 3 outputs as a static GPO port along with Reg 14h[3:1]

[3:1] R/W Aux GPO Values 3 0 3 Output values can be set indivually when Reg 10h [0] = 1
0- 1.8 V output out of the Auxiliary GPO pins when Reg 10h [0] = 1
[4] R/W Aux GPO 3.3 V 1 0
1- 3.3 V output out of the Auxiliary GPO pins when Reg 10h [0] = 1
[8:5] R/W Reserved 4 1 Reserved

TE
When set, CHIP_EN pin is used as a trigger for phase
synchronization. Can be used to synchronize multiple
[9] R/W Phase Sync 1 1 HMC1190LP6GE, or to along with the Reg 1Ah value to phase step
the output.
(Exact Frequency Mode must be enabled)

Option to send GPO multiplexed data (ex Lock Detect) to one of the
auxiliary outputs
0- None
[11:10] R/W Aux SPI GPO Output 2 0

[13:12] R/W Aux SPI Outputs

LE 2 0
1 - to [0]
2 - to [1]
3 - to [2]

When disabled:
0 - Outputs Hi Z
1 - Outputs stay driven
2 - Outputs driven to high
3 - Outputs driven to low
SO
[23:14] R/W Reserved 10 0 Reserved

2.21 Reg 15h Manual VCO Config Register Default F48A0 h

BIT TYPE NAME Width Default DESCRIPTION

1- VCO subsystem manual calibration enabled

[0] R/W Manual Calibration Mode 1 0
0- VCO subsystem manual calibration disabled

16d
[5:1] R/W Capacitor Switch Setting 5 capacitor switch setting
B

10h

[8:6] R/W Manual VCO Selection 3 2 selects the VCO core sub-band

1- Manual VCO tuning enabled

[9] R/W Manual VCO Tune Enable 1 0
0- Manual VCO tuning disabled
O

18d
[15:10] R/W Reserved 6 Reserved
12h

1 - Automatically scale CP current based on VCO frequency and

Enable Auto-Scale CP
[16] R/W 1 1 capacitor setting
current
0- Don’t scale CP current

[23:17] R/W Reserved 7 7d Reserved

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
53 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.22 Reg 16h Gain Divider Register Default 6C1 h

BIT TYPE NAME Width Default DESCRIPTION

0 - Mute, VCO and PLL buffer On, RF output stages Off

TRANSCEIVERS - Rx RFICs
1 - Fo
2 - Fo/2
3 - invalid, defaults to 2
4 - Fo/2
5 - invalid, defaults to 4
[5:0] R/W RF Divide Ratio 6 1
6 - Fo/6
...

TE
60 - Fo/60
61 - invalid, defaults to 60
62 - Fo/62
> 62 - invalid, defaults to 62

3 - Max Gain
LO Output Buffer Gain 2 - Max Gain - 3 dB
[7:6] R/W 2 3
Control 1 - Max Gain - 6 dB
0 - Max Gain - 9 dB

3 - Max Gain
[9:8]

[10]
R/W

R/W
LO2 Output Buffer gain
Control

Divider Output Stage Gain

Control
LE 2

1
2

1
2 - Max Gain - 3 dB
1 - Max Gain - 6 dB
0 - Max Gain - 9 dB

1 - Max Gain
0 - Max Gain - 3 dB

[23:11] R/W Reserved 13 0 Reserved

SO
B
O

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 54
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.23 Reg 17h Modes Register Default 1AB h

BIT TYPE NAME Width Default DESCRIPTION

Master enable for the entire VCO Subsystem

TRANSCEIVERS - Rx RFICs

1 - Enable
[0] R/W VCO SubSys Master Enable 1 1
0 - Disable
Chip Enable is also required to set as enable mode.

[1] R/W VCO Enable 1 1

External VCO Buffer to output stage enable. Only used when locking
[2] R/W External VCO Buffer Enable 1 0
an external VCO.

TE
[3] R/W PLL Buffer Enable 1 1 PLL Buffer Enable. Used when using an internal VCO.

[4] R/W LO1 Output Buffer Enable 1 0 Enables LO1 (LO_P & LO_N pins) output buffer.

[5] R/W LO2 Output Buffer Enable 1 1 Enables the LO2 (LO2_N & LO2_P pins) output buffer

[6] R/W External Input Enable 1 0 Enables External VCO input

[7] R/W Pre Lock Mute Enable 1 1 Mute both output buffers until the PLL is locked

Enables Single-Ended output mode for LO output

[8] R/W
LO1 Output Single-Ended
Enable
LE 1 1
1- Single-ended mode, LO_N pin is enabled, and LO_P pin is
disabled
0- Differential mode, both LO_N and LO_P pins enabled
Please note that single-ended output is only available on LO_N pin.

Enables Single-Ended output mode for LO2 output

1- Single-ended mode, LO2_N pin is enabled, and LO2_P pin is
LO2 Output Single-Ended
[9] R/W 1 0 disabled
Enable
0- Differential mode, both LO2_N and LO2_P pins enabled
Please note that single-ended output is only available on LO2_N pin.
SO
[10] R/W Reserved 1 0 Reserved

Connects CP to CP1 or CP2 output.

[11] R/W Charge Pump Output Select 1 0 0: CP1
1: CP2

[23:12] R/W Reserved 12 0 Reserved

2.24 Reg 18h Bias Register Default 54C1 h

B

BIT TYPE NAME Width Default DESCRIPTION

21697d
[18:0] R/W Reserved 19 Reserved
54C1h

External Input buffer BIAS

O

[19] R/W 1 0 External Input buffer BIAS bit0

bit0

External Input buffer BIAS

[20] R/W 1 0 External Input buffer BIAS bit1
bit1

[23:21] R/W Reserved 3 0 Reserved

2.25 Reg 19h Cals Register Default AAA h

BIT TYPE NAME Width Default DESCRIPTION

2730d
[23:0] R/W Reserved 2 Reserved. Program to AB2h.
AAAh

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
55 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

2.26 Reg 1Ah Seed Register Default B29D0Bh

BIT TYPE NAME Width Default DESCRIPTION

Used to program output phase relative to the reference frequency.

TRANSCEIVERS - Rx RFICs
(Exact Frequency Mode required). When not using Exact Frequency
Delta Sigma Modulator 11705611d Mode and Auto seed Enable Reg06h[8] =1, Reg1Ah sets the start
[23:0] R/W 24
Seed B29D0Bh phase of output signal. If AutoSeed disable Reg06h[8] =0, Reg1Ah
is the start phase of the signal after every frequency changel. (LO
Phase = 2π x Reg1Ah/(224)

TE
LE
SO
B
O

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 56
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

3.0 Application Information

The HMC1190LP6GE is a broadband dual channel, high dynamic range, high gain, low noise, high-
linearity down converting mixer with integrated Fractional-N Integer-N PLL and VCO, designed to
TRANSCEIVERS - Rx RFICs

cover RF frequencies from 700 MHz to 3.5 GHz. The HMC1190LP6GE`s low noise and high linearity
performance makes it suitable for a wide range of transmission standards, including TDD, FDD, LTE,
WiMAX, CDMA,GSM, MC-GSM, W-CDMA, UMTS, TD-SCDMA applications.
The HMC1190LP6GE offers an easy-to-use and complete frequency conversion solution for diversity and
MIMO receiver applications in a highly compact 6x6 mm plastic QFN package. The HMC1190LP6GE
greatly simplifies the design of diversity and MIMO receiver applications by increasing the integration level

TE
and reducing the number of required circuit elements thereby reducing cost, area, and power consumption.

3.1 Principle of Operation

HMC1190LP6GE’s single-ended RF inputs are converted into differential through the on-chip integrated
baluns. The single-ended RF inputs are internally broadband matched to 50 Ω and require only standard
DC-blocking capacitors.

LE
HMC1190LP6GE’s RF inputs can be externally matched for narrow band application frequencies with
a simple matching network including a series inductor, and a shunt capacitor to further improve the
performance. Please refer to the application circuit for narrow band RF input matching for the detailed
information.
The HMC1190LP6GE’s IF amplifiers are designed for differential 200 Ω output load impedance. A
few external components are required at these IF outputs for the broadband frequency response as
recommended in the application circuit.
SO
Refer to the IF output interface section for detailed information.
The HMC1190LP6GE requires 5V, 3.3V and 3V supply voltages and external bias voltages. Bias voltages
generate reference currents for the IF and LO amplifiers. 3.3V supply voltage and the external bias voltages
can be generated from 5V supply voltage to operate with a single supply. Please refer to the single supply
operation section for more information.
The reference currents to the IF and LO amplifiers can be disabled through SPI interface. See `Enabling /
Disabling Mixer Features` section for details.
B

3.2 Supply Number Reduction

The LOVDD, VCS1, VCS2, LOBIAS1, LOBIAS2, VGATE1 and VGATE2 pins of HMC1190LP6GE requires
O

different supply voltages.

Except LOVDD, other pin voltages i.e. VGATE1, VGATE2, LOBIAS1, LOBIAS2, VCS1, VCS2 voltages
are already generated from 5.5V supply voltage on evaluation board (see application circuit). These
bias voltages can be optimized by external resistors (VCS1, VCS2, LOBIAS1, LOBIAS2, VGATE1, and
VGATE2). The resistor values of VCS1, VCS2 on evaluation board are 590 Ohms. LOBIAS1 and LOBIAS2
series resistor values are 270 Ohms. Refer to the VCS Interface and LOBIAS Interface section for more
information.
On the evaluation board, VGATE1, VGATE2 pin voltages are 5V; however VGATE1, VGATE2 pin voltages
can be tuned between 4.7V and 5V for optimization of Input IP3 and conversion gain performances. After
VGATE1,VGATE2 pin voltages are optimized, these pin voltages can be generated from 5V supply by
changing the values of series resistors, R14 and R15. Refer to the VGATE interface section for more
information.
The 3 V supply voltage for the LO amplifiers can be generated from 5 V or 3.3 V supply voltages by adding

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
57 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

a series resistor (R_LOVDD) between LOVDD pin and supply voltage in the configuration shown in Figure
74.
If using a 5 V supply R_LOVDD = 14 Ω, and minimum power rating of R_LOVDD is 0.3 W

TRANSCEIVERS - Rx RFICs
If using a 3.3 V supply, R_LOVDD = 2.15 Ω, and minimum power of R_LOVDD is 0.05 W

TE
LE
Figure 74. Interface to generate 3 V for LOVDD pin from 3.3V or 5V Supply.

3.3 VGATE Interface

SO

The VGATE1, VGATE2 pins are bias pins for mixer cores. On evaluation board VGATE1, VGATE2 pin
voltages are set to 5V. However voltage can be tuned between 4.7V and 5V for optimizing input IP3
and conversion gain performances for desired frequency band. Higher IIP3 values can be obtained by
increasing the VGATE1, VGATE2 pin voltages but this will reduce HMC1190LP6GE`s conversion gain.
Figure 77 shows the measured conversion gain and IIP3 for four values of VGATE1, VGATE2 pin voltages.

Conversion Gain vs. VGATE [1] Input IP3 vs. VGATE

B

12 31

29
10
CONVERSION GAIN (dB)

27
8
O

25
IIP3(dBm)

6 23

21
4
19
2
17

0 15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz) FREQUENCY (GHz)

4.7 V 4.9 V 4.7 V 4.9 V

4.8 V 5.0 V 4.8 V 5 .0V

Figure 75. Conversion Gain & IIP3 vs. RF Frequency over VGATE Pin Voltage @25C, IF =150 MHz

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 58
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

After the VGATE voltage is tuned for optimized IIP3 and conversion gain performance, the VGATE pin
voltage can be generated from 5V supply voltage by changing the value of series resistors, R54 and R56
from 0 Ohm to an appropriate value.
Table 20 shows the typical resistor values that need to be added in series with VGATE1, VGATE2 pins for
TRANSCEIVERS - Rx RFICs

different VGATE voltages.A fine tune for R54 and R56 resistors can be used if a better fit is required.

Table 20. Resistor values for Different VGATE Pin Voltages

VGATE1=VGATE2 R54=R56
4.7 V 174 Ohms

TE
4.8 V 120 Ohms
4.9 V 56 Ohms
5.0 V 0 Ohm

3.4 VCS Interface and LOBIAS Interface

LE
VCS1, VCS2 pins are bias pins for IF amplifiers on each channel and set the reference currents to these IF
amplifiers.The VCS voltage is generated from the 5V supply by series resistors. Higher IIP3 values can be
obtained by changing the values of these series resistors R61 and R73, which will change the total supply
current of the IF amplifiers which can be seen on Table 21 a.
LOBIAS1, LOBIAS2 pins are bias pins for LO amplifiers and set the reference currents to these LO amplifiers.
The LOBIAS voltage is generated from the 5V supply by series resistors R71 and R57. Changing LOBIAS2
voltage, changes current consumed by LOVDD pin, which can be seen at Table 21 b.
SO
HMC1190LP6GE`s flexible design allows users to choose best configuration for their needs. For higher
power consumption, better OIP3 values can be achieved.
10 28

9 26
CONVERSION GAIN (dB)

8 24
IIP3(dBm)

7 22
B

6 20

5 18

4
O

16
3.2 3.5 3.6 3.9 4 4.2 3.2 3.5 3.6 3.9 4 4.2
VCS (V) VCS (V)
+3.35V +4.40V +3.35V +4.4V
+3.70V +4.75V +3.7V +4.75V
+4.05V +4.05V

Figure 76.Conversion Gain, IIP3 vs. VCS1, VCS2 and LOBIAS2 voltages at 1900 MHz RF Input. [1]
Figure 76 shows the measured conversion gain and IIP3 vs. VCS and LOBIAS2 voltages at 1900MHz.
Conversion gain and IIP3 vs. VCS and LOBIAS2 voltages at 1900MHz.

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
59 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

Table 21 a. VCS voltage vs IF Amplifier Currents

VCS Jumper, J13 (V) VCS Pin (V) IF Amp (mA) R61=R73
4.25 181 440 Ohms

TRANSCEIVERS - Rx RFICs
4.0 159 590 Ohms
5.0 V 3.75 135 740 Ohms
3.5 110 880 Ohms
3.25 86 1 KOhms

TE
Table 21 b. LOBIAS2 voltage vs LO Amplifier Currents
LOBIAS Jumper, J12 (V) LOBIAS2 Pin (V) LO Amp (mA) R71=R57
4.75 157 110 Ohms
4.4 150 270 Ohms
5.0 V 4.05 143 420 Ohms
3.7 135 580 Ohms

3.5 External RF Matching

3.36 LE 128

The HMC1190LP6GE`s RF inputs are internally broadband matched to 50Ω. RF inputs can be externally
740 Ohms

matched for a specific RF frequency band of interest to further improve Input IP3 (IIP3). Matching RF
inputs to a specific RF frequency band can be easily accomplished by adding a series inductor and a shunt
SO
capacitor. See Table 3 for values of the external matching components for corresponding RF frequency
bands. Application circuit with the external components on RF input pins can be seen at Figure 80.
VGATE1, VGATE2 pin voltages can be optimized for a specific RF frequency band by changing the resistor
values in series with these pins. Table-1 shows the resistor values (R54, R56) for corresponding VGATE
pin voltage.
Figure 77, Figure 78, and Figure 79 show the measured conversion gain, IIP3 and OIP3 for 900MHz,
1900MHz and 2500MHz RF frequency bands.
B

18 30
40
INPUT IP3 38
15 25
36
CONVERSION GAIN (dB)

34
12 20
32
O

OIP3(dBm)
IIP3 (dBm)

9 15 30
28
CONVERSION GAIN
6 10 26
24
3 5 22
20
0 0 18
700 800 900 1000 1100 0.7 0.8 0.9 1 1.1
FREQUENCY (MHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

Figure 77.Conversion gain, IIP3 and OIP3 for 900MHz RF frequency band. [1]

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 60
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

18 30
40
INPUT IP3
38
15 25
36
CONVERSION GAIN (dB)
TRANSCEIVERS - Rx RFICs

20 34
12
32

OIP3(dBm)
IIP3 (dBm)
9 15 30
28
6 10 26
CONVERSION GAIN 24
3 5 22
20

TE
0 0
18
1700 1800 1900 2000 2100 2200 1.7 1.8 1.9 2 2.1 2.2
FREQUENCY (MHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

Figure 78.Conversion Gain, IIP3 and OIP3 for 1900MHz RF frequency band. [1]
18 30

15
INPUT IP3
LE
25
40
38
36
CONVERSION GAIN (dB)

34
12 20
32
OIP3(dBm)
IIP3 (dBm)

9 15 30
28
6 10 26
24
SO
CONVERSION GAIN
3 5 22
20
0 0 18
2300 2400 2500 2600 2700 2.3 2.4 2.5 2.6 2.7
FREQUENCY (MHz) FREQUENCY (GHz)

+25C +85C -40C +25C +85C -40C

Figure 79. Conversion Gain, IIP3 and OIP3 for 2500MHz RF frequency bands. [1]
B

Table 22. Components for Selected Frequency Bands

Recommended VGATE1,2
Tune Frequency C82 C81 C80 R55
Voltages
O

900 MHz 2.7 pF 8.2 nH Open 0 Ohm 5.0V

1900 MHz 1 pF 2.7 nH Open 120 Ohms 4.8V

2500MHz Open 1 nH 1 pF 120 Ohms 4.8V

[1] Balun losses at IF output ports are de-embedded.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
61 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

TRANSCEIVERS - Rx RFICs
TE
LE
Figure 80. Application Circuit for Narrowband RF Input Matching
It is recommended to use high side LO injection for RF frequencies below 1.2 GHz for better IIP3. For
instance, higher IIP3 can be obtained if LO input is driven with high side at RF=900 MHz. Please refer to
Figure 81.
SO
31

29

27

25
IIP3 (dBm)

23

21

19
B

17

15
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
FREQUENCY (GHz)
O

High Side LO Low Side LO

Figure 81. Input IP3 vs. High Side LO & Low Side LO @ VGATE=4.8V

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 62
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

3.6 Input IP3 Dependence on RF Input Power

The HMC1190LP6GE accepts a wide range of RF input power. Figure 82 shows the IIP3 vs. RF input
power for 1900 MHz RF and 150 MHz IF.
TRANSCEIVERS - Rx RFICs

31

29

27

25
IIP3 (dBm)

TE
23

21

19

17

15
-10 -8 -6 -4 -2 0
RF POWER (dBm)

LE 1900 MHz

Figure 82. IIP3 vs. RF Input Power, RF= 1900 MHz, IF= 150 MHz, VGATE= 4.8V

3.7 Enabling / Disabling Mixer Features

HMC1190LP6GE has a dual channel down converter core but it can also be configured as a single channel
one. When single channel option is desired, HMC1190LP6GE`s unused IF amplifier can be disabled
SO
through SPI interface.
HMC1190LP6GE can also be used as standalone PLL/VCO. In this case all IF and LO buffer amplifiers
at mixer side can be disabled through SPI interface. Value of Reg14 should be changed in order to make
necessary enable/disable changes. See Table 23 for details.

Table 23. Mixer Enable / Disable

REG14h value Function
B

3F4 IF2 disabled, IF1 and LO_Mixer enabled

3F2 IF1 disabled, IF2 and LO_Mixer enabled
3F6 IF1, IF2 and LO_Mixer disabled
O

3F0 IF1, IF2 and LO_Mixer enabled

3.8 Using an External VCO

In order to configure HMC1190LP6GE to use with an external VCO, Register 17 needs to be configured to
disable the on chip VCO and VCO to PLL path. Enable External Buffer, second CP link and External I/O
switch. To make these changes Reg 17 [0:11] should be configured as 3157d.
Figure 83 shows HMC1190LP6GE configured as PLL alone used with External VCO HMC384LP4E. Loop
Filter components are used as below.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700
On-line at www.hittite.com
63 license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
• Order online at www.analog.com
Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. or apps@hittite.com
 HMC1190LP6GE
v06.1113

BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER

w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz

TRANSCEIVERS - Rx RFICs
TE
Figure 83. Loop filter components for HMC1190LP6GE is configured as PLL alone used with external VCO
HMC384LP4E

-40

-60
LE
PHASE NOISE(dBc/Hz)

-80

-100

-120

-140
SO
-160

-180
1 10 100 1000 10000
OFFSET (KHz)

Figure 84. Closed Loop Phase Noise with External HMC384LP4E VCO @ 2200 MHz.
For detailed theory of operation of PLL/VCO, please refer to the “PLLs with Integrated VCOs - RF VCOs Operating
B

Guide”.
O

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

For price, delivery and to place orders: For price, 2delivery, and to placeChelmsford,
orders: Analog MA
Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for anyHittite Microwave
infringements Corporation,
of patents or other Elizabeth Drive, 01824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343 Fax: 978-250-3373 Phone:
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Order781-329-4700
On-line at www.hittite.com
• Order online at www.analog.com 64
Trademarks and registered trademarks are Application Support:
the property of their Phone: 978-250-3343
respective owners. Application Support: Phone: 1-800-ANALOG-D
or apps@hittite.com