kiarash ghasemzadeh

6/9/2023
HKMG & clock routing

HKMG Transistors: thickness could be increased without increasing

the electrical oxide thickness, effectively
HKMG transistor stands for High-K Metal Gate
reducing tunneling current
transistor. It refers to a type of transistor
technology used in semiconductor and leakage power. Intel also replaced the
manufacturing. In HKMG transistors, the doped poly-silicon gate electrode with a metal
traditional gate dielectric material (usually gate to enhance capacitance and drive current.
silicon dioxide) is replaced with a high-k They continue to develop high-k metal-gate
dielectric material, such as hafnium dioxide technology, with the 45nm process already in
(HfO2), zirconium dioxide (ZrO2), or other production and the 32nm process on the
similar compounds. Additionally, the gate horizon.
electrode is made of metal instead of doped
poly-silicon.

The introduction of high-k dielectrics and metal

gate electrodes in HKMG transistors helps to
address the challenges of gate leakage and
performance limitations in traditional
transistors. The high-k dielectric materials have
a higher dielectric constant (k) compared to
silicon dioxide, allowing for thicker gates
without increasing the electrical oxide
thickness. This reduces quantum mechanical
tunneling and gate leakage. The metal gate
electrode eliminates poly-depletion, improving
the transistor's inversion charge and drive
current.

HKMG technology has been widely adopted in

Clock Tree Routing:
advanced semiconductor processes, such as the
45nm, 32nm, and smaller technology nodes. It Clock tree routing algorithms are used to
enables improved performance, reduced power minimize skew, which refers to the variation in
consumption, and enhanced transistor arrival times of clock signals at different points
characteristics, contributing to the ongoing in a circuit. The goal is to distribute the clock
progress in semiconductor technology. signal in such a way that the interconnections
carrying the clock signal to various sub-blocks
Intel achieved a significant breakthrough in
have equal lengths.
transistor technology by introducing a "high-k"
(Hi-k) material, specifically hafnium, as the gate Several algorithms exist to minimize skew:
dielectric and using new metals for gate
H-Tree: The H-Tree algorithm routes the clock
electrodes in their 45nm process. This
signal in a manner similar to the letter "H." It
innovation improved transistor performance
equalizes the wire lengths by ensuring that the
and reduced gate leakage in NMOS and PMOS
distances from the clock source point to each
transistors. By employing high-k materials with
clock sink point are the same. H-Tree is often
higher dielectric constants, the physical gate
 kiarash ghasemzadeh
6/9/2023
HKMG & clock routing

used in scenarios where clock terminal points

are symmetrically arranged, such as in gate
Exact zero skew in terms of distance due to the
arrays or FPGAs.
symmetry of the H-Tree.
X-Tree: The X-Tree algorithm is similar to the H-
Suitable for scenarios where clock terminal
Tree approach but allows for non-rectilinear
points are arranged in a symmetrical manner,
connections. It aims to minimize skew by
such as in gate arrays or FPGAs.
creating clock trees with non-linear
connections. However, the close proximity of  Disadvantages:
wires in X-Tree routing can lead to crosstalk.
Blockages can disrupt the symmetry of the H-
Tree, affecting its performance.
Method of Mean and Median (MMM) Non-uniform sink locations and varying sink
Algorithm: The MMM algorithm partitions clock capacitance can complicate the design of the H-
terminal points into subsets using median and Tree.
mean calculations. It connects the center of
mass of the entire set to the centers of mass of X-Tree Algorithm:
the partitioned subsets. This approach handles  Advantages:
clock sinks located anywhere and does not rely
on a rectilinear structure. Allows for non-rectilinear connections,
providing flexibility in routing clock signals.
Recursive Geometric Matching (RGM)
Algorithm: The RGM algorithm constructs a Can achieve zero skew when properly
clock tree using exclusive geometry matching. It implemented.
involves recursively finding sets of line segments
 Disadvantages:
that match endpoints with minimum total
length. Tapping points are established on each Close proximity of wires in X-Tree routing can
matching segment to maintain zero skew to lead to crosstalk, impacting signal integrity.
related sinks. The RGM algorithm follows a
Clock routing is not rectilinear, which can
bottom-up approach and generally yields better
complicate the design process.
results than top-down methods.
Method of Mean and Median (MMM)
Each of these algorithms aims to minimize skew
Algorithm:
by ensuring that clock interconnections have
equal lengths or follow specific geometric  Advantages:
patterns. However, they have their advantages
and limitations, such as sensitivity to blockages, Handles clock sinks located anywhere, not
non-uniform sink locations, crosstalk, and wire limited to a symmetrical arrangement.
interactions. The choice of algorithm depends Can achieve zero skew by partitioning clock
on the specific design requirements and terminals based on mean and median
constraints. calculations.
H-Tree Algorithm:  Disadvantages:
 Advantages:
 kiarash ghasemzadeh
6/9/2023
HKMG & clock routing

Ignores blockages, which can affect the design's

performance and introduce irregularities.

Produces a non-rectilinear clock tree,

potentially leading to wire interactions and
crosstalk.

Recursive Geometric Matching (RGM)

Algorithm:

 Advantages:

Offers a bottom-up approach, yielding better

results than top-down methods.

Considers geometric matching to construct a

clock tree with tapping points, maintaining zero
skew.

 Disadvantages:

More computationally complex compared to

other algorithms.

Potential wire interactions and crosstalk due to

non-rectilinear clock tree construction.

It's important to consider these advantages and

disadvantages when choosing a clock tree
routing algorithm, as they can impact the
performance, design complexity, and signal
integrity of the circuit.