UNIT 1

FUNCTIONAL BLOCKS OF A COMPUTER

CPU:-
The full form of CPU is Central Processing Unit . It is a brain of the computer. All types of
data processing operations and all the important functions of a computer are performed by
the CPU. It helps input and output devices to communicate with each other and perform their
respective operations. It also stores data which is input, intermediate results in between
processing, and instructions.

WHAT IS A CPU?
A Central Processing Unit is the most important component of a computer system. A CPU is
a hardware that performs data input/output, processing and storage functions for a computer
system. A CPU can be installed into a CPU socket. These sockets are generally located on
the motherboard. CPU can perform various data processing operations. CPU can store data,
instructions, programs, and intermediate results.

HISTORY OF CPU
Since 1823, when Baron Jons Jakob Berzelius discovered silicon, which is still the primary
component used in the manufacture of CPUs today, the history of the CPU has experienced
numerous significant turning points. The first transistor was created by John Bardeen, Walter
Brattain, and William Shockley in December 1947. in 1958, the first working integrated
circuit was built by Robert Noyce and Jack Kilby.
The Intel 4004 was the company’s first microprocessor, which it unveiled in 1971. Ted Hoff’s
assistance was needed for this. When Intel released its 8008 CPU in 1972, Intel 8086 in 1976,
and Intel 8088 in June 1979, it contributed to yet another win. The Motorola 68000, a 16/32-
bit processor, was also released in 1979. The Sun also unveiled the SPARC CPU in 1987.
AMD unveiled the AM386 CPU series in March 1991.
In January 1999, Intel introduced the Celeron 366 MHZ and 400 MHz processors. AMD back
in April 2005 with it’s first dual-core processor. Intel also introduced the Core 2 Dual
processor in 2006. Intel released the first Core i5 desktop processor with four cores in
September 2009.
In January 2010, Intel released other processors like Core 2 Quad processor Q9500, the first
Core i3 and i5 mobile processors, first Core i3 and i5 desktop processors.
In June 2017, Intel released Core i9 desktop processor, and Intel introduced its first Core i9
mobile processor In April 2018.

DIFFERENT PARTS OF CPU

Now, the CPU consists of 3 major units, which are:
1. Memory or Storage Unit
2. Control Unit
3. ALU(Arithmetic Logic Unit)
Let us now look at the block diagram of the computer:
Here, in this diagram, the three major components are also shown. So, let us discuss these
major components:

MEMORY OR STORAGE UNIT

As the name suggests this unit can store instructions, data, and intermediate results. The
memory unit is responsible for transferring information to other units of the computer when
needed. It is also known as an internal storage unit or the main memory or the primary storage
or Random Access Memory (RAM) as all these are storage devices.
Its size affects speed, power, and performance. There are two types of memory in the
computer, which are primary memory and secondary memory. Some main functions of
memory units are listed below:
 Data and instructions are stored in memory units which are required for
processing.
 It also stores the intermediate results of any calculation or task when they are in
process.
 The final results of processing are stored in the memory units before these
results are released to an output device for giving the output to the user.
 All sorts of inputs and outputs are transmitted through the memory unit.

CONTROL UNIT
As the name suggests, a control unit controls the operations of all parts of the computer but
it does not carry out any data processing operations. For executing already stored instructions,
It instructs the computer by using the electrical signals to instruct the computer system. It
takes instructions from the memory unit and then decodes the instructions after that it
executes those instructions. So, it controls the functioning of the computer. It’s main task is
to maintain the flow of information across the processor. Some main functions of the control
unit are listed below:
  Controlling of data and transfer of data and instructions is done by the control
unit among other parts of the computer.
 The control unit is responsible for managing all the units of the computer.
 The main task of the control unit is to obtain the instructions or data which is
input from the memory unit, interprets them, and then directs the operation of the
computer according to that.
 The control unit is responsible for communication with Input and output devices
for the transfer of data or results from memory.
 The control unit is not responsible for the processing of data or storing data.

ALU (ARITHMETIC LOGIC UNIT)

ALU (Arithmetic Logic Unit) is responsible for performing arithmetic and logical functions
or operations. It consists of two subsections, which are:
 Arithmetic Section
 Logic Section
Now, let us know about these subsections:

 ARITHMETIC SECTION: By arithmetic operations, we mean operations like

addition, subtraction, multiplication, and division, and all these operation and
functions are performed by ALU. Also, all the complex operations are done by
making repetitive use of the mentioned operations by ALU.

 LOGIC SECTION: By Logical operations, we mean operations or functions like

selecting, comparing, matching, and merging the data, and all these are performed by
ALU.

WHAT DOES A CPU DO?

The main function of a computer processor is to execute instruction and produce an output.
CPU work are Fetch, Decode and Execute are the fundamental functions of the computer.
 Fetch: the first CPU gets the instruction. That means binary numbers that are
passed from RAM to CPU.
 Decode: When the instruction is entered into the CPU, it needs to decode the
instructions. with the help of ALU (Arithmetic Logic Unit) the process of decode
begins.
 Execute: After decode step the instructions are ready to execute
 Store: After execute step the instructions are ready to store in the memory.
TYPES OF CPU
We have three different types of CPU:
 SINGLE CORE CPU: The oldest type of computer CPUs is single core CPU.
These CPUs were used in the 1970s. these CPUs only have a single core that
preform different operations. This means that the single core CPU can only
process one operation at a single time. single core CPU CPU is not suitable for
multitasking.
 DUAL-CORE CPU: Dual-Core CPUs contain a single Integrated Circuit with
two cores. Each core has its cache and controller. These controllers and cache are
work as a single unit. dual core CPUs can work faster than the single-core
processors.
 QUAD-CORE CPU: Quad-Core CPUs contain two dual-core processors
present within a single integrated circuit (IC) or chip. A quad-core processor
contains a chip with four independent cores. These cores read and execute various
instructions provided by the CPU. Quad Core CPU increases the overall speed for
programs. Without even boosting the overall clock speed it results in higher
performance.
 MEMORY
WHAT IS COMPUTER MEMORY?
Computer memory is just like the human brain. It is used to store data/information
and instructions. It is a data storage unit or a data storage device where data is to be processed
and instructions required for processing are stored. It can store both the input and output can
be stored here.

CHARACTERISTICS OF COMPUTER MEMORY

 It is faster computer memory as compared to secondary memory.
 It is semiconductor memories.
 It is usually a volatile memory, and main memory of the computer.
 A computer system cannot run without primary memory.

HOW DOES COMPUTER MEMORY WORK?

When you open a program, it is loaded from secondary memory into primary memory.
Because there are various types of memory and storage, an example would be moving
a program from a solid-state drive (SSD) to RAM. Because primary storage is
accessed more quickly, the opened software can connect with the computer’s
processor more quickly. The primary memory is readily accessible from temporary
memory slots or other storage sites.
Memory is volatile, which means that data is only kept temporarily in memory. Data
saved in volatile memory is automatically destroyed when a computing device is
turned off. When you save a file, it is sent to secondary memory for storage.
There are various kinds of memory accessible. It’s operation will depend upon the
type of primary memory used. but normally, semiconductor-based memory is more
related with memory. Semiconductor memory made up of IC (integrated circuits) with
silicon-based metal-oxide-semiconductor (MOS) transistors.

TYPES OF COMPUTER MEMORY

In general, computer memory is of three types:
 Primary memory
 Secondary memory
 Cache memory
Now we discuss each type of memory one by one in detail:

1. PRIMARY MEMORY
It is also known as the main memory of the computer system. It is used to store data
and programs or instructions during computer operations. It uses semiconductor technology
and hence is commonly called semiconductor memory. Primary memory is of two types:

 RAM (Random Access Memory): It is a volatile memory. Volatile

memory stores information based on the power supply. If the power supply
fails/ interrupted/stopped, all the data and information on this memory will
be lost. RAM is used for booting up or start the computer. It temporarily
 stores programs/data which has to be executed by the processor. RAM is of
two types:
 S RAM (Static RAM): S RAM uses transistors and the circuits
of this memory are capable of retaining their state as long as the
power is applied. This memory consists of the number of flip
flops with each flip flop storing 1 bit. It has less access time and
hence, it is faster.
 D RAM (Dynamic RAM): D RAM uses capacitors and
transistors and stores the data as a charge on the capacitors. They
contain thousands of memory cells. It needs refreshing of charge
on capacitor after a few milliseconds. This memory is slower than
S RAM.

 ROM (Read Only Memory): It is a non-volatile memory. Non-volatile

memory stores information even when there is a power supply failed/
interrupted/stopped. ROM is used to store information that is used to
operate the system. As its name refers to read-only memory, we can only
read the programs and data that is stored on it. It contains some electronic
fuses that can be programmed for a piece of specific information. The
information stored in the ROM in binary format. It is also known as
permanent memory. ROM is of four types:

 MROM (Masked ROM): Hard-wired devices with a pre-

programmed collection of data or instructions were the first
ROMs. Masked ROMs are a type of low-cost ROM that works in
this way.

 PROM (Programmable Read Only Memory): This read-only

memory is modifiable once by the user. The user purchases a
blank PROM and uses a PROM program to put the required
contents into the PROM. Its content can’t be erased once written.

 EPROM (Erasable Programmable Read Only

Memory): EPROM is an extension to PROM where you can
erase the content of ROM by exposing it to Ultraviolet rays for
nearly 40 minutes.

 EEPROM (Electrically Erasable Programmable Read Only

Memory): Here the written contents can be erased electrically.
You can delete and reprogramme EEPROM up to 10,000 times.
Erasing and programming take very little time, i.e., nearly 4 -10
ms (milliseconds). Any area in an EEPROM can be wiped and
programmed selectively.
2. SECONDARY MEMORY
It is also known as auxiliary memory and backup memory. It is a non-volatile memory and
used to store a large amount of data or information. The data or information stored in
secondary memory is permanent, and it is slower than primary memory. A CPU cannot
access secondary memory directly. The data/information from the auxiliary memory is first
transferred to the main memory, and then the CPU can access it.

CHARACTERISTICS OF SECONDARY MEMORY:-

 It is a slow memory but reusable.

 It is a reliable and non-volatile memory.
 It is cheaper than primary memory.
 The storage capacity of secondary memory is large.
 A computer system can run without secondary memory.
 In secondary memory, data is stored permanently even when the power is off.

TYPES OF SECONDARY MEMORY:-

1. MAGNETIC TAPES: Magnetic tape is a long, narrow strip of plastic film

with a thin, magnetic coating on it that is used for magnetic recording. Bits
are recorded on tape as magnetic patches called RECORDS that run along
many tracks. Typically, 7 or 9 bits are recorded concurrently. Each track
has one read/write head, which allows data to be recorded and read as a
sequence of characters. It can be stopped, started moving forward or
backward, or rewound.

2. MAGNETIC DISKS: A magnetic disk is a circular metal or a plastic plate

and these plates are coated with magnetic material. The disc is used on both
sides. Bits are stored in magnetized surfaces in locations called tracks that
run in concentric rings. Sectors are typically used to break tracks into pieces.

Hard discs are discs that are permanently attached and cannot be removed by a
single user.
3. OPTICAL DISKS: It’s a laser-based storage medium that can be written to and
read. It is reasonably priced and has a long lifespan. The optical disc can be taken
out of the computer by occasional users.

TYPES OF OPTICAL DISKS

 CD – ROM

 It’s called compact disk. Only read from memory.

 Information is written to the disc by using a controlled laser beam to
burn pits on the disc surface.
 It has a highly reflecting surface, which is usually aluminium.
 The diameter of the disc is 5.25 inches.
 16000 tracks per inch is the track density.
 The capacity of a CD-ROM is 600 MB, with each sector storing 2048
bytes of data.
 The data transfer rate is about 4800KB/sec. & the new access time is
around 80 milliseconds.

 WORM-(WRITE ONCE READ MANY)

 A user can only write data once.

 The information is written on the disc using a laser beam.
 It is possible to read the written data as many times as desired.
 They keep lasting records of information but access time is high.
 It is possible to rewrite updated or new data to another part of the disc.
 Data that has already been written cannot be changed.
 Usual size – 5.25 inch or 3.5 inch diameter.
 The usual capacity of 5.25 inch disk is 650 MB,5.2GB etc.

 DVDs
 The term “DVD” stands for “Digital Versatile/Video Disc,” and there
are two sorts of DVDs:
o DVDR (writable)
o DVDRW (Re-Writable)

 DVD-ROMS (Digital Versatile Discs): These are read-only

memory (ROM) discs that can be used in a variety of ways.
When compared to CD-ROMs, they can store a lot more data.
It has a thick polycarbonate plastic layer that serves as a
foundation for the other layers. It’s an optical memory that can
read and write data.

 DVD-R: DVD-R is a writable optical disc that can be used just

once. It’s a DVD that can be recorded. It’s a lot like
 WORM. DVD-ROMs have capacities ranging from 4.7 to 17
GB. The capacity of 3.5-inch disk is 1.3 GB.

3. CACHE MEMORY
It is a type of high-speed semiconductor memory that can help the CPU run faster. Between
the CPU and the main memory, it serves as a buffer. It is used to store the data and programs
that the CPU uses the most frequently.

ADVANTAGES OF CACHE MEMORY

 It is faster than the main memory.
 When compared to the main memory, it takes less time to access it.
 It keeps the programs that can be run in a short amount of time.
 It stores data in temporary use.

DISADVANTAGES OF CACHE MEMORY

 Because of the semiconductors used, it is very expensive.
 The size of the cache (amount of data it can store) is usually small.
 INPUT-OUTPUT SUBSYSTEMS
The I/O subsystem of a computer provides an efficient mode of communication between the
central system and the outside environment. It handles all the input-output operations of the
computer system.

1. PERIPHERAL DEVICES

Input or output devices that are connected to computer are called peripheral devices. These
devices are designed to read information into or out of the memory unit upon command from
the CPU and are considered to be the part of computer system. These devices are also
called peripherals.

For example: Keyboards, display units and printers are common peripheral devices.

There are three types of peripherals:

1. Input peripherals : Allows user input, from the outside world to the computer.
Example: Keyboard, Mouse etc.

2. Output peripherals: Allows information output, from the computer to the outside
world. Example: Printer, Monitor etc

3. Input-Output peripherals: Allows both input(from outised world to computer) as well

as, output(from computer to the outside world). Example: Touch screen etc.

In addition to the processor and a set of memory modules, the third key element of a computer
system is a set of input-output subsystem referred to as I/O, provides an efficient mode of
communication between the central system and the outside environment.

Programs and data must be entered into computer memory for processing and results obtained
from computations must be recorded or displayed for the user. Devices that are under the direct
control of the computer are said to be connected online. These devices are designed to read
information into or out of the memory unit upon command from CPU. Input or output devices
attached to the computer are also called peripherals.

Among the most common peripherals are keyboards, display units, and printers. Perhaps those
provide auxiliary storage for the systems are magnetic disks and tapes. Peripherals are
electromechanical and electromagnetic devices of some complexity. We can broadly classify
peripheral devices into three categories:

o Human Readable: Communicating with the computer users, e.g. video display
terminal, printers etc.
o Machine Readable: Communicating with equipments, e.g. magnetic disk, magnetic
tape, sensor, actuators used in robotics etc.
o Communication: Communicating with remote devices means exchanging data with
that, e.g. modem, NIC (network interface Card) etc.
 Fig: Block diagram of Peripheral device

Figure explains:-
 Control signals determine the function that the device will perform such
as send data to I/O module, accept data from I/O module.
 Status signals indicate the state of the device i.e. device is ready or not.
 Data bits are actual data transformation.
 Control logic associated with the device controls the device's operation
in response to direction from the I/O module.
 The transducer converts data from electrical to other forms of energy
during output and from other forms to electrical during input.
 Buffer is associated with the transducer to temporarily hold data being
transferred between the I/O module and external devices i.e. peripheral
environment.

A. INPUT DEVICE

 Keyboard
 Optical input devices
o Card Reader
o Paper Tape Reader.
o Optical Character Recognition (OCR).
o Optical Bar code reader (OBR).
o Digitizer o Optical Mark Reader.
 Magnetic Input Devices
o Magnetic Stripe Reader .
o Magnetic Ink Character Recognition (MICR).
 Screen Input Devices
 o Touch Screen.
o Light Pen.
o Mouse.

Analog Input Devices.

B. OUTPUT DEVICE

 Card Puncher, Paper Tape Puncher.

 Monitor (CRT, LCD, LED).
 Printer (Impact, Ink Jet, Laser, Dot Matrix).
 Plotter.
 Analog.
 Voice

2. INTERFACES

 Input-Output interface provides a method for transferring information between

internal storage (such as memory and CPU registers) and external I/O devices.

 Peripherals connected to a computer need special communication links for

interfacing them with the central processing unit.

 The communication link resolves the following differences between the computer
and peripheral devices.

o Devices and signals

 Peripherals - Electromechanical Devices
 CPU or Memory - Electronic Device.

o Data Transfer Rate

 Peripherals - Usually slower
 CPU or Memory - Usually faster than peripherals
 Some kinds of Synchronization mechanism may be needed

o Unit of Information
 Peripherals – Byte
 CPU or Memory – Word.

o Operating Modes
 Peripherals - Autonomous, Asynchronous
 CPU or Memory – Synchronous
  To resolve these differences, computer systems include special hardware
components (Interfaces) between the CPU and peripherals to supervise and
synchronize all input and output interfaces.

Interface is a shared boundary between two separate components of the computer system
which can be used to attach two or more components to the system for communication
purposes.

There are two types of interface:

1. CPU Inteface

2. I/O Interface

Peripherals connected to a computer need special communication links for interfacing with
CPU. In computer system, there are special hardware components between the CPU and
peripherals to control or manage the input-output transfers. These components are called input-
output interface units because they provide communication links between processor bus and
peripherals. They provide a method for transferring information between internal system and
input-output devices.

I/O BUS AND INTERFACE MODULES

 The I/O bus consists of data lines, address lines and control lines.

Fig: Connection of I/O bus to input-output devices

 Interface performs the following:

 Decodes the device address (device code)

 Decodes the commands (operation)
 Provides signals for the peripheral controller.
 Synchronizes the data flow and supervises the transfer rate between peripheral and
CPU or Memory.

 I/O commands that the interface may receive:

 Control command: issued to activate the peripheral and to inform it what to do.
  Status command: used to test various status conditions in the interface and the
peripheral.
 Output data: causes the interface to respond by transferring data from the bus into
one of its registers.
 Input data: is the opposite of the data output.

I/O VERSUS MEMORY BUS

 Computer buses can be used to communicate with memory and I/O in

three ways:

 Use two separate buses, one for memory and other for I/O. In this method, all data,
address and control lines would be separate for memory and I/O.
 Use one common bus for both memory and I/O but have separate control lines.
There is a separate read and write lines; I/O read and I/O write for I/O and memory
read and memory write for memory.
 Use a common bus for memory and I/O with common control line. This I/O
configuration is called memory mapped.

ISOLATED I/O VERSUS MEMORY MAPPED I/O

 Isolated I/O

 Separate I/O read/write control lines in addition to memory read/write control

lines.
 Separate (isolated) memory and I/O address spaces.
 Distinct input and output instructions.

 Memory-mapped I/O

 A single set of read/write control lines (no distinction between memory and I/O
transfer).
 Memory and I/O addresses share the common address space which reduces
memory address range available.
 No specific input or output instruction so the same memory reference instructions
can be used for I/O transfers.
 Considerable flexibility in handling I/O operations.
EXAMPLE OF I/O INTERFACE

 Information in each port can be assigned a meaning depending on the mode

of operation of the I/O device.

 Port A = Data; Port B = Command; Port C = Status.

 CPU initializes (loads) each port by transferring a byte to the Control

Register.

 Allows CPU can define the mode of operation of each port.

 Programmable Port: By changing the bits in the control register, it is possible to
change the interface characteristic.
3. MODES OF I/O DATA TRANSFER

Data transfer between the central unit and I/O devices can be handled in generally three
types of modes which are given below:

1. Programmed I/O

2. Interrupt Initiated I/O

3. Direct Memory Access

A. PROGRAMMED I/O

 Programmed I/O instructions are the result of I/O instructions written in

computer program. Each data item transfer is initiated by the instruction in
the program.
 Usually the program controls data transfer to and from CPU and peripheral.
Transferring data under programmed I/O requires constant monitoring of the
peripherals by the CPU.
 In programmed I/O, each data transfer in initiated by the instructions in the
CPU and hence the CPU is in the continuous monitoring of the interface.
 Input instruction is used to transfer data from I/O device to CPU, store
instruction is used to transfer data from CPU to memory and output
instruction is used to transfer data from CPU to I/O device.
 This technique is generally used in very slow speed computer and is not a
efficient method if the speed of the CPU and I/O is different.

Fig: Data transfer from I/O device to CPU

 I/O device places the data on the I/O bus and enables its data valid signal.
 The interface accepts the data in the data register and sets the F bit of status
register and also enables the data accepted signal.
 Data valid line is disables by I/O device.
 CPU is in a continuous monitoring of the interface in which it checks the F
bit of the status register.
 If it is set i.e. 1, then the CPU reads the data from data register and sets
F bit to zero.
 If it is reset i.e. 0, then the CPU remains monitoring the interface.
 Interface disables the data accepted signal and the system goes to initial state
where next item of data is placed on the data bus.

Fig: Flowchart for CPU program to input data

 CHARACTERISTICS:
 Continuous CPU involvement.
 CPU slowed down to I/O speed.
 Simple.
 Least hardware.

Polling, or polled operation, in computer science, refers to actively sampling the

status of an external device by a client program as a synchronous activity. Polling is
most often used in terms of input/output (I/O), and is also referred to as polled I/O
or software driven I/O.

B. INTERRUPT INITIATED I/O

In the programmed I/O method the CPU stays in the program loop until the I/O unit
indicates that it is ready for data transfer. This is time consuming process because it
keeps the processor busy needlessly.

This problem can be overcome by using interrupt initiated I/O. In this when the
interface determines that the peripheral is ready for data transfer, it generates an
interrupt. After receiving the interrupt signal, the CPU stops the task which it is
processing and service the I/O transfer and then returns back to its previous
processing task.

 Polling takes valuable CPU time.

 Open communication only when some data has to be passed -> Interrupt.
 I/O interface, instead of the CPU, monitors the I/O device.
 When the interface determines that the I/O device is ready for data transfer,
it generates an Interrupt Request to the CPU.
 Upon detecting an interrupt, CPU stops momentarily the task it is doing,
branches to the service routine to process the data transfer, and then returns
to the task it was performing.

The problem with programmed I/O is that the processor has to wait a long time
for the I/O module of concern to be ready for either reception or transmission of
data. The processor, while waiting, must repeatedly interrogate the status of the
I/O module. As a result, the level of the performance of the entire system is
severely degraded. An alternative is for the processor to issue an I/O command
to a module and then go on to do some other useful work. The I/O module will
then interrupt the processor to request service when it is ready to exchange data
with processor. The processor then executes the data transfer, and then resumes
its former processing. The interrupt can be initiated either by software or by
hardware.

INTERRUPT DRIVEN I/O BASIC OPERATION

 CPU issues read command.

 I/O module gets data from peripheral whilst CPU does other work.
  I/O module interrupts CPU.
 CPU requests data.
 I/O module transfers.

DATA INTERRUPT PROCESSING FROM CPU VIEWPOINT:-

 Issue read command

 Do other work
 Check for interrupt at end of each instruction cycle
 If interrupted:-

 Save context (registers).

 Process interrupt.
 Fetch data & store.

Fig: Simple Interrupt Processing

PRIORITY INTERRUPT

 Determines which interrupt is to be served first when two or more

requests are made simultaneously.
 Also determines which interrupts are permitted to interrupt the
computer while another is being serviced.
 Higher priority interrupts can make requests while servicing a lower
priority interrupt.
 PRIORITY INTERRUPT BY SOFTWARE (POLLING).

 Priority is established by the order of polling the devices (interrupt

sources), that is identify the highest-priority source by software means.
 One common branch address is used for all interrupts.
 Program polls the interrupt sources in sequence.
 The highest-priority source is tested first.
 Flexible since it is established by software.
 Low cost since it needs a very little hardware.
 Very slow

PRIORITY INTERRUPT BY HARDWARE

 Require a priority interrupt manager which accepts all the interrupt

requests to determine the highest priority request.
 Fast since identification of the highest priority interrupt request is
identified by the hardware.
 Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine.

I. DAISY CHAIN PRIORITY (SERIAL)

Fig: Daisy Chain priority Interrupt

 Interrupt Request from any device.

 CPU responds by INTACK.
 Any device receives signal (INTACK) at PI puts the VAD on the bus.
 Among interrupt requesting devices the only device which is physically
closest to CPU gets INTACK and it blocks INTACK to propagate to the
next device.
 Fig: One stage of Daisy chain priority arrangement

II. PARALLEL PRIORITY

Fig: Parallel priority interrupts hardware

 IEN: Set or Clear by instructions ION or IOF.

 IST: Represents an unmasked interrupt has occurred. INTACK enables
tristate Bus Buffer to load VAD generated by the Priority Logic.
 Interrupt Register:

 Each bit is associated with an Interrupt Request from different

Interrupt Source - different priority level.
 Each bit can be cleared by a program instruction.

 Mask Register:

 Mask Register is associated with Interrupt Register.

 Each bit can be set or cleared by an Instruction
  Priority Encoder
Determines the highest priority interrupt when more than one interrupts
take place.

Fig: Priority Encoder Truth Table

 Interrupt Cycle
At the end of each Instruction cycle

 CPU checks IEN and IST.

 If IEN and IST = 1, CPU -> Interrupt Cycle.

o SP  SP – 1; Decrement stack pointer.

o M[SP]  PC;Push PC into stack.
o INTACK  1; Enable interrupt acknowledge.
o PC  VAD; Transfer vector address to PC.
o IEN  0; Disable further interrupts.
o Go To Fetch to execute the first instruction in the interrupt service
routine

C. DIRECT MEMORY ACCESS

Removing the CPU from the path and letting the peripheral device manage the
memory buses directly would improve the speed of transfer. This technique is
known as DMA.

In this, the interface transfer data to and from the memory through memory bus.
A DMA controller manages to transfer data between peripherals and memory
unit.

Many hardware systems use DMA such as disk drive controllers, graphic cards,
network cards and sound cards etc. It is also used for intra chip data transfer in
multicore processors. In DMA, CPU would initiate the transfer, do other
operations while the transfer is in progress and receive an interrupt from the
DMA controller when the transfer has been completed.
 Above figure shows block diagram of DMA

 Large blocks of data transferred at a high speed to or from high speed

devices, magnetic drums, disks, tapes, etc.
 DMA controller Interface that provides I/O transfer of data directly to
and from the memory and the I/O device.
 CPU initializes the DMA controller by sending a memory address and
the number of words to be transferred.
 Actual transfer of data is done directly between the device and memory
through DMA controller -> Freeing CPU for other tasks.

The transfer of data between the peripheral and memory without the interaction
of CPU and letting the peripheral device manage the memory bus directly is
termed as Direct Memory Access (DMA).

Fig: CPU bus signal for DMA transfer

The two control signals Bus Request and Bus Grant are used to fascinate the
DMA transfer. The bus request input is used by the DMA controller to request
the CPU for the control of the buses. When BR signal is high, the CPU
terminates the execution of the current instructions and then places the address,
data, read and write lines to the high impedance state and sends the bus grant
signal. The DMA controller now takes the control of the buses and transfers the
data directly between memory and I/O without processor interaction. When the
transfer is completed, the bus request signal is made low by DMA. In response
to which CPU disables the bus grant and again CPU takes the control of address,
data, read and write lines.
The transfer of data between the memory and I/O of course facilitates in two
ways which are DMA Burst and Cycle Stealing.

DMA Burst: The block of data consisting a number of memory words is

transferred at a time.

Cycle Stealing: DMA transfers one data word at a time after which it must
return control of the buses to the CPU.
 CPU is usually much faster than I/O (DMA), thus CPU uses the most
of the memory cycles.
 DMA Controller steals the memory cycles from CPU.
 For those stolen cycles, CPU remains idle.
 For those slow CPU, DMA Controller may steal most of the memory
cycles which may cause CPU remain idle long time.

DMA CONTROLLER
The DMA controller communicates with the CPU through the data bus and
control lines. DMA select signal is used for selecting the controller, the register
select is for selecting the register. When the bus grant signal is zero, the CPU
communicates through the data bus to read or write into the DMA register.
When bus grant is one, the DMA controller takes the control of buses and
transfers the data between the memory and I/O.

Fig: Block diagram of DMA controller

The address register specifies the desired location of the memory which is
incremented after each word is transferred to the memory. The word count
register holds the number of words to be transferred which is decremented after
each transfer until it is zero. When it is zero, it indicates the end of transfer. After
which the bus grant signal from CPU is made low and CPU returns to its normal
operation. The control register specifies the mode of transfer which is Read or
Write.

DMA TRANSFER
 DMA request signal is given from I/O device to DMA controller.
 DMA sends the bus request signal to CPU in response to which CPU
disables its current instructions and initialize the DMA by sending the
following information.
 The starting address of the memory block where the data are
available (for read) and where data to be stored (for write).
 The word count which is the number of words in the memory
block.
 Control to specify the mode of transfer.
 Sends a bust grant as 1 so that DMA controller can take the
control of the buses.
 DMA sends the DMA acknowledge signal in response to which
peripheral device puts the words in the data bus (for write) or
receives a word from the data bus (for read).

Fig: DMA transfer in a computer system

 DMA OPERATION
 CPU tells DMA controller:-
 Read/Write.
 Device address.
 Starting address of memory block for data.
 Amount of data to be transferred.
 CPU carries on with other work.
 DMA controller deals with transfer.
 DMA controller sends interrupt when finished.

4. I/O PROCESSOR

 Processor with direct memory access capability that communicates with I/O
devices.
 Channel accesses memory by cycle stealing.
 Channel can execute a Channel Program.
 Stored in the main memory.
 Consists of Channel Command Word (CCW).
 Each CCW specifies the parameters needed by the channel to control the I/O
devices and perform data transfer operations.
 CPU initiates the channel by executing a channel I/O class instruction and once
initiated, channel operates independently of the CPU.

A computer may incorporate one or more external processors and assign them the task
of communicating directly with the I/O devices so that no each interface need to
communicate with the CPU. An I/O processor (IOP) is a processor with direct memory
access capability that communicates with I/O devices. IOP instructions are specifically
designed to facilitate I/O transfer. The IOP can perform other processing tasks such as
arithmetic logic, branching and code translation.

Fig: Block diagram of a computer with I/O Processor

The memory unit occupies a central position and can communicate with each processor
by means of direct memory access. The CPU is responsible for processing data needed
in the solution of computational tasks. The IOP provides a path for transferring data
between various peripheral devices and memory unit. In most computer systems, the
CPU is the master while the IOP is a slave processor. The CPU initiates the IOP and
after which the IOP operates independent of CPU and transfer data between the
peripheral and memory. For example, the IOP receives 5 bytes from an input device at
the device rate and bit capacity. After which the IOP packs them into one block of 40
bits and transfer them to memory. Similarly, the O/P word transfer from memory to IOP
is directed from the IOP to the O/P device at the device rate and bit capacity.

CPU – IOP COMMUNICATION

The memory unit acts as a message center where each processor leaves information for
the other. The operation of typical IOP is appreciated with the example by which the
CPU and IOP communication.

Fig: CPU – IOP communication

 The CPU sends an instruction to test the IOP path.
 The IOP responds by inserting a status word in memory for the CPU to check.
 The bits of the status word indicate the condition of the IOP and I/O device,
such as IOP overload condition, device busy with another transfer or device
ready for I/O transfer.
 The CPU refers to the status word in in memory to decide what to do next.
 If all right up to this, the CPU sends the instruction to start I/O transfer.
 The CPU now continues with another program while IOP is busy with I/O
program.
  When IOP terminates the execution, it sends an interrupt request to CPU.
 CPU responds by issuing an instruction to read the status from the IOP.
 IOP responds by placing the contents to its status report into specified memory
location.
 Status word indicates whether the transfer has been completed or with error.

5. DATA COMMUNICATION PROCESSOR

 Distributes and collects data from many remote terminals connected through
telephone and other communication lines.
 Transmission:
o Synchronous.
o Asynchronous
 Transmission Error:
o Parity.
o ChecksuM.
o Cyclic Redundancy Check.
o Longitudinal Redundancy Check.
 Transmission Modes:
o Simples.
o Half Duplex.
o Full Duplex.
 Data Link & Protocol.

A data communication (command) processor is an I/O processor that distributes and

collects data from remote terminals connected through telephone and other
communication lines. In processor communication, processor communicates with the
I/O device through a common bus i.e. data and control with sharing by each peripheral.
In data communication, processor communicates with each terminal through a single
pair of wires.

The way that remote terminals are connected to a data communication processor is via
telephone lines or other public or private communication facilities. The data
communication may be either through synchronous transmission or through
asynchronous transmission. One of the functions of data communication processor is
check for transmission errors. An error can be detected by checking the parity in each
character received. The other ways are checksum, longitudinal redundancy check
(LRC) and cyclic redundancy check (CRC).

Data can be transmitted between two points through three different modes. First is
simplex where data can be transmitted in only one direction such as TV broadcasting.
Second is half duplex where data can be transmitted in both directions at a time such as
walkie-talkie. The third is full duplex where data can be transmitted in both directions
simultaneously such as telephone.

The communication lines, modems and other equipment used in the transmission of
information between two or more stations is called data link. The orderly transfer of
information in a data link is accomplished by means of a protocol.
 CONTROL UNIT
The Control Unit is the part of the computer’s central processing unit (CPU), which directs
the operation of the processor. It was included as part of the Von Neumann Architecture by
John von Neumann. It is the responsibility of the control unit to tell the computer’s memory,
arithmetic/logic unit, and input and output devices how to respond to the instructions that
have been sent to the processor. It fetches internal instructions of the programs from the main
memory to the processor instruction register, and based on this register contents, the control
unit generates a control signal that supervises the execution of these instructions. A control
unit works by receiving input information which it converts into control signals, which are
then sent to the central processor. The computer’s processor then tells the attached hardware
what operations to perform. The functions that a control unit performs are dependent on the
type of CPU because the architecture of the CPU varies from manufacturer to manufacturer.

Examples of devices that require a CU are:

 Control Processing Units(CPUs)
 Graphics Processing Units(GPUs)

FUNCTIONS OF THE CONTROL UNIT

 It coordinates the sequence of data movements into, out of, and between a
processor’s many sub-units.
 It interprets instructions.
 It controls data flow inside the processor.
 It receives external instructions or commands to which it converts to sequence of
control signals.
 It controls many execution units(i.e. ALU, data buffers and registers) contained
within a CPU.
 It also handles multiple tasks, such as fetching, decoding, execution handling
and storing results.

TYPES OF CONTROL UNIT

There are two types of control units:
 Hardwired
 Micro programmable control unit.

A. HARDWIRED CONTROL UNIT

In the Hardwired control unit, the control signals that are important for instruction
execution control are generated by specially designed hardware logical circuits,
in which we can not modify the signal generation method without physical change
of the circuit structure. The operation code of an instruction contains the basic
data for control signal generation. In the instruction decoder, the operation code
is decoded. The instruction decoder constitutes a set of many decoders that
decode different fields of the instruction opcode.
As a result, few output lines going out from the instruction decoder obtains active
signal values. These output lines are connected to the inputs of the matrix that
generates control signals for execution units of the computer. This matrix
implements logical combinations of the decoded signals from the instruction
opcode with the outputs from the matrix that generates signals representing
consecutive control unit states and with signals coming from the outside of the
processor, e.g. interrupt signals. The matrices are built in a similar way as a
programmable logic arrays.

Control signals for an instruction execution have to be generated not in a single

time point but during the entire time interval that corresponds to the instruction
execution cycle. Following the structure of this cycle, the suitable sequence of
 internal states is organized in the control unit. A number of signals generated
by the control signal generator matrix are sent back to inputs of the next
control state generator matrix.
This matrix combines these signals with the timing signals, which are
generated by the timing unit based on the rectangular patterns usually supplied
by the quartz generator. When a new instruction arrives at the control unit, the
control units is in the initial state of new instruction fetching. Instruction
decoding allows the control unit enters the first state relating execution of the
new instruction, which lasts as long as the timing signals and other input
signals as flags and state information of the computer remain unaltered.

A change of any of the earlier mentioned signals stimulates the change of the
control unit state. This causes that a new respective input is generated for the
control signal generator matrix. When an external signal appears, (e.g. an
interrupt) the control unit takes entry into a next control state that is the state
concerned with the reaction to this external signal (e.g. interrupt processing).

The values of flags and state variables of the computer are used to select
suitable states for the instruction execution cycle. The last states in the cycle
are control states that commence fetching the next instruction of the program:
sending the program counter content to the main memory address buffer
register and next, reading the instruction word to the instruction register of
computer. When the ongoing instruction is the stop instruction that ends
program execution, the control unit enters an operating system state, in which
it waits for a next user directive.

B. MICRO PROGRAMMABLE CONTROL UNIT

The fundamental difference between these unit structures and the structure of the
hardwired control unit is the existence of the control store that is used for storing
words containing encoded control signals mandatory for instruction execution.
In microprogrammed control units, subsequent instruction words are fetched into
the instruction register in a normal way. However, the operation code of each
instruction is not directly decoded to enable immediate control signal generation
but it comprises the initial address of a microprogram contained in the control
store.

 WITH A SINGLE-LEVEL CONTROL STORE:

In this, the instruction opcode from the instruction register is sent to the control
store address register. Based on this address, the first microinstruction of a
microprogram that interprets execution of this instruction is read to
the microinstruction register. This microinstruction contains in its operation
part encoded control signals, normally as few bit fields. In a set
microinstruction field decoders, the fields are decoded. The microinstruction
also contains the address of the next microinstruction of the given instruction
microprogram and a control field used to control activities of the
microinstruction address generator.
 The last mentioned field decides the addressing mode (addressing operation)
to be applied to the address embedded in the ongoing microinstruction. In
microinstructions along with conditional addressing mode, this address is
refined by using the processor condition flags that represent the status of
computations in the current program.

The last microinstruction in the instruction of the given microprogram is the

microinstruction that fetches the next instruction from the main memory to the
instruction register.

 WITH A TWO-LEVEL CONTROL STORE:

In this, in a control unit with a two-level control store, besides the control
memory for microinstructions, a nano-instruction memory is included. In such
a control unit, microinstructions do not contain encoded control signals. The
operation part of microinstructions contains the address of the word in the nano-
instruction memory, which contains encoded control signals.

The nano-instruction memory contains all combinations of control signals that

appear in microprograms that interpret the complete instruction set of a given
computer, written once in the form of nano-instructions.
 In this way, unnecessary storing of the same operation parts of
microinstructions is avoided. In this case, microinstruction word can be much
shorter than with the single level control store. It gives a much smaller size in
bits of the microinstruction memory and, as a result, a much smaller size of
the entire control memory. The microinstruction memory contains the control
for selection of consecutive microinstructions, while those control signals are
generated at the basis of nano-instructions. In nano-instructions, control
signals are frequently encoded using 1 bit/ 1 signal method that eliminates
decoding.

ADVANTAGES OF A WELL-DESIGNED CONTROL UNIT

 Efficient instruction execution: A well-designed control unit can execute

instructions more efficiently by optimizing the instruction pipeline and
minimizing the number of clock cycles required for each instruction.
 Improved performance: A well-designed control unit can improve the
performance of the CPU by increasing the clock speed, reducing the latency, and
improving the throughput.
 Support for complex instructions: A well-designed control unit can support
complex instructions that require multiple operations, reducing the number of
instructions required to execute a program.
 Improved reliability: A well-designed control unit can improve the reliability
of the CPU by detecting and correcting errors, such as memory errors and pipeline
stalls.
 Lower power consumption: A well-designed control unit can reduce power
consumption by optimizing the use of resources, such as registers and memory,
and reducing the number of clock cycles required for each instruction.
  Better branch prediction: A well-designed control unit can improve branch
prediction accuracy, reducing the number of branch mispredictions and improving
performance.
 Improved scalability: A well-designed control unit can improve the scalability
of the CPU, allowing it to handle larger and more complex workloads.
 Better support for parallelism: A well-designed control unit can better support
parallelism, allowing the CPU to execute multiple instructions simultaneously and
improve overall performance.
 Improved security: A well-designed control unit can improve the security of
the CPU by implementing security features such as address space layout
randomization and data execution prevention.
 Lower cost: A well-designed control unit can reduce the cost of the CPU by
minimizing the number of components required and improving manufacturing
efficiency.

DISADVANTAGES OF A POORLY-DESIGNED CONTROL UNIT

 Reduced performance: A poorly-designed control unit can reduce the

performance of the CPU by introducing pipeline stalls, increasing the latency, and
reducing the throughput.
 Increased complexity: A poorly-designed control unit can increase the
complexity of the CPU, making it harder to design, test, and maintain.
 Higher power consumption: A poorly-designed control unit can increase power
consumption by inefficiently using resources, such as registers and memory, and
requiring more clock cycles for each instruction.
 Reduced reliability: A poorly-designed control unit can reduce the reliability of
the CPU by introducing errors, such as memory errors and pipeline stalls.
 Limitations on instruction set: A poorly-designed control unit may limit the
instruction set of the CPU, making it harder to execute complex instructions and
limiting the functionality of the CPU.
 Inefficient use of resources: A poorly-designed control unit may inefficiently
use resources such as registers and memory, leading to wasted resources and
reduced performance.
 Limited scalability: A poorly-designed control unit may limit the scalability of
the CPU, making it harder to handle larger and more complex workloads.
 Poor support for parallelism: A poorly-designed control unit may limit the
ability of the CPU to support parallelism, reducing the overall performance of the
system.
 Security vulnerabilities: A poorly-designed control unit may introduce security
vulnerabilities, such as buffer overflows or code injection attacks.
 Higher cost: A poorly-designed control unit may increase the cost of the CPU
by requiring additional components or increasing the manufacturing complexity.
 INSTRUCTION SET ARCHITECTURE OF A CPU

REGISTERS:-

A register is a small and temporary storage unit inside a computer’s central processing
unit (CPU). It plays a vital role in holding the data required by the CPU for immediate
processing and is made up of flip-flops. It usually holds a limited amount of data ranging
from 8 to 64 bits, depending on the processor architecture. Registers act as intermediate
storage for data during arithmetic logic and other processing operations.

A register is a tiny, fast storage memory within the central processing unit (CPU) or
the arithmetic logic unit (ALU) of a computer. Registers are utilized for a variety of functions
in handling and controlling instructions and data and play an important role in the operation
of a computer’s CPU.

MEMORY HIERARCHY AND THE ROLE OF REGISTERS

Computer systems have a memory hierarchy that includes multiple levels of memory with
varying access speeds and capacities. At the top of this hierarchy are the CPU registers, which
play a vital role in enhancing CPU performance. Registers are small, high-speed storage units
located within the CPU itself, providing fast access to frequently used data.

The memory hierarchy typically includes the following levels:

1. CPU Registers: The temporary storage units within the CPU are directly
accessible by the processor. They hold data required for immediate processing and
act as intermediate storage during operations.
2. Cache Memory: The fast memory located between the CPU and main
memory. Cache memory exploits the principle of temporal locality, caching
 frequently accessed data to reduce the need to access slower main memory
frequently.
3. Logic, (RAM): Slower than cache memory but larger in capacity the main
memory holds data and instructions that are currently being used by the CPU.
4. Secondary Storage: The slowest but highest-capacity memory used for the
long-term storage of data and programs.

TYPES OF REGISTERS:-

1. ACCUMULATOR REGISTER: The accumulator acts as a central point for

arithmetic and logical operations within the CPU. It fetches data from memory
and stores intermediate results during calculations. Arithmetic operations such as
addition, subtraction, multiplication, and division often take place in the
accumulator. The final result may be stored in the accumulator or transferred to
other registers or memory locations.

2. PROGRAM COUNTER (PC) REGISTER: The program counter is a special

register that keeps track of the memory address of the next instruction to be
fetched and executed. As the CPU executes each instruction in sequence the
program counter is updated to indicate the next instruction’s address in memory.
This process continues until the program’s execution is complete.

3. GENERAL-PURPOSE REGISTERS: General-purpose registers are versatile

because they can hold data and memory addresses. They are used for various
calculations and data manipulation tasks during program execution. General-
purpose registers are essential for performing arithmetic and logical operations on
data stored in the CPU.

4. INSTRUCTION REGISTER (IR): The instruction register holds the currently

fetched instruction from memory. It allows the CPU to decode and execute the
instruction based on its opcode and operands.

5. MEMORY ADDRESS REGISTER (MAR): The memory address

register stores the memory address of data or instructions to be accessed or written
in memory. It plays a crucial role in memory operations by indicating the location
of the data or instruction the CPU needs to access.

6. MEMORY DATA REGISTER (MDR): The Memory Data Register holds the
actual data fetched from or written to memory. When the CPU retrieves data from
memory, it is temporarily stored in the MDR before being processed further.

7. STACK POINTER (SP): The stack pointer is used in stack-based memory

operations. It keeps track of the top of the stack. which is a region of memory used
for temporary storage of data and return addresses during function calls.
 8. FLOATING-POINT REGISTERS: The Floating-point registers are
specialized for handling floating-point numbers and performing floating-point
arithmetic operations. These registers can store and manipulate floating-point
numbers with higher precision.

APPLICATIONS OF REGISTERS:-

1. ARITHMETIC AND LOGIC OPERATIONS: The Registers are extensively

used during arithmetic and logic operations in the CPU. They temporarily store
operands, intermediate results, and flags facilitating quick and efficient
calculations.

2. INSTRUCTION EXECUTION: The Registers play a crucial role in the

execution of machine instructions. They hold instructions and data needed for
immediate processing ensuring smooth program execution.

3. CPU PIPELINING: The pipelining is employed to increase performance by

overlapping the execution of multiple instructions. Registers help in holding
intermediate results and data between different stages of the pipeline.

4. CONTEXT SWITCHING: the CPU switches between different processes or

threads. it needs to save and restore the context of each process. Registers are used
to store the CPU’s state including the program counter stack pointer and general-
purpose registers during context switching.

5. MEMORY ADDRESSING: The memory address register (MAR) and memory

data register (MDR) are involved in memory operations. MAR holds the memory
address being accessed. while MDR temporarily stores data fetched from or
written to memory.

6. INPUT/OUTPUT OPERATIONS: The Registers are used to buffer data during

input/output operations. Input data is stored in input registers and output data is
temporarily held in output registers before being processed further.

7. FLOATING-POINT OPERATIONS: To Specialized floating-point registers

are used for handling floating-point arithmetic operations. These registers can
store and manipulate floating-point numbers with higher precision.

8. CONTROL UNIT OPERATIONS: The Registers play a critical role in the

control unit of the CPU. They hold control signals and flags that determine the
control flow and sequencing of the instructions during program execution.
ADVANTAGES AND DISADVANTAGES :
Advantages Disadvantages

1. Speed: The Registers offer fast access 1. Limited Capacity: The Registers have
times due to their proximity to the CPU, a small size, restricting the amount of data
enhancing overall system performance. they can hold at a time.

2. Data Processing Efficiency: They 2. Cost: The Registers are made from flip-
enable quick data manipulation, reducing flops and require more hardware,
the need to access slower main memory contributing to the overall cost of the
frequently. processor.
 INSTRUCTION EXECUTION CYCLE
In computer organization, an instruction cycle, also known as a fetch-decode-execute cycle,
is the basic operation performed by a central processing unit (CPU) to execute an instruction.
The instruction cycle consists of several steps, each of which performs a specific function in
the execution of the instruction. The major steps in the instruction cycle are:

1. Fetch: In the fetch cycle, the CPU retrieves the instruction from memory. The
instruction is typically stored at the address specified by the program counter
(PC). The PC is then incremented to point to the next instruction in memory.

2. Decode: In the decode cycle, the CPU interprets the instruction and determines
what operation needs to be performed. This involves identifying the opcode and
any operands that are needed to execute the instruction.

3. Execute: In the execute cycle, the CPU performs the operation specified by the
instruction. This may involve reading or writing data from or to memory,
performing arithmetic or logic operations on data, or manipulating the control
flow of the program.

There are also some additional steps that may be performed during the instruction
cycle, depending on the CPU architecture and instruction set:

Fetch operands: In some CPUs, the operands needed for an instruction are
fetched during a separate cycle before the execute cycle. This is called the
fetch operands cycle.

Store results: In some CPUs, the results of an instruction are stored during a
separate cycle after the execute cycle. This is called the store results cycle.

Interrupt handling: In some CPUs, interrupt handling may occur during any
cycle of the instruction cycle. An interrupt is a signal that the CPU receives
from an external device or software that requires immediate attention. When
an interrupt occurs, the CPU suspends the current instruction and executes an
interrupt handler to service the interrupt.

These cycles are the basic building blocks of the CPU’s operation and are performed
for every instruction executed by the CPU. By optimizing these cycles, CPU designers
can improve the performance and efficiency of the CPU, allowing it to execute
instructions faster and more efficiently.
THE INSTRUCTION CYCLE –

Each phase of Instruction Cycle can be decomposed into a sequence of elementary micro-
operations. In the above examples, there is one sequence each for the Fetch, Indirect,
Execute and Interrupt Cycles.

The Indirect Cycle is always followed by the Execute Cycle. The Interrupt Cycle is always
followed by the Fetch Cycle. For both fetch and execute cycles, the next cycle depends on
the state of the system.
We assumed a new 2-bit register called Instruction Cycle Code (ICC). The ICC designates
the state of processor in terms of which portion of the cycle it is in:-

00 : Fetch Cycle
01 : Indirect Cycle
10 : Execute Cycle
11 : Interrupt Cycle
At the end of each cycle, the ICC is set appropriately. The above flowchart of Instruction
Cycle describes the complete sequence of micro-operations, depending only on the
instruction sequence and the interrupt pattern (this is a simplified example). The operation of
the processor is described as the performance of a sequence of micro-operation.
DIFFERENT INSTRUCTION CYCLES:

A. The Fetch Cycle –

At the beginning of the fetch cycle, the address of the next instruction to be
executed is in the Program Counter (PC).

 Step 1: The address in the program counter is moved to the memory address
register (MAR), as this is the only register which is connected to address lines of
the system bus.

 Step 2: The address in MAR is placed on the address bus, now the control
unit issues a READ command on the control bus, and the result appears on
the data bus and is then copied into the memory buffer register (MBR).
Program counter is incremented by one, to get ready for the next instruction.
(These two actions can be performed simultaneously to save time)
 Step 3: The content of the MBR is moved to the instruction register(IR)

 Thus, a simple Fetch Cycle consist of three steps and four micro-operation.
Symbolically, we can write these sequence of events as follows:-

Here ‘I’ is the instruction length. The notations (t1, t2, t3) represents successive
time units. We assume that a clock is available for timing purposes and it emits
regularly spaced clock pulses. Each clock pulse defines a time unit. Thus, all time
units are of equal duration. Each micro-operation can be performed within the
time of a single time unit.

 First time unit: Move the contents of the PC to MAR.

 Second time unit: Move contents of memory location specified by MAR
to MBR. Increment content of PC by I.
 Third time unit: Move contents of MBR to IR.
Note: Second and third micro-operations both take place during the second
time unit.

B. THE INDIRECT CYCLES –

Once an instruction is fetched, the next step is to fetch source operands. Source
Operand is being fetched by indirect addressing (it can be fetched by any addressing
mode, here its done by indirect addressing). Register-based operands need not be fetched.
Once the opcode is executed, a similar process may be needed to store the result in main
memory. Following micro-operations takes place:-
 Step 1: The address field of the instruction is transferred to the MAR. This is used
to fetch the address of the operand.

Step 2: The address field of the IR is updated from the MBR.(So that it now
contains a direct addressing rather than indirect addressing).

Step 3: The IR is now in the state, as if indirect addressing has not been occurred.

Note: Now IR is ready for the execute cycle, but it skips that cycle for a moment
to consider the Interrupt Cycle .

C. EXECUTE CYCLE:-

The other three cycles (Fetch, Indirect and Interrupt) are simple and predictable. Each
of them requires simple, small and fixed sequence of micro-operation. In each case same
micro-operation are repeated each time around.

Execute Cycle is different from them. Like, for a machine with N different opcodes there
are N different sequence of micro-operations that can occur.

Lets take an hypothetical example :-

Consider an add instruction:

 Here, this instruction adds the content of location X to register R. Corresponding

micro-operation will be:-

We begin with the IR containing the ADD instruction.

 Step 1: The address portion of IR is loaded into the MAR.

Step 2: The address field of the IR is updated from the MBR, so the reference
memory location is read.

Step 3: Now, the contents of R and MBR are added by the ALU.

Lets take a complex example :-

Here, the content of location X is incremented by 1. If the result is 0, the next

instruction will be skipped. Corresponding sequence of micro-operation will be:-

 Here, the PC is incremented if (MBR) = 0. This test (is MBR equal to zero or not)
and action (PC is incremented by 1) can be implemented as one micro-operation.

Note : This test and action micro-operation can be performed during the same
time unit during which the updated value MBR is stored back to memory.
D. THE INTERRUPT CYCLE:
At the completion of the Execute Cycle, a test is made to determine whether any
enabled interrupt has occurred or not. If an enabled interrupt has occurred then
Interrupt Cycle occurs. The nature of this cycle varies greatly from one machine to
another.
Lets take a sequence of micro-operation:-

 Step 1: Contents of the PC is transferred to the MBR, so that they can be saved
for return.

Step 2: MAR is loaded with the address at which the contents of the PC are to be
saved.

PC is loaded with the address of the start of the interrupt-processing routine.

Step 3: MBR, containing the old value of PC, is stored in memory.

Note: In step 2, two actions are implemented as one micro-operation. However,

most processor provide multiple types of interrupts, it may take one or more
micro-operation to obtain the save_address and the routine_address before they
are transferred to the MAR and PC respectively.
USES OF DIFFERENT INSTRUCTION CYCLES :-
Here are some uses of different instruction cycles:
1. FETCH CYCLE: This cycle retrieves the instruction from memory and loads it
into the processor’s instruction register. The fetch cycle is essential for the
processor to know what instruction it needs to execute.

2. DECODE CYCLE: This cycle decodes the instruction to determine what

operation it represents and what operands it requires. The decode cycle is
important for the processor to understand what it needs to do with the instruction
and what data it needs to retrieve or manipulate.

3. EXECUTE CYCLE: This cycle performs the actual operation specified by the
instruction, using the operands specified in the instruction or in other registers.
The execute cycle is where the processor performs the actual computation or
manipulation of data.

4. STORE CYCLE: This cycle stores the result of the operation in memory or in a
register. The store cycle is essential for the processor to save the result of the
computation or manipulation for future use.

ADVANTAGES:

1. Standardization: The instruction cycle provides a standard way for CPUs to

execute instructions, which allows software developers to write programs that can
run on multiple CPU architectures. This standardization also makes it easier for
hardware designers to build CPUs that can execute a wide range of instructions.

2. Efficiency: By breaking down the instruction execution into multiple steps, the
CPU can execute instructions more efficiently. For example, while the CPU is
performing the execute cycle for one instruction, it can simultaneously fetch the
next instruction.

3. Pipelining: The instruction cycle can be pipelined, which means that multiple
instructions can be in different stages of execution at the same time. This improves
the overall performance of the CPU, as it can process multiple instructions
simultaneously.

DISADVANTAGES:

1. Overhead: The instruction cycle adds overhead to the execution of instructions,

as each instruction must go through multiple stages before it can be executed. This
overhead can reduce the overall performance of the CPU.
2. Complexity: The instruction cycle can be complex to implement, especially if the
CPU architecture and instruction set are complex. This complexity can make it
difficult to design, implement, and debug the CPU.

3. Limited parallelism: While pipelining can improve the performance of the CPU,
it also has limitations. For example, some instructions may depend on the results
of previous instructions, which limits the amount of parallelism that can be
achieved. This can reduce the effectiveness of pipelining and limit the overall
performance of the CPU.

ISSUES OF DIFFERENT INSTRUCTION CYCLES :-

Here are some common issues associated with different instruction cycles:
1. PIPELINE HAZARDS: Pipelining is a technique used to overlap the execution
of multiple instructions by breaking them into smaller stages. However, pipeline
hazards occur when one instruction depends on the completion of a previous
instruction, leading to delays and reduced performance.

2. BRANCH PREDICTION ERRORS: Branch prediction is a technique used to

anticipate which direction a program will take when encountering a conditional
branch instruction. However, if the prediction is incorrect, it can result in wasted
cycles and decreased performance.

3. INSTRUCTION CACHE MISSES: Instruction cache is a fast memory used to

store frequently used instructions. Instruction cache misses occur when an
instruction is not found in the cache and needs to be retrieved from slower
memory, resulting in delays and decreased performance.

4. INSTRUCTION-LEVEL PARALLELISM LIMITATIONS: Instruction-

level parallelism is the ability of a processor to execute multiple instructions
simultaneously. However, this technique has limitations as not all instructions can
be executed in parallel, leading to reduced performance in some cases.

5. RESOURCE CONTENTION: Resource contention occurs when multiple

instructions require the use of the same resource, such as a register or a memory
location. This can lead to delays and reduced performance if the processor is
unable to resolve the contention efficiently.
 RTL REPRESENTATION AND INTERPRETATION OF
INSTRUCTIONS

In symbolic notation, it is used to describe the micro-operations transfer among registers. It

is a kind of intermediate representation (IR) that is very close to assembly language, such as
that which is used in a compiler. The term “Register Transfer” can perform micro-operations
and transfer the result of operation to the same or other register.
Micro-operations :
The operation executed on the data store in registers are called micro-operations. They are
detailed low-level instructions used in some designs to implement complex machine
instructions.

Register Transfer :
The information transformed from one register to another register is represented in symbolic
form by replacement operator is called Register Transfer.

Replacement Operator :
In the statement, R2 <- R1, <- acts as a replacement operator. This statement defines the
transfer of content of register R1 into register R2.

There are various methods of RTL –

General way of representing a register is by the name of the register enclosed in a rectangular
box as shown in (a).
 Register is numbered in a sequence of 0 to (n-1) as shown in (b).
 The numbering of bits in a register can be marked on the top of the box as shown in
(c).
 A 16-bit register PC is divided into 2 parts- Bits (0 to 7) are assigned with lower
byte of 16-bit address and bits (8 to 15) are assigned with higher bytes of 16-bit
address as shown in (d).
Basic symbols of RTL:

REGISTER TRANSFER OPERATIONS:

The operation performed on the data stored in the registers are referred to as register
transfer operations.
There are different types of register transfer operations:
1. Simple Transfer – R2 <- R1
The content of R1 are copied into R2 without affecting the content of R1. It is an
unconditional type of transfer operation.

2. Conditional Transfer –
 It indicates that if P=1, then the content of R1 is transferred to R2. It is a unidirectional
operation.

3. Simultaneous Operations –
If 2 or more operations are to occur simultaneously then they are separated with
comma (,).

If the control function P=1, then load the content of R1 into R2 and at the same clock
load the content of R2 into R1.
 ADDRESSING MODES

Addressing Modes– The term addressing modes refers to the way in which the operand of
an instruction is specified. The addressing mode specifies a rule for interpreting or modifying
the address field of the instruction before the operand is actually executed.

Addressing modes for 8086 instructions are divided into two categories:
1) Addressing modes for data
2) Addressing modes for branch
The 8086 memory addressing modes provide flexible access to memory, allowing you to
easily access variables, arrays, records, pointers, and other complex data types. The key to
good assembly language programming is the proper use of memory addressing modes.
An assembly language program instruction consists of two parts.

IMPORTANT TERMS
 Starting address of memory segment.
 Effective address or Offset: An offset is determined by adding any
combination of three address elements: displacement, base and index.
 Displacement: It is an 8 bit or 16 bit immediate value given in the
instruction.
 Base: Contents of base register, BX or BP.
 Index: Content of index register SI or DI.
According to different ways of specifying an operand by 8086 microprocessor, different
addressing modes are used by 8086.

Addressing modes used by 8086 microprocessor are discussed below:

 Implied mode:: In implied addressing the operand is specified in the instruction

itself. In this mode the data is 8 bits or 16 bits long and data is the part of
instruction. Zero address instruction are designed with implied addressing mode.

Example: CLC (used to reset Carry flag to 0)

 Immediate addressing mode (symbol #): In this mode data is present in
address field of instruction. Designed like one address instruction format.
 Note: Limitation in the immediate mode is that the range of constants are
restricted by size of address field.

Example: MOV AL, 35H (move the data 35H into AL register)
 Register mode: In register addressing the operand is placed in one of 8 bit or 16
bit general purpose registers. The data is in the register that is specified by the
instruction.

Here one register reference is required to access the data.

Example: MOV AX,CX (move the contents of CX register to AX

register)
 Register Indirect mode: In this addressing the operand’s offset is placed in any
one of the registers BX,BP,SI,DI as specified in the instruction. The effective
address of the data is in the base register or an index register that is specified by
the instruction.
Here two register reference is required to access the data.

The 8086 CPUs let you access memory indirectly through a register using the
register indirect addressing modes.

MOV AX, [BX](move the contents of memory location s

addressed by the register BX to the register AX).

 Auto Indexed (increment mode): Effective address of the operand is the

contents of a register specified in the instruction. After accessing the operand, the
contents of this register are automatically incremented to point to the next
consecutive memory location.
 (R1)+.
Here one register reference, one memory reference and one ALU operation is
required to access the data.

Example:
Add R1, (R2)+ // OR
R1 = R1 +M[R2]
R2 = R2 + d
Useful for stepping through arrays in a loop. R2 – start of array d – size of an
element.

 Auto indexed (decrement mode): Effective address of the operand is the

contents of a register specified in the instruction. Before accessing the operand,
the contents of this register are automatically decremented to point to the previous
consecutive memory location.
–(R1)
Here one register reference, one memory reference and one ALU operation is
required to access the data.

Example:
Add R1,-(R2) //OR
R2 = R2-d
R1 = R1 + M[R2]

Auto decrement mode is same as auto increment mode. Both can also be used to
implement a stack as push and pop . Auto increment and Auto decrement modes are
useful for implementing “Last-In-First-Out” data structures.

 Direct addressing/ Absolute addressing Mode (symbol [ ]): The operand’s

offset is given in the instruction as an 8 bit or 16 bit displacement element. In this
addressing mode the 16 bit effective address of the data is the part of the
instruction.
Here only one memory reference operation is required to access the data.

Example:ADD AL,[0301] //add the contents of offset address

0301 to AL
 Indirect addressing Mode (symbol @ or ()): In this mode address field of
instruction contains the address of effective address. Here two references are
required.
1st reference to get effective address.
2nd reference to access the data.
 Based on the availability of Effective address, Indirect mode is of two kind:
1. Register Indirect: In this mode effective address is in the register, and
corresponding register name will be maintained in the address field of
an instruction.

Here one register reference, one memory reference is required to

access the data.

2. Memory Indirect: In this mode effective address is in the memory,

and corresponding memory address will be maintained in the address
field of an instruction.

Here two memory reference is required to access the data.

 Indexed addressing mode: The operand’s offset is the sum of the content of an
index register SI or DI and an 8 bit or 16 bit displacement.

Example:MOV AX, [SI +05]

 Based Indexed Addressing: The operand’s offset is sum of the content of a

base register BX or BP and an index register SI or DI.

Example: ADD AX, [BX+SI]

BASED ON TRANSFER OF CONTROL, ADDRESSING MODES ARE:

 PC relative addressing mode: PC relative addressing mode is used to

implement intra segment transfer of control, In this mode effective address
is obtained by adding displacement to PC.
EA= PC + Address field value
PC= PC + Relative value.
 Base register addressing mode: Base register addressing mode is used
to implement inter segment transfer of control. In this mode effective
address is obtained by adding base register value to address field value.

EA= Base register + Address field value.

PC= Base register + Relative value.
Note:
1. PC relative and based register both addressing modes are
suitable for program relocation at runtime.
2. Based register addressing mode is best suitable to write position
independent codes.
ADVANTAGES OF ADDRESSING MODES

1. To give programmers to facilities such as Pointers, counters for loop controls,

indexing of data and program relocation.
2. To reduce the number bits in the addressing field of the Instruction.
 INSTRUCTION SET
This basically means that an ISA describes the design of a Computer in terms of the basic
operations it must support. The ISA is not concerned with the implementation-specific
details of a computer. It is only concerned with the set or collection of basic operations the
computer must support. For example, the AMD Athlon and the Core 2 Duo processors have
entirely different implementations but they support more or less the same set of basic
operations as defined in the x86 Instruction Set.
1. The ISA defines the types of instructions to be supported by the processor.
Based on the type of operations they perform MIPS Instructions are classified into
3 types:
 Arithmetic / Logic Instructions:
These Instructions perform various Arithmetic & Logical operations
on one or more operands.

 Data Transfer Instructions:

These instructions are responsible for the transfer of instructions from
memory to the processor registers and vice versa.

 Branch and Jump Instructions:

These instructions are responsible for breaking the sequential flow of
instructions and jumping to instructions at various other locations, this
is necessary for the implementation of functions and conditional
statements.

2. The ISA defines the maximum length of each type of instruction. Since the MIPS
is a 32 bit ISA, each instruction must be accommodated within 32 bits.

3. The ISA defines the Instruction Format of each type of instruction.

The Instruction Format determines how the entire instruction is encoded within 32
bits
There are 3 types of Instruction Formats in the MIPS ISA:
 R-Instruction Format.
 I-Instruction Format.
 J-Instruction Format
 Figure – The Abstraction Hierarchy
We note that the Microarchitectural level lies just below the ISA level and hence is
concerned with the implementation of the basic operations to be supported by the Computer
as defined by the ISA. Therefore we can say that the AMD Athlon and Core 2 Duo processors
are based on the same ISA but have different microarchitectures with different performance
and efficiencies.

Instruction Set Architecture Microarchitecture

The Microarchitecture is more concerned

The ISA is responsible for defining the set of with the lower level implementation of
instructions to be supported by the processor. how the instructions are going to be
For example, some of the instructions executed and deals with concepts like
defined by the ARMv7 ISA are given below. Instruction Pipelining, Branch
Prediction, Out of Order Execution.

On the other hand, the Branch

of Computer Organization is
concerned with the implementation of a
particular ISA deals with various
The Branch of Computer Architecture is
hardware implementation techniques, i.e.
more inclined towards the Analysis and
is the Microarchitecture level. For
Design of Instruction Set Architecture. For
Example, ARM licenses other companies
Example, Intel developed
like Qualcomm, Apple for using ARM
the x86 architecture, ARM developed
ISA, but each of these companies have
the ARM architecture, & AMD developed
their own implementations of this ISA
the amd64 architecture. The RISC-V ISA
thereby making them different in
developed by UC Berkeley is an example of
performance and power efficiency.
an Open Source ISA.
The Krait cores developed by Qualcomm
have a different microarchitecture and the
Apple A-series processors have a
different microarchitecture.