PrimeTime® ECO Update

Introducing Clock ECO

Jacob Avidan
Vice President
Design Group, Synopsys

June 7, 2017
Israel

© 2017 Synopsys, Inc. 1 Synopsys Confidential Information

 PrimeTime Physically Aware ECO
Placement and Routing Aware Signoff Timing Closure

• Placement-Aware On-Route Fixing Hierarchical ECO

NDM
IC Compiler II
MPI ECO
Implementation

StarRC • Density-Aware • Load Buffering

• MIM-Aware
ECO Extraction • Blockage-Aware • Load Regrouping
• HyperScale ECO
• Multi-Voltage Aware • Load Shielding

PrimeTime Broad Customer Success

Physically-aware ECO

Source: SNUG and PrimeTime SIG Proceedings

© 2017 Synopsys, Inc. 2 Synopsys Confidential Information

 PrimeTime Clock Skew and DRC Fixing

Higher Setup Fix Rates

• ECO for Best PPA can Exist in Clock Network

– Setup fixing can be limited by data-path sizing and insertion
Setup slack
– Hold fixing may have higher ROI by clock skew ECO -1  0
Setup slack
10

• Fixing Target on Clock Network

+1
– Max transition & max capacitance violations
– Adjusting useful skew for setup & hold violations
Clk_Src Buffer or
inverter pair

• Available Fixing Methods

Adjust Useful Skew to Introduce
– Sizing, buffer insertion, inverter-pair insertion at pins on leaf and New Fixing Opportunities
branch levels in a clock network

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 Feature Description Clock ECO
Overview

• Clock ECO feature available in the PrimeTime 2016.12-SP3 release and later
– DRC violations (max_transition, max_cap, max_fanout) can be fixed on clock network
– Feature provides ability to fix setup and hold violations by changing clock arrival
– Supported in Physically-Aware ECO only

• Benefits of Clock ECO

– Ability to now fix DRC violations in clock network
– Timing violations can be resolved which could not be fixed in data path
– Fixing more timing violations with fewer changes

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 Clock ECO DRC Fixing Techniques

Q
max tran
max cap violation CLK
violation
DRC violation on a clock net Buf2X Buf2X

max tran Q
max cap violation
violation fixed
fixed CLK
DRC violation fixed by upsizing Buf4X Buf2X

max cap
max tran Q
violation
violation
fixed
fixed
CLK
DRC violation fixed by buffering Buf2X Buf4X Buf2X

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 Clock ECO Timing Fixing Techniques
Setup slack =
110ps -10 ps

Launch
D Q D Q

CK CK
Capture

C2 C3

C1 Clock
ECO Slower Capture Clock path allows
more time for setup path
Faster Launch on Launch Flop
Setup slack =
allows more time for setup path 110ps +1 ps

D Q D Q Launch
Upsizing for
faster launch CK CK
Capture
C2 C3

C1 Downsizing for
Buffer insertion for delayed capture
delayed capture
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 Buffer Count Reduction with Clock ECO
Hold Fixing Example

• Data path hold fixing requires 16 buffer insertions • Clock path hold fixing requires only 1 buffer insertion

Q0 D0 Q0 D0

Q1 D1 Q1 D1

Q2 D2 Q2 D2
… … ..... …..

…. ….
Q15 D15 Q15 D15

CK CK CK CK

C1 C2 C1 C2

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 User Interface for Clock ECO

• Option in set_eco_options for Clock ECO to enable loading of Clock Data

–set_eco_options –physical_enable_clock_data
–By Default PT does not read clock routing data from DEF.

• For DRC fixing new option for cell_type “clock_network”

–fix_eco_drc –cell_type clock_network
–When –cell_type clock_network is specified, fixing is only performed on clock network

• For Timing based fixing new option for cell_type “clock_network”

– fix_eco_timing –cell_type clock_network
– When –cell_type clock_network is specified, timing fixing is only done on clock network
– Clock fixing and Data path fixing cannot be done within a single command
– All other options of fix_eco_timing are supported for custom based timing fixing

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 Usage of Inverter Pair Insertion

• Inverter Pair Insertion for Timing and DRC fixing on Clock network
– fix_eco_drc/fix_eco_timing –cell_type clock_network –methods {insert_inverter_pair}
–buffer_list $INVs
– Supports setup, hold and all DRC types
– Inverter pair insertion is only done on clock network to fix clock network violations
– size_cell or insert_inverter_pair can be specified individually or together
– insert_inverter_pair and insert_buffer cannot be used in the same command
– All other options of fix_eco_drc/fix_eco_timing are supported for custom based timing fixing

• Output Example

add_buffer_on_route [get_net -of {CTS_BUF/Z}] -user_specified_buffers { PTECO_17 IVX200 4141.870 954.210 0

PTECO_18 IVX200 4141.870 954.210 0} ……………
insert_buffer [get_pins {reg1/CP}] IVX010 -inverter_pair -new_net_names {PTECO_NET100 PTECO_NET101}
-new_cell_names {PTECO_100 PTECO_101} -location {5459.6050 652.4400 5460.0250 652.4400}

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 User Interface for Clock ECO - Custom Options

VIO
Q0 D0
Q1 VIO D1
VIO D2
• fix_eco_timing -clock_fixes_per_change 4 Q2
: :
VIO D15
– Min number of violations improved to allow a clock change Q15

• fix_eco_timing -clock_max_level_from_reg 3
– Changes can only occur defined levels back from clock pin
4 3 2 1

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 Explanation of -clock_max_level_from_reg
• fix_eco_timing –cell_type clock_network -clock_max_level_from_reg <Value>
• Defualt is “0” meaning changes can occur anywhere in the clock tree
• User has ability to control where ECO can occur relative to the register clock pins

-clock_max_level_from_reg 1

Changes can only occur 1 level B4 B3 B2 B1

back from clock pin

-clock_max_level_from_reg 3

Changes can only occur 3 levels

B4 B3 B2 B1
back from clock pin

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 Controlling Cells used in Clock ECO
• For many designs only certain lib cells can be used in the clock network
– User should remove dont_use or dont_touch attributes for lib cells or clock leaf cells
– set_dont_use [get_lib_cells $valid_clock_buffers] false
– set_dont_touch [get_lib_cells $valid_clock_buffers] false
– set_dont_touch [get_cells $clock_leaf_cells] false

• PrimeTime ECO has the ability to control which lib cells can be used for buffering and sizing
– Buffering: User provide usable Clock buffer buffer list : –buffer_list $valid_clk_buffers
– Sizing: Use set_user_attribute & eco_alternative_cell_attribute_restrictions for clock lib cell
selection
– For Example :

define_user_attribute –type boolean –class lib_cell is_clk_cell

set clk_lcells [get_lib_cell */*CLK*]  Restrict lib cells to these
set_user_attribute $clk_lcells is_clk_cell true
set eco_alternative_cell_attribute_restrictions is_clk_cell

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 Clock ECO fixing
Results

• PrimeTime ECO enhancement enables better fixing results

Design Instance Count Setup Fixing
D1 73K Setup fix rate from 47% to 73%
D4 2.0M Setup fix rate from 14% to 44%

Design Instance Count Hold Fixing

D2 2.7M 17% hold buffer reduction
D3 11M 20% hold buffer reduction
D6 1M 20% less area added, 13% hold buffer reduction

Design Instance Count DRC Fixing

D5 4.5M 96% max transition violations fixed on clock network
D7 2.2M 94% max transition violations fixed on clock network

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 PrimeTime ECO Summary

• PrimeTime continues to focus on smarter ECO technologies to improve productivity

–Expand fixing methods and scope to further improve single-pass fix rate
–Efficient resource utilization to address larger number of signoff scenarios

• Clock ECO
–Fix DRC violations in clock network
–Fix timing violations which could not be fixed in data path
–Correct more timing violations with fewer changes

© 2017 Synopsys, Inc. 14 Synopsys Confidential Information

Thank You