UC284XA

UC384XA

HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER

NOT FOR NEW DESIGN

1 FEATURES Figure 1. Package

■ TRIMMED OSCILLATOR DISCHARGE
CURRENT
■ CURRENT MODE OPERATION TO 500kHz
AUTOMATIC FEED FORWARD DIP-8 SO-8
COMPENSATION
■ LATCHING PWM FOR CYCLE-BY-CYCLE Table 1. Order Codes
CURRENT LIMITING
■ INTERNALLY TRIMMED REFERENCE WITH Part Number Package
UNDERVOLTAGE LOCKOUT
■ HIGH CURRENT TOTEM POLE OUTPUT
UC2842AD1; UC3842AD1;
UC2843AD1; UC3843AD1;
s)
t(
SO-8
UNDERVOLTAGE LOCKOUT WITH UC2844AD1; UC3844AD1;

■
HYSTERESIS
LOW START-UP CURRENT (< 0.5mA)
UC2845AD1; UC3845AD1
UC2842AN; UC3842AN;
u c
DOUBLE PULSE SUPPRESSION UC2843AN; UC3843AN;

o d DIP-8
2 DESCRIPTION
The UC384xA family of control ICs provides the
UC2844AN; UC3844AN;
UC2845AN; UC3845AN
P r
necessary features to implement off-line or DC to
te
DC fixed frequency current mode control schemes
with a minimal external parts count. Internally im-
o le
Differences between members of this family are
the under-voltage lockout thresholds and maxi-
plemented circuits include a trimmed oscillator for
precise DUTY CYCLE CONTROL under voltage
b smum duty cycle ranges. The UC3842A and
UC3844A have UVLO thresholds of 16V (on) and
lockout featuring start-up current less than 0.5mA,
a precision reference trimmed for accuracy at the
- O 10V (off), ideally suited off-line applications The
corresponding thresholds for the UC3843A and
error amp input, logic to insure latched operation,
a PWM comparator which also provides current
( s ) UC3845A are 8.5 V and 7.9V. The UC3842A and
UC3843A can operate to duty cycles approaching

u
signed to source or sink high peak current. Thect
limit control, and a totem pole output stage de- 100%. A range of the zero to < 50 % is obtained by
the UC3844A and UC3845A by the addition of an

o d
output stage, suitable for driving N-Channel MOS- internal toggle flip flop which blanks the output off

Pr
FETs, is low in the off-state.

Figure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A)
every other clock cycle.

et e
l
7
Vi

o UVLO

bs
34V 8
5V VREF
5 S/R
GROUND REF 5V 50mA

INTERNAL

O 4
2.50V

VREF GOOD
LOGIC
BIAS

6
OUTPUT
RT/CT OSC T

ERROR AMP.
+ 2R S
2
VFB - R PWM
R 1V LATCH
1
COMP CURRENT
SENSE
3
CURRENT COMPARATOR
SENSE
D95IN331

REV. 5
May 2004 1/16
UC384XA - UC284XA

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit
Vi Supply Voltage (low impedance source) 30 V
Vi Supply Voltage (Ii < 30mA) Self Limiting
IO Output Current ±1 A
EO Output Energy (capacitive load) 5 µJ
Analog Inputs (pins 2, 3) – 0.3 to 5.5 V
Error Amplifier Output Sink Current 10 mA
Ptot Power Dissipation at Tamb ≤ 25 °C (DIP-8) 1.25 W
Ptot Power Dissipation at Tamb ≤ 25 °C (SO-8) 800 mW
Tstg Storage Temperature Range – 65 to 150 °C
TJ Junction Operating Temperature – 40 to 150 °C
TL Lead Temperature (soldering 10s) 300 °C
* All voltages are with respect to pin 5, all currents are positive into the specified terminal.

Figure 3. DIP-8/SO-8 Pin Connection (Top view)

s)
c t(
d u
COMP 1 8 VREF
r o
VFB 2 7 Vi

e P
ISENSE 3 6

le t
OUTPUT

so
RT/CT 4 5 GROUND

b
D95IN332

O
) -
Table 3. Pin Description
( s
N° Pin
u ct Function

1 COMP
d
This pin is the Error Amplifier output and is made available for loop compensation.

o
2 VFB
Pr This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.

3
t
ISENSE
e e A voltage proportional to inductor current is connected to this input. The PWM uses this

o l information to terminate the output switch conduction.

bs
4 RT/CT The oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible.

O 5 GROUND This pin is the combined control circuitry and power ground.

6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced
and sunk by this pin.

7 VCC This pin is the positive supply of the control IC.

8 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT.

2/16
 UC384XA - UC284XA

Table 4. Thermal Data

Symbol Parameter DIP-8 SO-8 Unit
Rth j-amb Thermal Resistance Junction-ambient Max. 100 150 °C/W

Table 5. Electrical Characteristcs

( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA;
0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
UC284XA UC384XA
Symbol Parameter Test Condition Unit
Min. Typ. Max. Min. Typ. Max.
REFERENCE SECTION
VREF Output Voltage Tj = 25°C Io= 1mA 4.95 5.00 5.05 4.90 5.00 5.10 V
∆VREF Line Regulation 12V ≤ Vi ≤ 25V 2 20 2 20 mV
∆VREF Load Regulation 1 ≤ Io ≤ 20mA 3 25 3 25 mV
∆VREF/∆T Temperature Stability (Note 2) 0.2 0.2 mV/°C
Total Output Variation Line, Load, Temperature 4.9 5.1 4.82 5.18
s) V
eN Output Noise Voltage 10Hz ≤ f ≤ 10KHz
Tj = 25°C (note 2)
50 50

c t( µV

Long Term Stability Tamb = 125°C, 1000Hrs 5 25

d u5 25 mV
(note 2)
r o
ISC Output Short Circuit
OSCILLATOR SECTION
-30 -100

e P
-180 -30 -100 -180 mA

fOSC Frequency
∆fOSC/∆V Frequency Change with Volt.
Tj = 25°C 47

le t
52 57 47 52 57 KHz

so
VCC = 12V to 25V – 0.2 1 – 0.2 1 %
∆VREF/∆T Frequency Change with Temp. TA = Tlow to Thigh – 5 – – 5 – %
VOSC Oscillator Voltage Swing (peak to peak)
Ob – 1.6 – – 1.6 – V
Idischg Discharge Current (VOSC =2V)
ERROR AMP SECTION
TJ = 25°C

) - 7.8 8.3 8.8 7.8 8.3 8.8 mA

( s
ct
V2 Input Voltage VPIN1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V
Ib Input Bias Current VFB = 5V -0.1 -1 -0.1 -2 µA
AVOL
d u 2V ≤ Vo ≤ 4V 65 90 65 90 dB
BW
r
Unity Gain Bandwidth
o TJ = 25°C 0.7 1 0.7 1 MHz
PSRR
Io
e P
Power Supply Rejec. Ratio
Output Sink Current
12V ≤ Vi ≤ 25V
VPIN2 = 2.7V
60
2
70
12
60
2
70
12
dB
mA

l et VPIN1= 1.1V
Io
o Output Source Current VPIN2 = 2.3V VPIN1 = 5V -0.5 -1 -0.5 -1 mA

bs
VOUT High VPIN2 = 2.3V;RL = 15KΩ to 5 6.2 5 6.2 V
Ground

O VOUT Low VPIN2 = 2.7V;RL = 15KΩ to

Pin 8
0.8 1.1 0.8 1.1 V

CURRENT SENSE SECTION

GV Gain (note 3 & 4) 2.85 3 3.15 2.85 3 3.15 V/V
V3 Maximum Input Signal VPIN1 = 5V (note 3) 0.9 1 1.1 0.9 1 1.1 V
SVR Supply Voltage Rejection 12 ≤ Vi ≤ 25V (note 3) 70 70 dB
Ib Input Bias Current -2 -10 -2 -10 µA
Delay to Output 150 300 150 300 ns

3/16
 UC384XA - UC284XA

Table 5. Electrical Characteristcs (continued)

( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA;
0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
UC284XA UC384XA
Symbol Parameter Test Condition Unit
Min. Typ. Max. Min. Typ. Max.
OUTPUT SECTION
VOL Output Low Level ISINK = 20mA 0.1 0.4 0.1 0.4 V
ISINK = 200mA 1.6 2.2 1.6 2.2 V
VOH Output High Level ISOURCE = 20mA 13 13.5 13 13.5 V
ISOURCE = 200mA 12 13.5 12 13.5 V
VOLS UVLO Saturation VCC = 6V; I 0.7 1.2 0.7 1.2 V
SINK = 1mA
tr Rise Time Tj = 25°C 50 150 50 150 ns
CL = 1nF (2)
tf Fall Time Tj = 25°C 50 150 50 150 ns
CL = 1nF (2)

s)
UNDER-VOLTAGE LOCKOUT SECTION
c t(
Start Threshold X842A/4A
X843A/5A
15
7.8
16
8.4
17
9.0
14.5
7.8
d u16
8.4
17.5
9.0
V
V
Min Operating Voltage X842A/4A 9 10 11
r o 8.5 10 11.5 V

PWM SECTION
After Turn-on

e P
Maximum Duty Cycle X842A/3A 94
le t
96 100 94 96 100 %

so
X844A/5A 47 48 50 47 48 50 %
Minimum Duty Cycle 0 0 %
TOTAL STANDBY CURRENT
Ob
Ist Start-up Current
45A
) -
Vi = 6.5V for UCX843A/ 0.3 0.5 0.3 0.5 mA

( s
Vi = 14V for UCX842A/44A 0.3 0.5 0.3 0.5 mA
Ii Operating Supply Current
ct
VPIN2 = VPIN3 = 0V 12 17 12 17 mA

du
Viz Zener Voltage Ii = 25mA 30 36 30 36 V

r o
Notes: 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close
to Tamb as possible.

e P
2. These parameters, although guaranteed, are not 100% tested in production.
3. Parameter measured at trip point of latch with VPIN2 = 0.

l et
4. Gain defined as : A = ∆VPIN1/∆VPIN3; 0 ≤ VPIN3 ≤ 0.8V
5. Adjust Vi above the start threshold before setting at 15 V.

s o
O b

4/16
 UC384XA - UC284XA

Figure 4. Open Loop Test Circuit.

VREF
4.7KΩ RT

2N2222 A Vi
VREF
0.1µF
100KΩ COMP 8
1 7
ERROR AMP. VFB Vi
2 1W
ADJUST 1KΩ 0.1µF
ISENSE 1KΩ
4.7KΩ ISENSE 3 OUTPUT
ADJUST 5KΩ 6 OUTPUT
RT/CT
4 GROUND
5

CT
D95IN343 GROUND

High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and
bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 KΩ
s)
potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
c t(
Figure 5. Oscillator Frequency vs Timing Figure 7. Oscillator Discharge Current vs.
d u
fo
Resistance Temperature.
Idischg
r o
P
D96IN362 D95IN335
(Hz)
(mA)

te Vi=15V

le
VOSC=2V
1M 8.5
CT
=4
70
pF
s o
100K 2.2
1nF

nF

Ob 8.0

-
4.7
nF

(t s)
10K 7.5

u c 7.0
1K
300 1K

o
3K 10K
d 30K RT(Ω) -55 -25 0 25 50 75 100 TA(˚C)

Pr
Figure 6. Maximum Duty Cycle vs Timing Figure 8. Error Amp Open-Loop Gain and

fo
Resistor

et e Phase vs. Frequency.

D95IN337
φ

l (dB)
D96IN363
(Hz)
Vi=15V
o
bs
VO=2V to 4V
80 30
80 RL=100K
Gain
TA=25˚C
O 60
60

40
60

90
Phase
40
20 120

20 0 150

-20 180
0
300 1K 3K 10K 30K RT(Ω) 10 100 1K 10K 100K 1M f(Hz)

5/16
 UC384XA - UC284XA

Figure 9. Current Sense Input Threshold vs. Figure 12. Output Saturation Voltage vs. Load
Error Amp Output Voltage. Current.
Vth D95IN338 Vsat D95IN341
(V) (V)
Source Saturation
Vi=15V Vi
(Load to Ground)
1.0 -1
TA=25˚C TA=-40˚C
TA=25˚C
-2
0.8 Vi=15V
80µs Pulsed Load 120Hz Rate
TA=125˚C
0.6
3

0.4 TA=-40˚C
2
TA=25˚C
TA=-40˚C
0.2 1
Sink Saturation GND
(Load to Vi)
0.0 0
0 2 4 6 VO(V) 0 200 400 600 IO(mA)

Figure 10. Reference Voltage Change vs. Figure 13. Supply Current vs. Supply Voltage.
s)
t(
Source Current..

uc
D95IN339 Ii D95IN342
60 (mA)

50
Vi=15V

o d
40 TA=-40˚C
20

P r
e
let
TA=125˚C 15
30

so
TA=25˚C

RT=10K
UCX843/45

UCX842/44

10 CT=3.3nF
20 VFB=0V

10
Ob 5
ISense=0V
TA=25˚C

-
(s)
0 0
0 20 40 60 80 100 Iref(mA) 0 10 20 30 Vi(V)

Figure 11. Reference Short Circuit Current vs.

c t
Temperature..
d u
ISC
(mA)
r o D95IN340

100
e P Vi=15V
RL≤0.1Ω

90
l et
s o
O b 80

70

60

50
-55 -25 0 25 50 75 100 TA(˚C)

6/16
 UC384XA - UC284XA

Figure 14. Output Waveform. Figure 15. Output Cross Conduction

Figure 16. Oscillator and Output Waveforms.

Vi

s)
8
7 CT

c t(
5V REG
OUTPUT
d u
RT
PWM
6
OUTPUT
r o
LARGE RT/SMALL CT
CLOCK

e P
4
OSCILLATOR

le tCT
ID

s o
CT

Ob OUTPUT

5
GND
) - SMALL RT/LARGE CT

( s
ct
D95IN344

d u
Figure 17. Error Amp Configuration.

r o
e P 2.5V

l et
s o 1mA

O b +

VFB 2
Zi -
COMP 1
Zf
D95IN345

7/16
 UC384XA - UC284XA

Figure 18. Under Voltage Lockout.

7 ON/OFF COMMAND
Vi TO REST OF IC ICC

<17mA
UC3842A UC3843A
UC3844A UC3845A
VON 16V 8.4V <0.5mA
VCC
VOFF 10V 7.6V VOFF VON

D95IN346mod

Figure 19. Current Sense Circuit.

ERROR
AMPL.
s)
t(
2R
IS
COMP
1 R 1V
u c
CURRENT

o d
SENSE
R
CURRENT
3

P r COMPARATOR

RS C SENSE

te
le
5

D95IN347
GND

s o
Peak current (is) is determined by the formula
Ob
) - 1.0V
I Smax ≈ ------------
RS

( s
ct
A small RC filter may be required to suppress switch transients.

Figure 20. Slope Compensation Techniques.

d u
r o
e P
l et VREG
8
VREG
8

s o RT RT

b
RT/CT RT/CT
IS 4 IS 4

O RSLOPE

R1
CT

ISENSE
RSLOPE
R1
CT

ISENSE
3 3
5 5
RS RS
GND GND
D95IN348

8/16
 UC384XA - UC284XA

Figure 21. Isolated MOSFET Drive and Current Transformer Sensing.

VCC Vin

+ ISOLATION
5.0Vref BOUNDARY
-

VGS Waveforms

Q1 + +
+ 6 0 0
- - -
50% DC 25% DC
S
Q V(pin 1) -1.4

-
R Ipk =
3RS
( NN )
S

+
COMP/LATCH 3 R

RS NS NP
s)
t(
C

D95IN349

u c
Figure 22. Latched Shutdown.
o d
P r
4
OSC
te
8
o le
b s R

BIAS

- O R +

(s)
1mA
+ 2R

c t 2
-
EA

u
R

od
1

Pr 2N
3905
5

et e 2N
3903

o l
bs
D95IN350

SCR must be selected for a holding current of less than 0.5mA at TA(min).
The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.

9/16
 UC384XA - UC284XA

Figure 23. Error Amplifier Compensation

+
From VO 2.5V
1mA
Ri + 2R
-
2 EA
Rd Cf Rf R

1
5
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.

+
From VO 2.5V
1mA
RP + 2R
Ri
2
-
EA
R
s)
t(
CP Rd Cf Rf

u c
d
5 D95IN351

o
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.

P r
Figure 24. External Clock Synchronization.
te
o le
VREF
b s
8

- O R

(t s)
BIAS
RT R

u c 4

o d +
OSC

Pr
EXTERNAL
SYNC INPUT
CT

et e 0.01µF +
-
2R

o l 47Ω
2 EA
R

b s 1

O The diode clamp is required if the Sync amplitude is large enough to cause
5
D95IN352

the bottom side of CT to go more than 300mV below ground

10/16
 UC384XA - UC284XA

Figure 25. External Duty Cycle Clamp and Multi Unit Synchronization.

VREF 8

RA R

BIAS
8 4
RB 5K R
6
+ 3 4
5 R OSC
- +
5K Q 7

+ + 2R
2 S 2
- -
EA
C 5K R
1 NE555 1

s) 5

TO ADDITIONAL
c t(
u
UCX84XAs
1.44 RB
f=
(RA + 2RB)C
Dmax =
RA + 2RB

o d D95IN353

P r
Figure 26. Soft-Start Circuit
te
o le
b s
8

- O 5Vref

(t s)
R
+

u c R
BIAS -

o d
Pr 4
+
OSC

et e 1mA S

o l + 2R Q

b s 1MΩ
2
-
EA R 1V
+
-
R

O 1

C 5

D95IN354

11/16
 UC384XA - UC284XA

Figure 27. Soft-Start and Error Amplifier Output Duty Cycle Clamp.

VCC Vin

+
8 5Vref
-
R
+
BIAS - 7
R

4 6
OSC Q1
+

1mA VClamp S
+ 2R - Q 5
2
- R

)
+
EA R 1V

s
R2

t(
1 Comp/Latch

u c RS

d
C R1 BC109

VCLAMP = ·
R1
R1 + R 2
where 0 <VCLAMP <1V Ipk(max) =
VCLAMP
RS
r o D95IN355

e P
le t
s o
Ob
) -
( s
u ct
o d
Pr
et e
o l
b s
O

12/16
 UC384XA - UC284XA

Figure 28. SO-8 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D (1) 4.80 5.00 0.189 0.197

E 3.80 4.00 0.15 0.157

e 1.27 0.050

H 5.80 6.20 0.228 0.244

s)
h 0.25 0.50 0.010 0.020

c t(
L 0.40 1.27 0.016 0.050

d u
o
k 0˚ (min.), 8˚ (max.)

ddd 0.10 0.004

P r
Note: (1) Dimensions D does not include mold flash, protru-
sions or gate burrs.
teSO-8
le
Mold flash, potrusions or gate burrs shall not exceed
0.15mm (.006inch) in total (both side).

s o
Ob
) -
( s
u ct
o d
Pr
et e
o l
b s
O

0016023 C

13/16
 UC384XA - UC284XA

Figure 29. DIP-8 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 3.32 0.131

a1 0.51 0.020

B 1.15 1.65 0.045 0.065

b 0.356 0.55 0.014 0.022

b1 0.204 0.304 0.008 0.012

D 10.92 0.430

E 7.95 9.75 0.313 0.384

e 2.54 0.100

s)
e3 7.62 0.300

c t(
e4 7.62 0.300

d u
F 6.6 0.260

r o
I 5.08 0.200

e P
L 3.18 3.81 0.125 0.150

le t DIP-8

o
Z 1.52 0.060

b s
- O
( s )
u ct
o d
Pr
et e
o l
b s
O

14/16
 UC384XA - UC284XA

Table 6. Revision History

Date Revision Description of Changes

March 1999 4 First Issue in EDOCS

May 2004 5 NOT FOR NEW DESIGN

s)
c t(
d u
r o
e P
le t
s o
Ob
) -
( s
u ct
o d
Pr
et e
o l
b s
O

15/16
 UC384XA - UC284XA

s)
c t(
d u
r o
e P
le t
s o
Ob
) -
( s
u ct
o d
Pr
et e
o l
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

b s
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

Oauthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

© 2004 STMicroelectronics - All rights reserved

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