UC3844, UC3845, UC2844,

UC2845

High Performance
Current Mode Controllers
The UC3844, UC3845 series are high performance fixed frequency
current mode controllers. They are specifically designed for Off−Line
and DC−to−DC converter applications offering the designer a cost http://onsemi.com
effective solution with minimal external components. These integrated
circuits feature an oscillator, a temperature compensated reference, high PDIP−8
gain error amplifier, current sensing comparator, and a high current N SUFFIX
totem pole output ideally suited for driving a power MOSFET. CASE 626
8
Also included are protective features consisting of input and
1
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, a latch for single pulse metering, and a flip−flop which SOIC−14
blanks the output off every other oscillator cycle, allowing output dead 14 D SUFFIX
CASE 751A
times to be programmed for 50% to 70%. 1
These devices are available in an 8−pin dual−in−line plastic package
SOIC−8
as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14
8 D1 SUFFIX
package has separate power and ground pins for the totem pole output CASE 751A
stage. 1
The UCX844 has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off−line converters. The UCX845 is tailored for PIN CONNECTIONS
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off). Compensation 1 8 Vref

Features www.DataSheet4U.com Voltage Feedback 2 7 VCC

• Current Mode Operation to 500 kHz Output Switching Frequency Current Sense 3 6 Output

• Output Deadtime Adjustable from 50% to 70% RT/CT 4 5 GND

• Automatic Feed Forward Compensation (Top View)

• Latching PWM for Cycle−By−Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output Compensation 1 14 Vref

• Input Undervoltage Lockout with Hysteresis NC 2 13 NC

• Low Startup and Operating Current Voltage Feedback 3 12 VCC

• Direct Interface with ON Semiconductor SENSEFETt Products NC 4 11 VC

• Pb−Free Packages are Available Current Sense 5 10 Output

VCC 7(12) NC 6 9 GND

Vref VCC RT/CT 7 8 Power Ground

5.0V
8(14) Undervoltage
Reference
R Lockout (Top View)

Vref VC
R Undervoltage 7(11)
Lockout
ORDERING INFORMATION
RTCT Output See detailed ordering and shipping information in the package
4(7) Oscillator Flip 6(10) dimensions section on page 14 of this data sheet.
Flop
Voltage &
PWR GND
Latching
Feedback +
− PWM
5(8) DEVICE MARKING INFORMATION
2(3) Current See general marking information in the device marking
Error Sense section on page page 14 of this data sheet.
Amplifier 3(5)
1(1)
Output
Comp.
GND 5(9)
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 1. Simplified Block Diagram

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

July, 2006 − Rev. 7 UC3844/D
 UC3844, UC3845, UC2844, UC2845

MAXIMUM RATINGS
Rating Symbol Value Unit
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink (Note 1) IO 1.0 A
Output Energy (Capacitive Load per Cycle) W 5.0 mJ
Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V
Error Amp Output Sink Current IO 10 mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, Case 751A
Maximum Power Dissipation @ TA = 25°C PD 862 mW
Thermal Resistance Junction−to−Air RqJA 145 °C/W
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 25°C PD 1.25 W
Thermal Resistance Junction−to−Air RqJA 100 °C/W
Operating Junction Temperature TJ + 150 °C
Operating Ambient Temperature TA °C
UC3844, UC3845 0 to + 70
UC2844, UC2845 − 25 to + 85
Storage Temperature Range Tstg − 65 to + 150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum Package power dissipation limits must be observed.

ELECTRICAL CHARACTERISTICS (VCC = 15 V, (Note 2), RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh (Note 3), unless otherwise noted.)
UC284X UC384X
Characteristics Symbol Min Typ Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V
Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV
Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV
Temperature Stability TS − 0.2 − − 0.2 − mV/°C
Total Output Variation over Line, Load, Temperature Vref 4.9 − 5.1 4.82 − 5.18 V
Output Noise Voltage (f = 10 Hz to kHz, TJ = 25°C) Vn − 50 − − 50 − mV
Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV
Output Short Circuit Current ISC − 30 − 85 − 180 − 30 − 85 − 180 mA
OSCILLATOR SECTION
Frequency fosc kHz
TJ = 25°C 47 52 57 47 52 57
TA = Tlow to Thigh 46 − 60 46 − 60
Frequency Change with Voltage (VCC = 12 V to 25 V) Dfosc/DV − 0.2 1.0 − 0.2 1.0 %
Frequency Change with Temperature Dfosc/DT − 5.0 − − 5.0 − %
TA = Tlow to Thigh
Oscillator Voltage Swing (Peak−to−Peak) Vosc − 1.6 − − 1.6 − V
Discharge Current (Vosc = 2.0 V, TJ = 25°C) Idischg − 10.8 − − 10.8 − mA
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 V
Input Bias Current (VFB = 2.7 V) IIB − −0.1 −1.0 − −0.1 −2.0 mA
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 − 65 90 − dB
2. Adjust VCC above the Startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3844, UC3845 Thigh = +70°C for UC3844, UC3845
−25°C for UC2844, UC2845 +85°C for UC2844, UC2845

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 UC3844, UC3845, UC2844, UC2845

ELECTRICAL CHARACTERISTICS (VCC = 15 V, (Note 4), RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh (Note 5), unless otherwise noted.)
UC284X UC384X
Characteristics Symbol Min Typ Max Min Typ Max Unit
ERROR AMPLIFIER SECTION (continued)
Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz
Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB
Output Current mA
Sink (VO = 1.1 V, VFB = 2.7 V) ISink 2.0 12 − 2.0 12 −
Source (VO = 5.0 V, VFB = 2.3 V) ISource −0.5 −1.0 − −0.5 −1.0 −

Output Voltage Swing V

High State (RL = 15 k to ground, VFB = 2.3 V) VOH 5.0 6.2 − 5.0 6.2 −
Low State (RL = 15 k to Vref, VFB = 2.7 V) VOL − 0.8 1.1 − 0.8 1.1

CURRENT SENSE SECTION

Current Sense Input Voltage Gain (Notes 6 & 7) AV 2.85 3.0 3.15 2.85 3.0 3.15 V/V
Maximum Current Sense Input Threshold (Note 6) Vth 0.9 1.0 1.1 0.9 1.0 1.1 V
Power Supply Rejection Ratio PSRR dB
VCC = 12 V to 25 V (Note 6) − 70 − − 70 −
Input Bias Current IIB − −2.0 −10 − −2.0 −10 mA
Propagation Delay (Current Sense Input to Output) tPLH(IN/OUT) − 150 300 − 150 300 ns
OUTPUT SECTION
Output Voltage V
Low State (ISink = 20 mA) VOL − 0.1 0.4 − 0.1 0.4
(ISink = 200 mA) − 1.6 2.2 − 1.6 2.2
High State (ISink = 20 mA) 12 13.5 − 13 13.5 −
VOH
(ISink = 200 mA) 12 13.4 − 12 13.4 −
Output Voltage with UVLO Activated VOL(UVLO) V
VCC = 6.0 V, ISink = 1.0 mA − 0.1 1.1 − 0.1 1.1
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold Vth V
UCX844 15 16 17 14.5 16 17.5
UCX845 7.8 8.4 9.0 7.8 8.4 9.0
Minimum Operating Voltage After Turn−On VCC(min) V
UCX844 9.0 10 11 8.5 10 11.5
UCX845 7.0 7.6 8.2 7.0 7.6 8.2
PWM SECTION
Duty Cycle %
Maximum DCmax 46 48 50 47 48 50
Minimum DCmin − − 0 − − 0

TOTAL DEVICE
Power Supply Current (Note 4) ICC mA
Startup:
(VCC = 6.5 V for UCX845A, − 0.5 1.0 − 0.5 1.0
(VCC 14 V for UCX844) Operating − 12 17 − 12 17
Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − 30 36 − V
4. Adjust VCC above the Startup threshold before setting to 15 V.
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3844, UC3845 Thigh = +70°C for UC3844, UC3845
−25°C for UC2844, UC2845 +85°C for UC2844, UC2845
6. This parameter is measured at the latch trip point with VFB = 0 V.
DV Output Compensation
7. Comparator gain is defined as: AV
DV Current Sense Input

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 UC3844, UC3845, UC2844, UC2845

10 75
0 VCC = 15 V

% DT, PERCENT OUTPUT DEADTIME

TA = 25°C
50 1.0 nF
70
RT, TIMING RESISTOR (k Ω )

2.0 nF
20
5.0 nF
65
CT = 10 nF
10
5.0 60

2.0 55 100
NOTE: Output switches
at one−half the oscillator pF
frequency. 200
500 pF
1.0 50 pF
10 k 20 k 50 k 100 k 200 k 500 k 1.0 M 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
fosc, OSCILLATOR FREQUENCY (Hz) fosc, OSCILLATOR FREQUENCY (Hz)

Figure 2. Timing Resistor versus Figure 3. Output Deadtime versus

Oscillator Frequency Oscillator Frequency

VCC = 15 V VCC = 15 V
2.55 V AV = −1.0 3.0 V AV = −1.0
TA = 25°C TA = 25°C
20 mV/DIV

200 mV/DIV
2.5 V 2.5 V

2.45 V 2.0 V

0.5 ms/DIV 1.0 ms/DIV

Figure 4. Error Amp Small Signal Figure 5. Error Amp Large Signal
Transient Response Transient Response
Vth, CURRENT SENSE INPUT THRESHOLD (V)

100 0 1.2
A VOL , OPEN LOOP VOLTAGE GAIN (dB)

VCC = 15 V VCC = 15 V
VO = 2.0 V to 4.0 V
80 1.0
φ, EXCESS PHASE (DEGREES)

RL = 100 K 30
Gain
TA = 25°C
60 60 0.8
TA = 25°C

40 90 0.6
Phase TA = 125°C
20 120 0.4 TA = −55°C

0 150 0.2

−20 180 0
10 100 1.0 k 10 k 100 k 1.0 M 10 M 0 2.0 4.0 6.0 8.0
f, FREQUENCY (Hz) VO, ERROR AMP OUTPUT VOLTAGE (V)

Figure 6. Error Amp Open Loop Gain and Figure 7. Current Sense Input Threshold
Phase versus Frequency versus Error Amp Output Voltage

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 UC3844, UC3845, UC2844, UC2845

Δ V ref , REFERENCE VOLTAGE CHANGE (mV)

SHORT CIRCUIT CURRENT (mA)

0 110
VCC = 15 V
VCC = 15 V
−4.0
RL ≤ 0.1 W

−8.0 90

−12

−16 TA = 125°C 70
TA = −55°C

, REFERENCE
−20 TA = 25°C

−24 50

SC
0 20 40 60 80 100 120 −55 −25 0 25 50 75 100 125
Iref, REFERENCE SOURCE CURRENT (mA) TA, AMBIENT TEMPERATURE (°C)

I
Figure 8. Reference Voltage Change Figure 9. Reference Short Circuit Current
versus Source Current versus Temperature

Δ V , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

Δ V , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

VCC = 15 V VCC = 12 V to 25 V
IO = 1.0 mA to 20 mA TA = 25°C
TA = 25°C
O
O

2.0 ms/DIV 2.0 ms/DIV

Figure 10. Reference Load Regulation Figure 11. Reference Line Regulation

0
V sat , OUTPUT SATURATION VOLTAGE (V)

VCC Source Saturation VCC = 15 V

(Load to Ground) 80 ms Pulsed Load VCC = 15 V
−1.0 TA = 25°C 120 Hz Rate CL = 1.0 nF
90%
TA = 25°C
−2.0
TA = −55°C

3.0
TA = −55°C
2.0 TA = 25°C
10%
1.0 Sink Saturation
(Load to VCC) GN
0 D
0 200 400 600 800 50 ns/DIV
IO, OUTPUT LOAD CURRENT (mA)

Figure 12. Output Saturation Voltage Figure 13. Output Waveform

versus Load Current

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 UC3844, UC3845, UC2844, UC2845

VCC, OUTPUT VOLTAGE 25

VCC = 30 V

20 V/DIV
CL = 15 pF

ICC, SUPPLY CURRENT (mA)

TA = 255C 20

15

10 RT = 10 k

100 mA/DIV
ICC, SUPPLY CURRENT

CT = 3.3 nF

UCX845

UCX844
VFB = 0 V
5 ISense = 0 V
TA = 255C
0
100 ns/DIV 0 10 20 30 40
VCC, SUPPLY VOLTAGE (V)
Figure 14. Output Cross Conduction Figure 15. Supply Current versus
Supply Voltage

PIN FUNCTION DESCRIPTION

Pin
8−Pin 14−Pin Function Description
1 1 Compensation This pin is Error Amplifier output and is made available for loop compensation.
2 3 Voltage This is the inverting input of the Error Amplifier. It is normally connected to the switching
Feedback power supply output through a resistor divider.

3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.

4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and capacitor CT to ground. Operation to 1.0 MHz is possible.

5 − GND This pin is combined control circuitry and power ground (8−pin package only).
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are
sourced and sunk by this pin. The output switches at one−half the oscillator frequency.

7 12 VCC This pin is the positive supply of the control IC.

8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT.
− 8 Power Ground This pin is a separate power ground return (14−pin package only) that is connected back to
the power source. It is used to reduce the effects of switching transient noise on the control
circuitry.
− 11 VC The Output high state (VOH) is set by the voltage applied to this pin (14−pin package only).
With a separate power source connection, it can reduce the effects of switching transient
noise on the control circuitry.
− 9 GND This pin is the control circuitry ground return (14−pin package only) and is connected to back
to the power source ground.

− 2,4,6,13 NC No connection (14−pin package only). These pins are not internally connected.

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 UC3844, UC3845, UC2844, UC2845

OPERATING DESCRIPTION

The UC3844, UC3845 series are high performance, fixed This occurs when the power supply is operating and the load
frequency, current mode controllers. They are specifically is removed, or at the beginning of a soft−start interval
designed for Off−Line and DC−to−DC converter (Figures 21, 22). The Error Amp minimum feedback
applications offering the designer a cost effective solution resistance is limited by the amplifier’s source current
with minimal external components. A representative block (0.5 mA) and the required output voltage (VOH) to reach the
diagram is shown in Figure 16. comparator’s 1.0 V clamp level:
3.0 (1.0 V) + 1.4 V
Oscillator Rf(min) ≈ = 8800 W
0.5 mA
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT Current Sense Comparator and PWM Latch
is charged from the 5.0 V reference through resistor RT to The UC3844, UC3845 operate as a current mode
approximately 2.8 V and discharged to 1.2 V by an internal controller, whereby output switch conduction is initiated by
current sink. During the discharge of CT, the oscillator the oscillator and terminated when the peak inductor current
generates an internal blanking pulse that holds the center reaches the threshold level established by the Error
input of the NOR gate high. This causes the Output to be in Amplifier Output/Compensation (Pin 1). Thus the error
a low state, thus producing a controlled amount of output signal controls the inductor current on a cycle−by−cycle
deadtime. An internal flip−flop has been incorporated in the basis. The current Sense Comparator PWM Latch
UCX844/5 which blanks the output off every other clock configuration used ensures that only a single pulse appears
cycle by holding one of the inputs of the NOR gate high. This at the Output during any given oscillator cycle. The inductor
in combination with the CT discharge period yields output current is converted to a voltage by inserting the ground
deadtimes programmable from 50% to 70%. Figure 2 shows referenced sense resistor RS in series with the source of
RT versus Oscillator Frequency and Figure 3, Output output switch Q1. This voltage is monitored by the Current
Deadtime versus Frequency, both for given values of CT. Sense Input (Pin 3) and compared a level derived from the
Note that many values of RT and CT will give the same Error Amp Output. The peak inductor current under normal
oscillator frequency but only one combination will yield a operating conditions is controlled by the voltage at pin 1
specific output deadtime at a given frequency. where:
In many noise sensitive applications it may be desirable to V(Pin 1) − 1.4 V
frequency−lock the converter to an external system clock. Ipk =
3 RS
This can be accomplished by applying a clock signal to the
circuit shown in Figure 18. For reliable locking, the Abnormal operating conditions occur when the power
free−running oscillator frequency should be set about 10% supply output is overloaded or if output voltage sensing is
less than the clock frequency. A method for multi unit lost. Under these conditions, the Current Sense Comparator
synchronization is shown in Figure 19. By tailoring the threshold will be internally clamped to 1.0 V. Therefore the
clock waveform, accurate Output duty cycle clamping can maximum peak switch current is:
be achieved to realize output deadtimes of greater than 70%. 1.0 V
Ipk(max) =
RS
Error Amplifier When designing a high power switching regulator it
A fully compensated Error Amplifier with access to the becomes desirable to reduce the internal clamp voltage in
inverting input and output is provided. It features a typical order to keep the power dissipation of RS to a reasonable
dc voltage gain of 90 dB, and a unity gain bandwidth of level. A simple method to adjust this voltage is shown in
1.0 MHz with 57 degrees of phase margin (Figure 6). The Figure 20. The two external diodes are used to compensate
noninverting input is internally biased at 2.5 V and is not the internal diodes yielding a constant clamp voltage over
pinned out. The converter output voltage is typically divided temperature. Erratic operation due to noise pickup can result
down and monitored by the inverting input. The maximum if there is an excessive reduction of the Ipk(max) clamp
input bias current is −2.0 mA which can cause an output voltage.
voltage error that is equal to the product of the input bias A narrow spike on the leading edge of the current
current and the equivalent input divider source resistance. waveform can usually be observed and may cause the power
The Error Amp Output (Pin 1) is provide for external loop supply to exhibit an instability when the output is lightly
compensation (Figure 29). The output voltage is offset by loaded. This spike is due to the power transformer
two diode drops (≈ 1.4 V) and divided by three before it interwinding capacitance and output rectifier recovery time.
connects to the inverting input of the Current Sense The addition of an RC filter on the Current Sense Input with
Comparator. This guarantees that no drive pulses appear at a time constant that approximates the spike duration will
the Output (Pin 6) when Pin 1 is at its lowest state (VOL). usually eliminate the instability; refer to Figure 24.

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 UC3844, UC3845, UC2844, UC2845

VCC Vin

VCC 7(12)

Vref 36V
Reference +
8(14) Regulator −
VCC +
R Internal UVLO
2.5V Bias −
+ VC
RT R + − 7(11)
3.6V Vref
− UVLO
Output Q1
Oscillator
4(7) T Q 6(10)
CT +
1.0mA
S Power Ground
+ Q
− 5(8)
Voltage Feedback − 2R R PWM
+
Input 2(3) Latch
Error R 1.0V Current Sense Input
Output Amplifier
Compensation Current Sense 3(5)
1(1) Comparator RS

GND 5(9) + Sink Only

=
− Positive True Logic
Pin numbers in parenthesis are for the D suffix SOIC−14 package.

Figure 16. Representative Block Diagram

Capacitor CT

Latch
‘‘Set’’ Input

Output/
Compensation
Current Sense
Input

Latch
‘‘Reset’’ Input

Output

Large RT/Small CT Small RT/Large CT

Figure 17. Timing Diagram

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 UC3844, UC3845, UC2844, UC2845

Undervoltage Lockout designer added flexibility in tailoring the drive voltage

Two undervoltage lockout comparators have been independent of VCC. A zener clamp is typically connected
incorporated to guarantee that the IC is fully functional to this input when driving power MOSFETs in systems
before the output stage is enabled. The positive power where VCC is greater the 20 V. Figure 23 shows proper
supply terminal (VCC and the reference output (Vref) are power and control ground connections in a current sensing
each monitored by separate comparators. Each has built−in power MOSFET application.
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator Reference
upper and lower thresholds are 16 V/10 V for the UCX844, The 5.0 V bandgap reference is trimmed to ± 1.0%
and 8.4 V/7.6 V for the UCX845. The Vref comparator upper tolerance at TJ = 25°C on the UC284X, and ± 2.0% on the
and lower thresholds are 3.6 V/3/4 V. The large hysteresis UC384X. Its primary purpose is to supply charging current
and low startup current of the UCX844 makes it ideally to the oscillator timing capacitor. The reference has short
suited in off−line converter applications where efficient circuit protection and is capable of providing in excess of
bootstrap startup techniques later required (Figure 30). The 20 mA for powering additional control system circuitry.
UCX845 is intended for lower voltage DC−to−DC converter
applications. A 36 V zener is connected as a shunt regulator
Design Considerations
from VCC to ground. Its purpose is to protect the IC from Do not attempt to construct the converter on
excessive voltage that can occur during system startup. The wire−wrap or plug−in prototype boards. High frequency
minimum operating voltage for the UCX844 is 11 V and circuit layout techniques are imperative to prevent
8.2 V for the UCX845. pulsewidth jitter. This is usually caused by excessive noise
Output pick−up imposed on the Current Sense or Voltage Feedback
These devices contain a single totem pole output stage that inputs. Noise immunity can be improved by lowering circuit
was specifically designed for direct drive of power impedances at these points. The printed circuit layout should
MOSFETs. It is capable of up to ± 1.0 A peak drive current contain a ground plane with low−current signal and
and has a typical rise and fall time of 50 ns with a 1.0 nF load. high−current switch and output grounds returning on
Additional internal circuitry has been added to keep the separate paths back to the input filter capacitor. Ceramic
Output in a sinking mode whenever and undervoltage bypass capacitors (0.1 mF) connected directly to VCC, VC,
lockout is active. This characteristic eliminates the need for and Vref may be required depending upon circuit layout.
an external pull−down resistor. This provides a low impedance path for filtering the high
The SOIC−14 surface mount package provides separate frequency noise. All high current loops should be kept as
pins for VC (output supply) and Power Ground. Proper short as possible using heavy copper runs to minimize
implementation will significantly reduce the level of radiated EMI. The Error Amp compensation circuitry and
switching transient noise imposed on the control circuitry. the converter output voltage divider should be located close
This becomes particularly useful when reducing the Ipk(max) to the IC and as far as possible from the power switch and
clamp level. The separate VC supply input allows the other noise generating components.

Vref

8(14) R
Bias RA 8(14) R
RT R
8 4 Bias
R
RB
OSC 6 5.0k
External + + OSC
CT 4(7) − R
Sync 0.01 3 +
5.0k

5 Q 4(7)
Input +
− 2 + S
2R − 7 +
47 2(3) EA −
R 5.0k MC1455 EA 2R
C 2(3)
R
1(1) 1
1(1)
5(9)
To 5(9)
1.44 RB Additional
The diode clamp is required if the Sync amplitude is large enough to f= Dmax =
(RA + 2RB)C RA + 2RB UCX84XA’s
cause the bottom side of CT to go more than 300 mV below ground.

Figure 18. External Clock Synchronization Figure 19. External Duty Cycle Clamp and
Multi−Unit Synchronization

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 UC3844, UC3845, UC2844, UC2845

VCC
Vin
7(12)

5.0Vref +
− +
8(14) R
Bias + −
R + −
7(11) 5.0Vref
− Q1 8(14) R
OSC Bias +
+ T 6(10) −
4(7) VClamp R +
1.0mA S
+ − Q −
R2 − + R 5(8) OSC
EA 2R
2(3) Comp/Latch 4(7) + T
R
1.0V 3(5) 1.0mA S
1(1) + − Q
RS − + R
R1 EA 2R

1.0M
5(9) 2(3)
R
1.67 1.0V
R1 R2 VClamp 1(1)
VClamp + 0.33 x 10−3 Ipk(max) ≈ C
R1 + R2 RS
R2 5(9)
+1 Where: 0 ≤ VClamp ≤ 1.0 V tSoft−Start  3600C in mF
R1

Figure 20. Adjustable Reduction of Clamp Level Figure 21. Soft−Start Circuit

VCC
Vin
7(12)

+ VCC
5.0Vref − Vin RS Ipk rDS(on)
8(14) R
+ (12) VPin 5 ≈
rDM(on) + RS
Bias + −
R − If: SENSEFET = MTP10N10M
+ +
7(11) 5.0Vref − RS = 200
− Q1 +
OSC Then: Vpin 5 = 0.075 Ipk
+ T 6(10) + − D SENSEFET
4(7) VClamp −
+
1.0mA S (11)
+ − Q S
− + R 5(8) −
EA 2R
2(3)
R Comp/Latch T (10) G K
R2 M
1.0V 3(5) S
1(1) RS − Q
+ R (8)
MPSA63 5(9) Comp/Latch Power Ground
C To Input Source
R1 1.67
VClamp R1 R2 (5) Return
+ 0.33 x 10−3 RS
R2 R1 + R2 1/4 W
+1 Control CIrcuitry
R1
Ground:
VClamp
Ipk(max)≈ Where: 0 ≤ VClamp ≤ 1.0 V To Pin (9)
RS
VC R1 R2 Virtually lossless current sensing can be achieved with the implement of a SENSEFET
tSoftstart = − In 1− C power switch. For proper operation during over current conditions, a reduction of the
3VClamp R1 + R2
Ipk(max) clamp level must be implemented. Refer to Figures 20 and 22.

Figure 22. Adjustable Buffered Reduction of Figure 23. Current Sensing Power MOSFET
Clamp Level with Soft−Start
VCC
Vin
7(12)

5.0Vref +
− +

+ −
+ −
7(11)
− Q1
T 6(10)
S
− Q
+ R 5(8)
Comp/Latch R
3(5) The addition of the RC filter will eliminate
C RS instability caused by the leading edge spike on
the current waveform.

Figure 24. Current Waveform Spike Suppression

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VCC IB
Vin Vin
7(12) +

+ 0
5.0Vref − Base
+ Charge
− Removal
+ −
− C1
+
7(11)
− Rg Q1
Q1
T 6(10) 6(1)
S
− Q
+ R 5(8) 5(8)
Comp/Latch
3(5) 3(5)
RS RS

Series gate resistor Rg will damp any high frequency parasitic oscillations The totem−pole output can furnish negative base current for enhanced
caused by the MOSFET input capacitance and any series wiring inductance transistor turn−off, with the addition of capacitor C1.
in the gate−source circuit.

Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive

8(14) R
Bias
R

VCC Vin
OSC
7(12)
4(7) +
1.0mA
+ Isolation +
5.0Vref − −
+ Boundary EA 2R
2(3)

ÉÉ É
R
+ − VGS Waveforms
−

ÉÉÉ ÉÉ
+ Q1 1(1)
7(11) +
+
− 0 0 MCR 2N 5(9)
− − 101 3905
T 6(10) 50% DC 25% DC
2N
S V(pin 1) − 1.4 NP
− Q 3903
+ R 5(8) Ipk =
3 RS NS
Comp/Latch R
3(5) C NS
RS Np
The MCR101 SCR must be selected for a holding of less than 0.5 mA at TA(min).
The simple two transistor circuit can be used in place of the SCR as shown. All
resistors are 10 k.

Figure 27. Isolated MOSFET Drive Figure 28. Latched Shutdown

From VO
2.5V + From VO
2.5V +
Ri 2(3) 1.0mA
+ Rp 2(3) 1.0mA
− Ri +
EA 2R −
Rd CI Rf EA 2R
R Rd CI Rf
Cp R
1(1)
1(1)
5(9)
Rf ≥ 8.8 k 5(9)

Error Amp compensation circuit for stabilizing any current−mode topology except Error Amp compensation circuit for stabilizing current−mode boost and flyback
for boost and flyback converters operating with continuous inductor current. topologies operating with continuous inductor current.

Figure 29. Error Amplifier Compensation

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 UC3844, UC3845, UC2844, UC2845

L1
+ MBR1635
4.7W MDA 250 4.7k 3300pF 5.0V/4.0A
202 T1 + +
56k 2200 1000
115VA
C 5.0V RTN
MUR110
1N4935 1N4935 12V/0.3A
+ L2 +
1000 10
7(12) + +
68 47 ±12V RTN
100
8(14) 1000 10
5.0Vref + + +
− + −12V/0.3A
0.01 1N4937 MUR110
Bias 680pF L3
+
+ −
33k 7(11) 1N4937
2.7k
4(7) 22W
OSC
1.0nF + T 6(10) MTP
1N5819
18k 4N50
2(3) S
+ Q
− − R 5(8)
EA +
150k
100pF

4.7k Comp/Latch 3(5) 1.0k

1(1) 470pF 0.5W

5(9)

T1 − Primary: 45 Turns # 26 AWG

T1 − Secondary ± 12 V: 9 Turns # 30 AWG Figure 30. 27 Watt Off−Line Flyback Regulator
T1 − (2 strands) Bifiliar Wound
T1 − Secondary 5.0 V: 4 Turns (six strands)
T1 − #26 Hexfiliar Wound
T1 − Secondary Feedback: 10 Turns #30 AWG
T1 − (2 strands) Bifiliar Wound Test Conditions Results
T1 − Core: Ferroxcube EC35−3C8
T1 − Bobbin: Ferroxcube EC35PCB1 Line Regulation: 5.0 V Vin = 95 VAC to 130 VAC D = 50 mV or ± 0.5%
T1 − Gap ≈ 0.01" for a primary inductance of 1.0 mH
± 12 V D = 24 mV or ± 0.1%
L1 − 15 mH at 5.0 A, Coilcraft Z7156. Load Regulation: 5.0 V Vin = 115 VAC, Iout = 1.0 A to 4.0 A D = 300 mV or ± 3.0%
L2, L3 − 25 mH at 1.0 A, Coilcraft Z7157.
± 12 V Vin = 115 VAC, Iout = 100 mA to 300 D = 60 mV or ± 0.25%
mA
Output Ripple: 5.0 V Vin = 115 VAC 40 mVpp
± 12 V 80 mVpp
Efficiency Vin = 115 VAC 70%
All outputs are at nominal load currents, unless otherwise noted.

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Vin = 15V

+
UC3845 7(12) 47 Output Load Regulation
(open loop configuration)

34V IO (mA) VO (V)

8(14) Reference +
0 29.9
Regulator − 2 28.8
VCC + 1N5819
R Internal UVLO 9 28.3
2.5V Bias − 18 27.4
+ 7(11) 36 24.4
10k R + −
3.6V Vref
− UVLO 15 10
4(7) 6(10) 1N5819
Oscillator VO  2 (Vin)
T + +
1.0nF + 47
0.5mA Connect to
S 5(8) Pin 2 for R2
+ 2R Q
2(3) − closed loop
− R PWM operation.
+
Latch
Error R 1.0V 3(5)
1(1) Amplifier R2
VO = 2.5 +1 R1
Current Sense R2
Comparator

5(9)

The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series
resistor may be required when using tantalum or other low ESR capacitors. The converter’s output can provide
excellent line and load regulation by connecting the R2/R1 resistor divider as shown.

Figure 31. Step−Up Charge Pump Converter

Vin = 15V

+
UC3845 7(12) 47

8(14) 34V
Reference +
Regulator −
VCC +
R Internal UVLO
2.5V Bias −
+ 7(11)
10k R + −
3.6V Vref
− UVLO 15 10
4(7) 6(10) 1N5819
Oscillator VO  − (Vin)
T + +
+ 1N5819 47
1.0nF 0.5mA
S 5(8)
+ 2R Q
2(3) −
− R PWM
+ Output Load Regulation
Latch
Error R 1.0V 3(5) IO (mA) VO (V)
1(1) Amplifier
Current Sense 0 −14.4
Comparator 2 −13.2
9 −12.5
5(9) 18 −11.7
32 −10.6
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A.
An additional series resistor may be required when using tantalum or other low ESR capacitors.

Figure 32. Voltage−Inverting Charge Pump Converter

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 UC3844, UC3845, UC2844, UC2845

ORDERING INFORMATION
Device Operating Temperature Range Package Shipping†
UC3844D SOIC−14 55 Units/Rail
UC3844DG SOIC−14 55 Units/Rail
(Pb−Free)
UC3844DR2 SOIC−14 2500 Tape & Reel
UC3844DR2G SOIC−14 2500 Tape & Reel
(Pb−Free)
UC3844N PDIP−8 50 Units/Rail
UC3844NG PDIP−8 50 Units/Rail
(Pb−Free)
TA = 0° to +70°C
UC3845D SOIC−14 55 Units/Rail
UC3845DG SOIC−14 55 Units/Rail
(Pb−Free)
UC3845DR2 SOIC−14 2500 Tape & Reel
UC3845DR2G SOIC−14 2500 Tape & Reel
(Pb−Free)
UC3845N PDIP−8 50 Units/Rail
UC3845NG PDIP−8 50 Units/Rail
(Pb−Free)
UC2844D SOIC−14 55 Units/Rail
UC2844DG SOIC−14 55 Units/Rail
(Pb−Free)
UC2844DR2 SOIC−14 2500 Tape & Reel
UC2844DR2G SOIC−14 2500 Tape & Reel
(Pb−Free)
UC2844N PDIP−8 50 Units/Rail
UC2844NG PDIP−8 50 Units/Rail
(Pb−Free)
TA = −25° to +85°C
UC2845D SOIC−14 55 Units/Rail
UC2845DG SOIC−14 55 Units/Rail
(Pb−Free)
UC2845DR2 SOIC−14 2500 Tape & Reel
UC2845DR2G SOIC−14 2500 Tape & Reel
(Pb−Free)
UC2845N PDIP−8 50 Units/Rail
UC2845NG PDIP−8 50 Units/Rail
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
PDIP−8 SOIC−14 SOIC−8
N SUFFIX D SUFFIX D1 SUFFIX
CASE 626 CASE 751A CASE 751
8
14 8
UC384xN UC384xDG 384x
AWL AWLYWW ALYW
YYWWG G
1 1
1

8
14 x = 4 or 5
UC284xN UC284xDG A = Assembly Location
AWL AWLYWW WL, L = Wafer Lot
YYWWG YY, Y = Year
1 WW, W = Work Week
1 G or G = Pb−Free Package

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PACKAGE DIMENSIONS

PDIP−8
N SUFFIX
CASE 626−05
ISSUE L

NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
8 5 FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B− 3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
F B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
NOTE 2 −A− D 0.38 0.51 0.015 0.020
L F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
C K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10_ −−− 10_
−T− J N 0.76 1.01 0.030 0.040
SEATING N
PLANE
M
D K
H G
0.13 (0.005) M T A M B M

SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G

NOTES:
−A− 1. DIMENSIONING AND TOLERANCING PER
14 8 ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
−B− P 7 PL PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
0.25 (0.010) M B M
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
1 7 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
G R X 45 _ F CONDITION.
C
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
−T− B 3.80 4.00 0.150 0.157
K M J C 1.35 1.75 0.054 0.068
SEATING D 14 PL D 0.35 0.49 0.014 0.019
PLANE
0.25 (0.010) M T B S A S F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

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 UC3844, UC3845, UC2844, UC2845

PACKAGE DIMENSIONS

SOIC−8
D1 SUFFIX
CASE 751−07
ISSUE AG

−X− NOTES:
1. DIMENSIONING AND TOLERANCING PER
A ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
8 5
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL
4 IN EXCESS OF THE D DIMENSION AT
−Y− K MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G
MILLIMETERS INCHES
C N X 45 _ DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
SEATING
PLANE B 3.80 4.00 0.150 0.157
−Z− C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
0.10 (0.004) G 1.27 BSC 0.050 BSC
H M J H 0.10 0.25 0.004 0.010
D J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0 _ 8 _
0.25 (0.010) M Z Y S X S
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

SENSEFET is a trademark of Semiconductor Components Industries, LLC.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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16