Features

• Six High-side and Six Low-side Drivers

• Outputs Freely Configurable as Switch, Half Bridge or H-bridge
• Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
• 0.6A Continuous Current per Switch
• Low-side: RDSon < 1.5Ω versus Total Temperature Range 40-V Dual Hex
• High-side: RDSon < 2.0Ω versus Total Temperature Range
• Very Low Quiescent Current Is < 20 µA in Standby Mode Output Driver
• Outputs Short-circuit Protected
• Overtemperature Prewarning and Protection with Serial Input
• Undervoltage Protection
• Various Diagnosis Functions such as Shorted Output, Open Load, Overtemperature Control
and Power Supply Fail
• Serial Data Interface
• Operation Voltage up to 40V T6816
• Daisy Chaining Possible
• SO28 Power Package

1. Description
The T6816 is a fully protected driver interface designed in 0.8 µm BCDMOS technol-
ogy. It is especially suitable for truck or bus applications and the industrial 24-V
www.DataSheet4U.com

supply. It controls up to 12 different loads via a 16-bit dataword.

Each of the six high-side and six low-side drivers is capable to drive currents up to
600 mA. The drivers are freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC is also designed to easily build
H-bridges to drive DC motors in motion-control applications.
Protection is guaranteed in terms of short-circuit conditions, overtemperature and
undervoltage. Various diagnosis functions and a very low quiescent current in standby
mode open a wide range of applications.
Automotive qualification referring to conducted interferences, EMC protection and
2 kV ESD protection gives added value and enhanced quality for the exacting require-
ments of automotive applications.

Rev. 4595E–BCD–09/05
Figure 1-1. Block Diagram

HS1 HS2 HS3 HS4 HS5 HS6

15 15 13 13 12 12 3 3 2 2 28 28

5
Fault Fault Fault Fault Fault Fault VS
Detect Detect Detect Detect Detect Detect

10
VS
26
DI 6
GND

Osc
25 7
CLK S O H L H L H L H L H L H L S GND
S C L S S S S S S S S S S S S R
I T D 6 6 5 5 4 4 3 3 2 2 1 1 R
VS 8
GND
24 Input Register
Control UV -
CS protection
Output Register logic 9
GND
Thermal
17 L
INH P I S H H L H L H L H L H L T protection 20
S N C S S S S S S S S S S S S P GND
F H D 6 6 5 5 4 4 3 3 2 2 1 1
Power-on
18 reset 21
DO GND

VCC 22
GND

Fault Fault Fault Fault Fault Fault 23

Detect Detect Detect Detect Detect Detect GND

VCC
19
VCC

16 14 11 4 1 27

LS1 LS2 LS3 LS4 LS5 LS6

2 T6816
4595E–BCD–09/05
 T6816
2. Pin Configuration
Figure 2-1. Pinning SO28
HS6 LS6 DI CLK CS GND GND GND GND VCC DO INH LS1 HS1
28 27 26 25 24 23 22 21 20 19 18 17 16 15

T6816

Lead frame

1 2 3 4 5 6 7 8 9 10 11 12 13 14
LS5 HS5 HS4 LS4 VS GND GND GND GND VS LS3 HS3 HS2 LS2

Table 2-1. Pin Description

Pin Symbol Function
Low-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection;
1 LS5
diagnosis for short and open load
High-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection;
2 HS5
diagnosis for short and open load
3 HS4 High-side driver output 4; see pin 2
4 LS4 Low-side driver output 4; see pin 1
5 VS Power supply output stages HS4, HS5, HS6, internal supply; external connection to pin 10 necessary
6, 7, 8, 9 GND Ground; reference potential; internal connection to pin 20-23; cooling tab
10 VS Power supply output stages HS1, HS2 and HS3
11 LS3 Low-side driver output 3; see pin 1
12 HS3 High-side driver output 3; see pin 2
13 HS2 High-side driver output 2; see pin 2
14 LS2 Low-side driver output 2; see pin 1
15 HS1 High-side driver output 1; see pin 2
16 LS1 Low-side driver output 1; see pin 1
17 INH Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operating
Serial data output; 5V CMOS logic level tri-state output for output (status) register data; sends 16-bit status
18 DO information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless device is
selected by CS = low, therefore, several ICs can operate on one data output line only.
19 VCC Logic supply voltage (5V)
20-23 GND Ground; see pin 6-9
Chip select input; 5V CMOS logic level input with internal pull up;
24 CS
low = serial communication is enabled, high = disabled
Serial clock input; 5V CMOS logic level input with internal pull down;
25 CLK
controls serial data input interface and internal shift register (fmax = 2 MHz)
Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control
26 DI
device; DI expects a 16-bit control word with LSB being transferred first
27 LS6 Low-side driver output 6; see pin 1
28 HS6 High-side driver output 6; see pin 2

3
4595E–BCD–09/05
3. Functional Description

3.1 Serial Interface

Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.

Figure 3-1. Data Transfer Input Data Protocol

CS

DI SRR LS1 HS1 LS2 HS2 LS3 HS3 LS4 HS4 LS5 HS5 LS6 HS6 OLD SCT SI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK

DO TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD INH PSF

Table 3-1. Input Data Protocol

Bit Input Register Function
Status register reset (high = reset; the bits PSF, SCD and
0 SRR
overtemperature shutdown in the output data register are set to low)
1 LS1 Controls output LS1 (high = switch output LS1 on)
2 HS1 Controls output HS1 (high = switch output HS1 on)
3 LS2 See LS1
4 HS2 See HS1
5 LS3 See LS1
6 HS3 See HS1
7 LS4 See LS1
8 HS4 See HS1
9 LS5 See LS1
10 HS5 See HS1
11 LS6 See LS1
12 HS6 See HS1
13 OLD Open load detection (low = on)
Programmable time delay for short circuit
14 SCT
(shutdown delay high/low = 12 ms/1.5 ms)
Software inhibit; low = standby, high = normal operation
15 SI (data transfer is not affected by standby function because the digital part
is still powered)

4 T6816
4595E–BCD–09/05
 T6816
Table 3-2. Output Data Protocol
Output (Status)
Bit Register Function
Temperature prewarning: high = warning
0 TP
(overtemperature shutdown see remark below)
Normal operation: high = output is on, low = output is off
1 Status LS1 Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched off)
Normal operation: high = output is on, low = output is off
2 Status HS1 Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched off)
3 Status LS2 Description see LS1
4 Status HS2 Description see HS1
5 Status LS3 Description see LS1
6 Status HS3 Description see HS1
7 Status LS4 Description see LS1
8 Status HS4 Description see HS1
9 Status LS5 Description see LS1
10 Status HS5 Description see HS1
11 Status LS6 Description see LS1
12 Status HS6 Description see HS1
Short circuit detected: set high, when at least one output is switched off by a
13 SCD
short circuit condition
Inhibit: this bit is controlled by software (bit SI in input register) and hardware
14 INH
inhibit (pin 17). High = standby, low = normal operation
15 PSF Power supply fail: undervoltage at pin VS detected
Note: Bit 0 to 15 = high: overtemperature shutdown

Table 3-3. Status of the Input Register after Power on Reset

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(SI) (SCT) (OLD) (HS6) (LS6) (HS5) (LS5) (HS4) (LS4) (HS3) (LS3) (HS2) (LS2) (HS1) (LS1) (SRR)
H H H L L L L L L L L L L L L L

5
4595E–BCD–09/05
3.2 Power Supply Fail
In case of undervoltage at pin VS, an internal timer is started. When the undervoltage delay time
(tdUV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output regis-
ter is set and all outputs are disabled. When normal voltage is present again, the outputs are
enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input
register.

3.3 Open-load Detection

If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and
a pull-down current for each low-side switch is turned on (open-load detection current IHS1-6,
ILS1-6). If VVS – VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condi-
tion), the corresponding bit of the output in the output register is set to high. Switching on an
output stage with OLD bit set to low disables the open-load function for this output.

3.4 Overtemperature Protection

If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature
prewarning bit (TP) in the output register is set. When the temperature falls below the thermal
prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a
complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the
microcontroller has read this information, CS is set high and the data transfer is interrupted with-
out affecting the state of the input and output registers.
If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are
disabled and all bits in the output register are set high. The outputs can be enabled again when
the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has
been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold
have hysteresis.

3.5 Short-circuit Protection

The output currents are limited by a current regulator. Current limitation takes place when the
overcurrent limitation and shutdown threshold (IHS1-6, ILS1-6) are reached. Simultaneously, an
internal timer is started. The shorted output is disabled when during a permanent short the delay
time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-cir-
cuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set
during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to
the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled.

3.6 Inhibit
There are two ways to inhibit the T6816:
1. Set bit SI in the input register to zero
2. Switch pin 17 (INH) to 0V
In both cases, all output stages are turned off but the serial interface stays active. The output
stages can be activated again by bit SI = 1 or by pin 17 (INH) switched back to 5V.

6 T6816
4595E–BCD–09/05
 T6816

4. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins
Parameter Pin Symbol Value Unit
Supply voltage 5, 10 VVS –0.3 to +40 V
Supply voltage t < 0.5 s; IS ≥ –2 A 5, 10 VVS –1 V
Supply voltage difference ⏐ VS_pin5 – VS_pin10⏐ ∆VVS 150 mV
Supply current 5, 10 IVS 1.4 A
Supply current t < 200 ms 5, 10 IVS 2.6 A
Logic supply voltage 19 VVCC –0.3 to +7 V
Input voltage 17 VINH –0.3 to +17 V
Logic input voltage 24 to 26 VDI, VCLK, VCS –0.3 to VVCC +0.3 V
Logic output voltage 18 VDO –0.3 to VVCC +0.3 V
Input current 17, 24 to 26 IINH, IDI, ICLK, ICS –10 to +10 mA
Output current 18 IDO –10 to +10 mA
1 to 4, 11 to 16, ILS1 to ILS6 Internal limited, see
Output current
27 and 28 IHS1 to IHS6 output specification
Reverse conducting current 2, 3, 12, 13, 15,
IHS1 to IHS6 17 A
(tPulse = 150 µs) 28 towards 5, 10
Junction temperature range Tj –40 to +150 °C
Storage temperature range TSTG –55 to +150 °C

5. Thermal Resistance
All values refer to GND pins
Parameter Test Conditions Pin Symbol Min. Typ. Max. Unit
Junction pin Measured to GND 6 to 9, 20 to 23 RthJP 25 K/W
Junction ambient RthJA 65 K/W

6. Operating Range
All values refer to GND pins
Parameter Test Conditions Pin Symbol Min. Typ. Max. Unit
Supply voltage 5, 10 VVS VUV(1) 40 V
Logic supply voltage 19 VVCC 4.5 5 5.5 V
VINH, VDI, VCLK,
Logic input voltage 17, 24 to 26 –0.3 VVCC V
VCS
Serial interface clock
25 fCLK 2 MHz
frequency
Junction
Tj –40 150 °C
temperature range
Note: 1. Threshold for undervoltage detection.

7
4595E–BCD–09/05
7. Noise and Surge Immunity
Parameter Test Conditions Value
Conducted interferences ISO 7637-1 Level 4(1)
Interference Suppression VDE 0879 Part 2 Level 5
ESD (Human Body Model) MIL-STD-883D Method 3015.7 2 kV
ESD (Machine Model) EOS/ESD - S 5.2 150V
Note: 1. Test pulse 5: VSmax = 40V

8. Electrical Characteristics
7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1 Current Consumption
VVS < 28V,
1.1 Quiescent current (VS) 5, 10 IVS 40 µA A
INH or bit SI = low
Quiescent current 4.5V < VVCC < 5.5V,
1.2 19 IVCC 20 µA A
(VCC) INH or bit SI = low
VVS < 28V normal
1.3 Supply current (VS) operating, all output 5, 10 IVS 0.8 1.2 mA A
stages off
VVS < 28V normal
1.4 Supply current (VS) operating, all output 5, 10 IVS 10 mA A
stages on, no load
4.5V < VVCC < 5.5V,
1.5 Supply current (VCC) 19 IVCC 150 µA A
normal operating pin
2 Internal Oscillator Frequency
Frequency (timebase
2.1 fOSC 19 45 kHz A
for delay timers)
3 Undervoltage Detection, Power-on Reset
Power-on reset
3.1 19 VVCC 3.4 3.9 4.4 V A
threshold
Power-on reset delay
3.2 After switching on VVCC 19 tdPor 30 95 160 µs A
time
Undervoltage detection
3.3 5, 10 VUV 5.5 7.0 V A
threshold
Undervoltage detection
3.4 5, 10 ∆VUV 0.4 V A
hysteresis
Undervoltage detection
3.5 5, 10 tdUV 7 21 ms A
delay
4 Thermal Prewarning and Shutdown
4.1 Thermal prewarning 17 TjPWset 125 145 165 °C A
4.2 Thermal prewarning 17 TjPWreset 105 125 145 °C A
Thermal prewarning
4.3 ∆TjPW 20 K A
hysteresis
4.4 Thermal shutdown 17 Tj switch off 150 170 190 °C A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level

8 T6816
4595E–BCD–09/05
 T6816
8. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
4.5 Thermal shutdown 17 Tj switch on 130 150 170 °C A
Thermal shutdown
4.6 ∆Tj switch off 20 K A
hysteresis
Ratio thermal
Tj switch off/
4.7 shutdown/thermal 1.05 1.17 A
TjPW set
prewarning
Ratio thermal
Tj switch on/
4.8 shutdown/thermal 1.05 1.2 A
TjPW reset
prewarning
5 Output Specification (LS1-LS6, HS1-HS6) 7.5V < VVS < 40V
1, 4, 11,
5.1 On resistance IOut = 600 mA 14, 16, RDS OnL 1.5 Ω A
27
2, 3, 12,
5.2 On resistance IOut = –600 mA 13, 15, RDS OnH 2.0 Ω A
28
1, 4, 11,
Output clamping
5.3 ILS1-6 = 50 mA 14, 16, VLS1-6 40 60 V A
voltage
27
1, 4, 11,
VLS1–6 = 40V
5.4 Output leakage current 14, 16, ILS1-6 10 µA A
all output stages off
27
2, 3, 12,
VHS1-6 = 0V
5.5 Output leakage current 13, 15, IHS1-6 –10 µA A
all output stages off
28
1-4,
Inductive shutdown
5.7 11-16, Woutx 15 mJ D
energy
27, 28
1-4,
Output voltage edge dVLS1-6/dt
5.8 11-16, 50 200 400 mV/µs A
steepness dVHS1-6/dt
27, 28
1-4,
Overcurrent limitation
5.9 11-16, ILS1-6 650 950 1250 mA A
and shutdown threshold
27
2, 3,
Overcurrent limitation
5.10 12,13, IHS1-6 –1250 –950 –650 mA A
and shutdown threshold
15, 28
Overcurrent shutdown Input register
5.11 tdSd 1.0 1.5 2.0 ms A
delay time bit 14 (SCT) = low
1, 4,
Open load detection Input register bit 13
5.12 11,14, ILS1-6 60 200 µA A
current (OLD) = low, output off
16, 27
2, 3, 12,
Open load detection Input register bit 13
5.13 13 15, IHS1-6 –150 –30 µA A
current (OLD) = low, output off
28
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level

9
4595E–BCD–09/05
8. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
Open load detection
5.14 ILS1-6/IHS1-6 1.2 A
current ratio
1, 4,
Open load detection Input register bit 13
5.15 11,14, VLS1-6 0.6 2 V A
threshold (OLD) = low, output off
16, 27
2, 3,
Open load detection Input register bit 13 VVS –
5.16 12, 13 0.6 2 V A
threshold (OLD) = low, output off VHS1-6
15, 28
Output switch on
5.17 RLoad = 1 kΩ tdon 0.5 ms A
delay(1)
Output switch off
5.18 RLoad = 1 kΩ tdoff 1 ms A
delay(1)
6 Inhibit Input
Input voltage low level 0.3 ×
6.1 17 VIL V A
threshold VVCC
Input voltage high level 0.7 ×
6.2 17 VIH V A
threshold VVCC
Hysteresis of input
6.3 17 ∆VI 100 700 mV A
voltage
6.4 Pull-down current VINH = VVCC 17 IPD 10 80 µA A
7 Serial Interface - Logic Inputs DI, CLK, CS
Input voltage low-level 0.3 ×
7.1 24-26 VIL V A
threshold VVCC
Input voltage high-level 0.7 ×
7.2 24-26 VIH V A
threshold VVCC
Hysteresis of input
7.3 24-26 ∆VI 50 500 mV A
voltage
Pull-down current pin
7.4 VDI, VCLK = VVCC 25, 26 IPDSI 2 50 µA A
DI, CLK
7.5 Pull-up current pin CS VCS= 0V 24 IPUSI –50 –2 µA A
8 Serial Interface - Logic Output DO
8.1 Output voltage low level IOL = 3 mA 18 VDOL 0.5 V A
Output voltage high VVCC –
8.2 IOL = –2 mA 18 VDOH V A
level 0.7V
Leakage current VCS = VVCC,
8.3 18 IDO –10 10 µA A
(tri-state) 0V < VDO < VVCC
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level

10 T6816
4595E–BCD–09/05
 T6816

9. Serial Interface - Timing

Parameters Test Conditions Timing Chart No. Symbol Min. Typ. Max. Unit
DO enable after CS falling edge CDO = 100 pF 1 tENDO 200 ns
DO disable after CS rising edge CDO = 100 pF 2 tDISDO 200 ns
DO fall time CDO = 100 pF – tDOf 100 ns
DO rise time CDO = 100 pF – tDOr 100 ns
DO valid time CDO = 100 pF 10 tDOVal 200 ns
CS setup time 4 tCSSethl 225 ns
CS setup time 8 tCSSetlh 225 ns
Input register bit 14
CS high time 9 tCSh 16 ms
(SCT) = high
Input register bit 14
CS high time 9 tCSh 2 ms
(SCT) = low
CLK high time 5 tCLKh 225 ns
CLK low time 6 tCLKl 225 ns
CLK period time – tCLKp 500 ns
CLK setup time 7 tCLKSethl 225 ns
CLK setup time 3 tCLKSetlh 225 ns
DI setup time 11 tDIset 40 ns
DI hold time 12 tDIHold 40 ns

11
4595E–BCD–09/05
Figure 9-1. Serial Interface Timing with Chart Numbers

1 2

CS

DO

CS

4 7

CLK

3 6 8

DI

11

CLK

10 12

DO

Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.2 × VCC
Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC

12 T6816
4595E–BCD–09/05
 T6816
10. Application
Figure 10-1. Application Circuit

VCC

U5021M Enable
WATCHDOG
HS1 HS2 HS3 HS4 HS5 HS6
Trigger
Reset

15 13 12 3 2 28
VS
BYT41D VBatt
5 V
Fault Fault Fault Fault Fault Fault S
Detect Detect Detect Detect Detect Detect
Microcontroller

10 + 24V
VS
26
DI 6 GND

Osc
25 S O H L H L H L H L H L H L S 7 GND
CLK S C L S S S S S S S S R
S S S S
I T D 6 6 5 5 4 4 3 3 2 2 1 1 R VS
8 GND
24 Input Register Control UV -
CS protection
Output Register logic 9 GND
Thermal
17 P I S H L H L H L H L H L H L T protection
INH 20
S N C S S S S S S S S S S S S P GND
F H D 6 6 5 5 4 4 3 3 2 2 1 1
Power-on
18 Reset 21
DO GND

VCC 22
GND

Fault Fault Fault Fault Fault Fault 23

Detect Detect Detect Detect Detect Detect GND

VCC VCC
VCC
19 V
CC

VCC 5V
+
16 14 11 4 1 27
LS1 LS2 LS3 LS4 LS5 LS6

VS VS

10.1 Application Notes

It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possi-
ble to the power supply and GND pins.
Recommended value for capacitors at VS:
electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for elec-
trolytic capacitor depends on external loads, conducted interferences and reverse conducting
current IHSX (see: Absolute Maximum Ratings).
Recommended value for capacitors at VCC:
electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as
possible to GND pins.

13
4595E–BCD–09/05
11. Ordering Information
Extended Type Number Package Remarks
T6816-TIQY SO28 Power package, taped and reeled, Pb-free

12. Package Information

Package SO28 9.15
8.65
Dimensions in mm 18.05
17.80 7.5
7.3

2.35

0.4 0.25 0.25

0.10 10.50
1.27
16.51 10.20

28 15

technical drawings
according to DIN
specifications

1 14

14 T6816
4595E–BCD–09/05
 T6816
13. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No. History
• Pb-free logo on page 1 added
4595E-BCD-09/05 • Section 1 “Description” on page 1 changed
• Ordering Information on page 14 changed
• Put datasheet in a new template
4595D-BCD-05/05
• Table “Electrical Characteristics” rows 5.15 and 5.16 changed
• Put datasheet in a new template
4595C-BCD-04/04 • Table “Absolute Maximum Ratings” on page 7 changed
• Table “Electrical Characteristics” on page 10 changed

15
4595E–BCD–09/05
 Atmel Corporation Atmel Operations
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Hong Kong Tel: (33) 4-42-53-60-00
Tel: (852) 2721-9778 Fax: (33) 4-42-53-60-01
Fax: (852) 2722-1369
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1-24-8 Shinkawa Fax: 1(719) 540-1759
Chuo-ku, Tokyo 104-0033
Japan Scottish Enterprise Technology Park
Tel: (81) 3-3523-3551 Maxwell Building
Fax: (81) 3-3523-7581 East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743

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