TSC2003-Q1

www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

I2C TOUCH SCREEN CONTROLLER

1FEATURES APPLICATIONS
•
2 Qualified for Automotive Applications • Personal Digital Assistants
• 2.5-V To 5.25-V Operation • Portable Instruments
• Internal 2.5-V Reference • Point-of-Sale Terminals
• Direct Battery Measurement (0.5 V To 6 V) • Pagers
• Touch Screen Monitors
• On-Chip Temperature Measurement
• Cellular Phones
• Touch-Pressure Measurement
• I2C Interface Supports: Standard, Fast, And
High-Speed Modes
• Auto Power Down
• TSSOP-16 Package

DESCRIPTION
The TSC2003 is a 4-wire resistive touch screen controller. It also features direct measurement of two batteries,
two auxiliary analog inputs, temperature measurement, and touch-pressure measurement.
The TSC2003 has an on-chip 2.5-V reference that can be utilized for the auxiliary inputs, battery monitors, and
temperature-measurement modes. The reference can also be powered down when not used to conserve power.
The internal reference operates down to 2.7-V supply voltage while monitoring the battery voltage from 0.5 V to
6 V.
The TSC2003 is available in the small TSSOP-16 package and is specified over the –40°C to 85°C temperature
range.

VDD
PENIRQ
X+ TEMP0
X– TEMP1
SCL

VDD
SAR
2 SDA
IC
Y+
Y– Comparator Interface
and
MUX CDAC Control
Logic
A0
IN1 Internal
IN2 Clock
VBAT1 Channel Select

A1

VBAT2

VREF Internal
2.5-V REF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 85°C TSSOP – PW Reel of 2000 TSC2003IPWRQ1 T2003Q1

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

PW PACKAGE
(TOP VIEW)

VDD 1 16 IN1
X+ 2 15 IN2
Y+ 3 14 A0
X– 4 13 A1
Y– 5 12 SCL
GND 6 11 SDA
VBAT1 7 10 PENIRQ
VBAT2 8 9 VREF

TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
VDD 1 Power supply
X+ 2 I X+ position
Y+ 3 I Y+ position
X– 4 I X– position
Y– 5 I Y– position
GND 6 Ground
VBAT1 7 I Battery monitor 1
VBAT2 8 I Battery monitor 1
VREF 9 I/O Voltage reference
PENIRQ 10 O Pen interrupt. Open-drain, requires 30-kΩ to 100-kΩ external pullup resistor.
SDA 11 I/O Serial data
SCL 12 I Serial clock
A1 13 I I2C bus address A1
A0 14 I I2C bus address A0
IN2 15 I Auxiliary analog-to-digital converter input 2
IN1 16 I Auxiliary analog-to-digital converter input 1

2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

ABSOLUTE MAXIMUM RATINGS (1) (2)

over operating free-air temperature range (unless otherwise noted)
VDD Supply voltage range –0.3 V to 6 V
Digital inputs –0.3 V to VDD + 0.3 V
VI Input voltage range All analog inputs except pins 7 and 8 –0.3 V to VDD + 0.3 V
Analog input pins 7 and 8 –0.3 V to 6 V
PD Power dissipation (TJ(max) – TA)/θJA
θJA Package thermal impedance, junction to free air 115.2°C
TA Operating free-air temperature range –40°C to 85°C
TJ Maximum junction temperature 150°C
Tstg Storage temperature range –65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are referenced to GND.

ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2.7 V, VREF = 2.5-V external voltage, I2C bus frequency = 3.4 MHz, 12-bit mode,
digital inputs = GND or VDD (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Input
VI Full-scale input voltage span 0 VREF V
VI Absolute input voltage –0.2 VDD + 0.2 V
Ci Capacitance 25 pF
Ileak Leakage current 0.1 µA
System Performance
Resolution 12 bits
Standard and fast modes 11
No missing codes bits
High-speed mode 10
Standard and fast modes ±2
Integral linearity error LSB (1)
High-speed mode ±4
Offset error ±6 LSB
Gain error ±4 LSB
Vn Noise Including internal VREF, RMS 70 µV
PSRR Power-supply rejection ratio 70 dB
Sampling Dynamics
Throughput rate 50 ksps
Channel-to-channel isolation VIN = 2.5 Vpp at 50 kHz 100 dB
Switch Drivers
Y+, X+ on-resistance 5.5 Ω
Y–, X– on-resistance 7.3 Ω
Drive current (2) Duration 100 ms 50 mA

(1) LSB = least significant bit. With VREF equal to 2.5 V, one LSB is 610 µV.
(2) Specified by design. Exceeding 50-mA source current may result in device degradation.

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

TA = –40°C to 85°C, VDD = 2.7 V, VREF = 2.5-V external voltage, I2C bus frequency = 3.4 MHz, 12-bit mode,
digital inputs = GND or VDD (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference Output
Internal reference voltage 2.45 2.50 2.55 V
ppm/
Internal reference drift 25
°C
Internal reference on 300 Ω
ZO Output impedance
Internal reference off 1 GΩ
IQ Quiescent current PD1 = 1, PD0 = 0, SDA and SCL high 750 µA
Reference Input
VI Input voltage 2 VDD V
RI Resistance PD1 = PD0 = 0 1 GΩ
Battery Monitor
VI Input voltage 0.5 6 V
Sampling battery 10 kΩ
ZI Input impedance
Battery monitor off 1 GΩ
External VREF = 2.5 V –2 +2
Accuracy %
Internal reference –3 +3
Temperature Measurement
Temperature range –40 85 °C
Differential method (3) 1.6
Resolution °C
TEMP0 (4) 0.3
Differential method (3) ±2
Accuracy °C
TEMP0 (4) ±3
Digital Input/Output
High-level input voltage, all
VIH | IIH | ≤ 5 µA 0.7 × VDD VDD + 0.3 V
except PENIRQ (5)
Low-level input voltage, all except
VIL | IIL | ≤ 5 µA –0.3 0.3 × VDD V
PENIRQ (5)
High-level output voltage, all
VOH IOH = –250 µA 0.8 × VDD V
except PENIRQ
Low-level output voltage, all
VOL IOL = 250 µA 0.4 V
except PENIRQ
Low-level output voltage,
VOL 30-kΩ pullup 0.4 V
PENIRQ
Ci Input capacitance SDA, SCL 10 pF

(3) Difference between TEMP0 and TEMP1 measurement. No calibration necessary.

(4) Temperature drift is –2.1 mV/°C
(5) Specified by design

4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

ELECTRICAL CHARACTERISTICS (continued)

TA = –40°C to 85°C, VDD = 2.7 V, VREF = 2.5-V external voltage, I2C bus frequency = 3.4 MHz, 12-bit mode,
digital inputs = GND or VDD (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply Requirements
Specified performance 2.7 3.6
VDD Supply voltage
Operating range 2.5 5.25
High-speed mode
254 650
(SCL = 3.4 MHz)
Internal reference off, Fast mode
95
IQ Quiescent current PD1 = PD0 = 0 (SCL = 400 kHz) µA
Standard mode
63
(SCL = 100 kHz)
Internal reference on, PD0 = 0 1005
High-speed mode
90
(SCL = 3.4 MHz)
Internal reference off, Fast mode
Power-down current when part is 21
IPD PD1 = PD0 = 0 (SCL = 400 kHz) µA
not addressed
Standard mode
4
(SCL = 100 kHz)
PD1 = PD0 = 0, SDA = SCL = VDD 3
PD Power dissipation VDD = 2.7 V 1.8 mW
Temperature Range
TA Operating free-air temperature Specified performance –40 85 °C

TIMING CHARACTERISTICS (1) (2)

TA = –40°C to 85°C, VDD = 2.7 V (unless otherwise noted) (see Figure 1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode 0 100
kHz
Fast mode 0 400
fSCL SCL clock frequency
High-speed mode, Cb = 100 pF max 0 3.4
MHz
High-speed mode, Cb = 400 pF max 0 1.7
Bus free time between Stop and Start Standard mode 4.7
tBUF µs
conditions Fast mode 1.3
Standard mode 4 µs
tHD; STA Hold time (repeated) Start condition Fast mode 600
ns
High-speed mode 160
Standard mode 4.7
µs
Fast mode 1.3
tlow Low period of the SCL clock
High-speed mode, Cb = 100 pF max 160
ns
High-speed mode, Cb = 400 pF max 320
Standard mode 4 µs
Fast mode 600
thigh High period of the SCL clock
High-speed mode, Cb = 100 pF max 60 ns
High-speed mode, Cb = 400 pF max 120
Standard mode 4.7 µs
tSU; STA Setup time for a repeated Start condition Fast mode 600
ns
High-speed mode 160

(1) All values referred to VIHMIN and VILMAX levels.

(2) Not production tested

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

TIMING CHARACTERISTICS (continued)

TA = –40°C to 85°C, VDD = 2.7 V (unless otherwise noted) (see Figure 1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode 250
tSU; DAT Data setup time Fast mode 100 ns
High-speed mode 10
Standard mode 0 3.45
µs
Fast mode 0 0.9
tHD; DAT Data hold time
High-speed mode, Cb = 100 pF max 0 70
ns
High-speed mode, Cb = 400 pF max 0 150
Standard mode 1000
Fast mode 20 + 0.1Cb 300
trCL Rise time of SCL signal ns
High-speed mode, Cb = 100 pF max 10 80
High-speed mode, Cb = 400 pF max 20 160
Standard mode 1000
Rise time of SCL signal after a repeated Start Fast mode 20 + 0.1Cb 300
trCL1 ns
condition and after an acknowledge bit High-speed mode, Cb = 100 pF max 10 80
High-speed mode, Cb = 400 pF max 20 160
Standard mode 300
Fast mode 20 + 0.1Cb 300
tfCL Fall time of SCL signal ns
High-speed mode, Cb = 100 pF max 10 80
High-speed mode, Cb = 400 pF max 20 160
Standard mode 1000
Fast mode 20 + 0.1Cb 300
trDA Rise time of SDA signal ns
High-speed mode, Cb = 100 pF max 10 80
High-speed mode, Cb = 400 pF max 20 160
Standard mode 300
Fast mode 20 + 0.1Cb 300
tfDA Fall time of SDA signal ns
High-speed mode, Cb = 100 pF max 10 80
High-speed mode, Cb = 400 pF max 20 160
Standard mode 4 µs
tSU; STO Setup time for Stop condition Fast mode 600
ns
High-speed mode 160
Standard mode 400
Fast mode 400
Cb Capacitive load for SDA or SCL pF
High-speed mode, SCL = 1.7 MHz 400
High-speed mode, SCL = 3..4 MHz 100
Fast mode 0 50
tSP Pulse width of spike suppressed ns
High-speed mode 0 10
Standard mode
Noise margin at the high level for each
VnH Fast mode 0.2 × VDD V
connected device (including hysteresis)
High-speed mode
Standard mode
Noise margin at the low level for each
VnL Fast mode 0.1 × VDD V
connected device (including hysteresis)
High-speed mode

6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

trDA
tfDA

SDA
tBUF

tLOW
trCL tfCL tHD; STA tSP

SCL

tHD; STA
tHD; DAT tSU; DAT
tSU; STA trCL1 tSU; STO
tHIGH

Stop Start Repeated Start

Figure 1. Timing Diagram

Power-On Sequence Timing

During TSC2003 power-up, the I2C bus should be idle. In other words, the SDA and SCL lines must be high
before the TSC2003 supply (VDD) ramps up greater than 0.9 V. If the TSC2003 uses the same supply as the I2C
bus pullup resistors (VI2C), then a 1-µF capacitor placed very close to the TSC2003 supply pin causes the
TSC2003 supply to ramp up more slowly (see Figure 2). If the TSC2003 supply (VDD) is different than the supply
to the I2C bus pullup resistors (VI2C), then VI2C should be turned on before the TSC2003 supply (VDD) is powered
up.
t1 ≥ 0
100% VDD
VDD ~ 0.9 V
0V
SCL High
100% VI2C
2
SCL ~ 0.9 V I C Bus Activity
0V

100% VI2C
SDA ~ 0.9 V SDA Low I2C Bus Activity
0V

Figure 2. Power-On Sequence Timing Diagram

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs V DD
300 1200
High-Speed Mode = 3.4MHz
1100
250 1000
High-Speed Mode = 3.4MHz
900
Supply Current (µA)

Supply Current (µA)

200 800
700
150 600
Fast Mode = 400kHz Fast Mode = 400kHz
500
100 400
Standard Mode = 100kHz
300
50 200
Standard Mode = 100kHz
100
0 0
Ð40 Ð20 0 20 40 60 80 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature ( °C) VDD (V)

SUPPLY CURRENT vs I 2C BUS FREQUENCY SUPPLY CURRENT (Part Not Addressed) vs V DD

300 1000
900
High-Speed Mode = 3.4MHz
250 800

Supply Current (µA)

High-Speed Mode 700
Supply Current (µA)

200 600
500
400 Fast
150
Mode = 400kHz
300
100 200 Standard
Mode = 100kHz
100
Fast/Standard Mode
50 0
10 100 1000 10000 2.5 3.0 3.5 4.0 4.5 5.0 5.5
I2C Bus Frequency (kHz) VDD (V)

SUPPLY CURRENT (Part Not Addressed) CHANGE IN GAIN vs TEMPERATURE

vs TEMPERATURE 4.0
100
3.0
90
Gain Delta from +25ûC (LSB)

80 2.0
High-Speed Mode = 3.4MHz
Supply Current (µA)

70 1.0
60
0.0
50
Fast Mode = 400kHz Ð1.0
40
30 Ð2.0

20 Ð3.0
Standard Mode = 100kHz
10 Ð4.0
0 Ð40 Ð20 0 20 40 60 80 100
Ð40 Ð20 0 20 40 60 80 100
Temperature ( °C)
Temperature ( °C)

8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

TYPICAL CHARACTERISTICS (continued)

CHANGE IN OFFSET vs TEMPERATURE EXTERNAL REFERENCE CURRENT
6.0 vs TEMPERATURE
5.0 10
Offset Delta from +25°C (LSB)

4.0 9

External Reference Current (µA)

3.0 8
2.0 High-Speed Mode = 3.4MHz
7
1.0
0.0 6
–1.0 5
–2.0 4
–3.0 Fast Mode = 400kHz
3
–4.0 Standard Mode = 100kHz
2
–5.0
1
–6.0
–40 –20 0 20 40 60 80 100 0
Temperature ( °C) –40 –20 0 20 40 60 80 100
Temperature ( °C)

SWITCH-ON RESISTANCE vs VDD SWITCH-ON RESISTANCE vs TEMPERATURE

(X+, Y+: +V DD to Pin; X–, Y– : Pin to GND) (X+, Y+: +VDD to Pin; X –, Y –: Pin to GND)
9 9
X–
8 8
X–
7 7
Y–
6 6
Y–
RON (Ω)
RON (Ω)

5 5
Y+
4 4
X+ Y+ X+
3 3

2 2

1 1

0 0
2.5 3 3.5 4 4.5 5 5.5 –40 –20 0 20 40 60 80 100
VDD (V) Temperature ( °C)

INTERNAL V REF vs TEMPERATURE INTERNAL V REF vs V DD

2.55 2.55
2.54 2.54
2.53 2.53
2.52 2.52
Internal VREF (V)
Internal VREF (V)

2.51 2.51
2.50 2.50
2.49 2.49
2.48 2.48
2.47 2.47
2.46 2.46
2.45 2.45
2.5 3 3.5 4 4.5 5 5.5
–40
–35
–30
–25
–20
–15
–10
–05
0
05
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85

Temperature ( °C) VDD (V)

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

TYPICAL CHARACTERISTICS (continued)

TEMPERATURE DIODE VOLTAGE vs TEMPERATURE TEMP0 DIODE VOLTAGE vs VDD (25°C)
850 614
800
Temperature Diode Voltage (mV)

TEMP1

TEMP0 Diode Voltage (mV)

750 613
700

650 612
600
TEMP0
550
611
500

450
610
–40
–35
–30
–25
–20
–15
–10
–05
0
05
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature ( °C) VDD (V)
TEMP1 DIODE VOLTAGE vs V DD (25°C)
738
736
TEMP1 Diode Voltage (mV)

734
732
730

728
726
724

722
720
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

DEVICE INFORMATION

The TSC2003 is a classic Successive Approximation Register (SAR) analog-to-digital converter (ADC). The
architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The
converter is fabricated on a 0.6µ CMOS process.
The basic operation of the TSC2003 is shown in Figure 3. The device features an internal 2.5-V reference and
an internal clock. Operation is maintained from a single supply of 2.7 V to 5.25 V. The internal reference can be
overdriven with an external, low-impedance source between 2 V and VDD. The value of the reference voltage
directly sets the input range of the converter.
The analog input (X, Y, and Z parallel coordinates, auxiliary inputs, battery voltage, and chip temperature) to the
converter is provided via a multiplexer. A unique configuration of low on-resistance switches allows an
unselected ADC input channel to provide power and an accompanying pin to provide ground for an external
device. By maintaining Figure 3, a differential input to the converter, and a differential reference architecture, it is
possible to negate the switch’s on-resistance error (should this be a source of error for the particular
measurement).

Voltage +2.7V to +5V

Regulator

1.2kΩ 1.2kΩ 50kΩ

1µF TSC2003
to +
0.1µF
10µF
(Optional) 1 +VDD IN1 16 Auxiliary Input

2 X+ IN2 15 Auxiliary Input

3 Y+ A0 14

Touch 4 X– A1 13
Screen
5 Y– SCL 12 Serial Clock

6 GND SDA 11 Serial Data

7 VBAT1 PENIRQ 10 Pen Interrupt

8 VBAT2 VREF 9
1µF
+ to
0.1µF 10µF
(Optional)

Main Secondary
Battery Battery

Figure 3. Basic Operation of the TSC2003

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

Analog Input
See Figure 4 for a block diagram of the input multiplexer on the TSC2003, the differential input of the ADC, and
the converter's differential reference.
When the converter enters the Hold mode, the voltage difference between the +IN and –IN inputs (see Figure 4)
is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion
rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically
25 pF). After the capacitor has been fully charged, there is no further input current. The amount of charge
transfer from the analog source to the converter is a function of conversion rate.
PENIRQ +VDD VREF

TEMP1 TEMP0

C2-C0 C3
(Shown 101B) (Shown HIGH)

X+

X–
Ref ON/OFF

Y+ +REF
+IN
Y–
Converter
–IN
2.5-V –REF
Reference

7.5kΩ
VBAT1
7.5kΩ
VBAT2
2.5kΩ 2.5kΩ

Battery Battery
On On
IN1
IN2
GND

Figure 4. Simplified Diagram of the Analog Input

12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

Internal Reference
The TSC2003 has an internal 2.5-V voltage reference that can be turned on or off with the power-down control
bits, PD0 and PD1 (see Table 2 and Figure 5). The internal reference is powered down when power is first
applied to the device.
The internal reference voltage is only used in the single-ended reference mode for battery monitoring,
temperature measurement, and for measuring the auxiliary input. Optimal touch screen performance is achieved
when using a ratiometric conversion; thus, all touch screen measurements are done automatically in the
differential mode.
Reference
Power Down

VREF
Band
Gap Buffer

Optional
To
CDAC

Figure 5. Simplified Diagram of the Internal Reference

Reference Input
The voltage difference between +REF and –REF (see Figure 4) sets the analog input range. The TSC2003
operates with a reference in the range of 2 V to VDD. There are several critical items concerning the reference
input and its wide-voltage range. As the reference voltage is reduced, the analog voltage weight of each digital
output code is also reduced. This is often referred to as the LSB (least significant bit) size, and is equal to the
reference voltage divided by 4096 (256 if in 8-bit mode). Any offset or gain error inherent in the ADC appears to
increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given
converter is 2 LSBs with a 2.5-V reference, it is typically 2.5 LSBs with a 2-V reference. In each case, the actual
offset of the device is the same, 1.22 mV. With a lower reference voltage, more care must be taken to provide a
clean layout including adequate bypassing, a clean (low noise, low ripple) power supply, a low-noise reference (if
an external reference is used), and a low-noise input signal.
The voltage into the VREF input is not buffered, and directly drives the capacitor digital-to-analog converter
(CDAC) portion of the TSC2003. Therefore, the input current is very low, typically < 6 µA.

Reference Mode
There is a critical item regarding the reference when making measurements while the switch drivers are on. For
this discussion, it is useful to consider the basic operation of the TSC2003 (see Figure 3). This particular
application shows the device being used to digitize a resistive touch screen. A measurement of the current Y
position of the pointing device is made by connecting the X+ input to the ADC, turning on the Y+ and Y– drivers,
and digitizing the voltage on X+, as shown in Figure 6. For this measurement, the resistance in the X+ lead does
not affect the conversion; it does, however, affect the settling time, but the resistance is usually small enough
that this is not a concern. However, because the resistance between Y+ and Y– is fairly low, the on-resistance of
the Y drivers does make a small difference. Under the situation outlined so far, it would not be possible to
achieve a 0-V input or a full-scale input regardless of where the pointing device is on the touch screen because
some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the
resistance of the touch screen, providing an additional source of error.

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

+VDD VREF

Y+

+REF
+IN
X+
Converter
–IN
–REF

Y–

GND

Figure 6. Simplified Diagram of Single-Ended Reference

This situation is remedied, as shown in Figure 7, by using the differential mode: the +REF and –REF inputs are
connected directly to Y+ and Y–, respectively. This makes the ADC ratiometric. The result of the conversion is
always a percentage of the external reference, regardless of how it changes in relation to the on-resistance of
the internal switches.
+VDD

Y+

+REF
+IN
X+
Converter
–IN
–REF

Y–

GND

Figure 7. Simplified Diagram of Differential Reference (Y Switches Enabled, X+ is Analog Input)

Differential reference mode always uses the supply voltage, through the drivers, as the reference voltage for the
ADC. VREF cannot be used as the reference voltage in differential mode.
It is possible to use a high-precision reference on VREF in single-ended reference mode for measurements which
do not need to be ratiometric (i.e., battery voltage, temperature measurement, etc.). In some cases, it could be
possible to power the converter directly from a precision reference. Most references can provide enough power
for the TSC2003, but they might not be able to supply enough current for the external load, such as a resistive
touch screen.

14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

Touch Screen Settling

In some applications, external capacitors may be required across the touch screen for filtering noise picked up by
the touch screen (i.e., noise generated by the LCD panel or backlight circuitry). These capacitors provide a
low-pass filter to reduce the noise, but they also cause a settling time requirement when the panel is touched.
The settling time typically shows as a gain error. The problem is that the input and/or reference has not settled to
its final steady-state value prior to the ADC sampling the input(s) and providing the digital output. Additionally, the
reference voltage may still be changing during the measurement cycle.
To resolve these settling time problems, the TSC2003 can be commanded to turn on the drivers only without
performing a conversion (see Table 1). Time can then be allowed before the command is issued to perform a
conversion. Generally, the time it takes to communicate the conversion command over the I2C bus is adequate
for the touch screen to settle.

Temperature Measurement
In some applications, such as battery recharging, a measurement of ambient temperature is required. The
temperature measurement technique used in the TSC2003 relies on the characteristics of a semiconductor
junction operating at a fixed current level to provide a measurement of the temperature of the TSC2003 chip. The
forward diode voltage (VBE) has a well-defined characteristic versus temperature. The temperature can be
predicted in applications by knowing the 25°C value of the VBE voltage and then monitoring the delta of that
voltage as the temperature changes. The TSC2003 offers two modes of temperature measurement.
The first mode requires calibrations at a known temperature, but only requires a single reading to predict the
ambient temperature. A diode is used during this measurement cycle. The voltage across the diode is connected
through the MUX for digitizing the diode forward bias voltage by the ADC with an address of C3 = 0, C2 = 0, C1
= 0, and C0 = 0 (see Table 1 and Figure 8 for details). This voltage is typically 600 mV at 25°C, with a 20-µA
current through it. The absolute value of this diode voltage can vary a few millivolts; the temperature coefficient
(TC) of this voltage is very consistent at –2.1 mV/°C. During the final test of the end product, the diode voltage
would be stored at a known room temperature, in memory, for calibration purposes by the user. The result is an
equivalent temperature measurement resolution of 0.3°C/LSB.

X+

MUX A/D
Converter

Temperature Select
TEMP0 TEMP1

Figure 8. Temperature Measurement Mode Functional Block Diagram

The second mode does not require a test temperature calibration, but instead uses a two-measurement method
to eliminate the need for absolute temperature calibration and for achieving 2°C/LSB accuracy. This mode
requires a second conversion with an address of C3 = 0, C2 = 1, C1 = 0, and C0 = 0, with a 91 times larger
current. The voltage difference between the first and second conversion using 91 times the bias current is
represented by kT/q × 1n (N), where N is the current ratio (91), k is Boltzmann's constant (1.38054 × 10–23
electron-volts/degree Kelvin), q is the electron charge (1.602189 × 10–19 C), and T is the temperature in degrees
Kelvin. This mode can provide improved absolute temperature measurement over the first mode, but at the cost
of less resolution (1.6°C/LSB).

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

The equation to solve for °K is shown in Equation 1:

q • ∆V
°K =
k • 1n(N) (1)
Where:
ΔV V(I91) – V(I1) (in mV)
∴ °K 2.573 × ΔV°K/mV
°C = 2.573 × ΔV(mV) – 273°K

NOTE:
The bias current for each diode temperature measurement is only turned on during
the acquisition mode, and, therefore, does not add any noticeable increase in power,
especially if the temperature measurement only occurs occasionally.

Battery Measurement
An added feature of the TSC2003 is the ability to monitor the battery voltage on the other side of the voltage
regulator (dc/dc converter), as shown in Figure 9. The battery voltage can vary from 0.5 V to 6 V, while the
voltage regulator maintains the voltage to the TSC2003 at 2.7 V, 3.3 V, etc. The input voltage (VBAT1 or VBAT2) is
divided down by 4 so that a 6-V battery voltage is represented as 1.5 V to the ADC. The simplifies the
multiplexer and control logic. To minimize the power consumption, the divider is only on during the sample period
which occurs after control bits C3 = 0, C2 = 0, C1 = 0, and C0 = 1 (VBAT1) or C3 = 0, C2 = 1, C1 = 0, and C0 = 1
(VBAT2) are received. See Table 1 and Table 2 for the relationship between the control bits and configuration of
the TSC2003.

DC/DC 2.7V
Converter
Battery
0.5V +
to
6.0V VDD

0.125V to 1.5V
VBAT A/D
Converter
7.5kΩ

2.5kΩ

Figure 9. Battery Measurement Functional Block Diagram

16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

Pressure Measurement
Measuring touch pressure can also be done with the TSC2003. To determine pen or finger touch, the pressure of
the "touch" needs to be determined. Generally, it is not necessary to have high accuracy for this test, therefore,
the 8-bit resolution mode is recommended. However, calculations are shown with the 12-bit resolution mode.
There are several different ways of performing this measurement, and the TSC2003 supports two methods.
The first method requires knowing the X-Plate resistance, measurement of the X-Position, and two additional
cross-panel measurements (Z2 and Z1) of the touch screen, as shown in Figure 10. Use Equation 2 to calculate
the touch resistance:
X-Position Z2
RTOUCH = RX-Plate • –1
4096 Z1 (2)
The second method requires knowing both the X-Plate and Y-Plate resistance, measurement of X-Position and
Y-Position, and Z1. Equation 3 calculates the touch resistance using the second method:
R X −Plate • X-Position 4096 Y-Position
R TOUCH = –1 – R Y −Plate • 1–
4096 Z1 4096
(3)
Measure X-Position
X+ Y+

Touch

X-Position

X– Y–

Measure Z1-Position
X+ Y+

Touch

Z1-Position

X– Y–

X+ Y+

Touch

Z2-Position

X– Y–
Measure Z2-Position

Figure 10. Pressure Measurement Block Diagrams

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

Digital Interface
The TSC2003 supports the I2C serial bus and data transmission protocol in all three defined modes: standard,
fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving
data as a receiver. The device that controls the message is called a master. The devices that are controlled by
the master are slaves. The bus must be controlled by a master device which generates the serial clock (SCL),
controls the bus access, and generates the Start and Stop conditions. The TSC2003 operates as a slave on the
I2C bus. Connections to the bus are made via the open-drain I/O lines SDA and SDL.
The following bus protocol has been defined, as shown in Figure 11:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as control signals.

SDA

Slave Address R/W

Acknowledgement
Direction
Signal from
Bit
Receiver

Acknowledgement
Signal from
Receiver

SCL 1 2 6 7 8 9 1 2 3-7 8 9
ACK ACK
Start Stop Condition
Condition Repeated If More Bytes Are Transferred or Repeated
Start Condition

Figure 11. I2C Bus Protocol

Accordingly, the following bus conditions have been defined:

Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data line, from high to low, while the clock is high defines a
Start condition.
Stop Data Transfer: A change in the state of the data line, from low to high, while the clock line is high defines a
Stop condition.
Data Valid: The state of the data line represents valid data when, after a Start condition, the data line is stable
for the duration of the high period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is not limited, and is determined by the master device. The
information is transferred byte-wise, and each receiver acknowledges with a ninth-bit.
Within the I2C bus specifications, a standard mode (100-kHz clock rate), a fast mode (400-kHz clock rate), and a
high-speed mode (3.4-MHz clock rate) are defined. The TSC2003 works in all three modes.
Acknowledge: Each receiving device, when accessed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse, which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that
the SDA line is stable low during the high period of the acknowledge clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the
data line high to enable the master to generate the Stop condition.

18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

Figure 11 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two
types of data transfer are possible:
• Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave
address and each received byte.
• Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by
the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the
slave to the master. The master returns an acknowledge bit after all received bytes other than the last one. At
the end of the last received byte, a ‘not acknowledge’ is returned.
The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended
with a Stop condition or a repeated Start condition. Because a repeated Start condition is also the beginning of
the next serial transfer, the bus is not released.
The TSC2003 may operate in the following two modes:
• Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is received,
an acknowledge bit is transmitted. Start and Stop conditions are recognized as the beginning and end of a
serial transfer. Address recognition is performed by hardware after reception of the slave address and
direction bit.
• Slave transmitter mode: The first byte (the slave address) is received and handled as in the slave receiver
mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is
transmitted on SDA by the TSC2003 while the serial clock is input on SCL. Start and Stop conditions are
recognized as the beginning and end of a serial transfer.

Address Byte
The address byte, as shown in Figure 12, is the first byte received following the Start condition from the master
device. The first five bits (MSBs) of the slave address are factory preset to 10010. The next two bits of the
address byte are the device select bits: A1 and A0. Input pins (A1 and A0) on the TSC2003 determine these two
bits of the device address for a particular TSC2003. Therefore, a maximum of four devices with the same preset
code can be connected on the same bus at one time.
MSB LSB
1 0 0 1 0 A1 A0 R/W

Figure 12. Address Byte

The A1–A0 address inputs can be connected to VDD or digital ground. The last bit of the address byte (R/W)
defines the operation to be performed. When set to a "1", a read operation is selected; when set to a "0", a write
operation is selected. Following the Start condition, the TSC2003 monitors the SDA bus and checks the device
type identifier being transmitted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W
bit, the slave device outputs an acknowledge signal on the SDA line.

Command Byte
The TSC2003 operating mode is determined by a command byte, which is shown in Figure 13.
MSB LSB
C3 C2 C1 C0 PD1 PD0 M X

Figure 13. Command Byte

The bits in the device command byte are defined as follows:

• C3–C0: Configuration bits. These bits set the input multiplexer address and functions that the TSC2003 will
perform, as shown in Table 1.
• PD1–PD0: Power-down bits. These two bits select the power-down mode that the TSC2003 will enter after
the current command completes, as shown in Table 2.

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

Table 1. Possible Input Configurations

REFERENCE
C3 C2 C1 C0 FUNCTION INPUT TO ADC X DRIVERS Y DRIVERS
MODE
0 0 0 0 Measure TEMP0 TEMP0 Off Off Single ended
0 0 0 1 Measure VBAT1 VBAT1 Off Off Single ended
0 0 1 0 Measure IN1 IN1 Off Off Single ended
0 0 1 1 Reserved — — — Single ended
0 1 0 0 Measure TEMP1 TEMP1 Off Off Single ended
0 1 0 1 Measure VBAT2 VBAT2 Off Off Single ended
0 1 1 0 Measure IN2 IN2 Off Off Single ended
0 1 1 1 Reserved — — — Single ended
1 0 0 0 Activate X– Drivers — On Off Differential
1 0 0 1 Activate Y– Drivers — Off On Differential
1 0 1 0 Activate Y+, X– Drivers — X– On Y+ On Differential
1 0 1 1 Reserved — — — Differential
1 1 0 0 Measure X Position Y+ On Off Differential
1 1 0 1 Measure Y Position X+ Off On Differential
1 1 1 0 Measure Z1 Position X+ X– On Y+ On Differential
1 1 1 1 Measure Z2 Position Y– X– On Y+ On Differential

Table 2. Power-Down Bit Functions

PD1 PD0 PENIRQ DESCRIPTION
0 0 Enabled Power-down between conversions
0 1 Disabled Internal reference off, ADC on
1 0 Enabled Internal reference on, ADC off
1 1 Disabled Internal reference on, ADC on

The internal reference voltage can be turned on or off independently of the ADC. This can allow extra time for
the internal reference voltage to settle to its final value prior to making a conversion. Allow this extra wakeup time
if the internal reference was powered down. Also note that the status of the internal reference power down is
latched into the part (internally) when a Stop or repeated Start occurs at the end of a command byte (see
Figure 14 and Figure 16). Therefore, to turn off the internal reference, an additional write to the TSC2003 with
PD1 = 0, is required after the channel has been converted.
It is recommended to set PD0 = 0 in each command byte to get the lowest power consumption possible. If
multiple X-, Y-, and Z-position measurements are done one right after another, such as when averaging, PD0 = 1
leaves the touch screen drivers on at the end of each conversion cycle.
• M: Mode bit. If M is 0, the TSC2003 is in 12-bit mode. If M is 1, 8-bit mode is selected.
• X: Don’t care
When the TSC2003 powers up, the power-down mode bits need to be written to ensure that the part is placed
into the desired mode to achieve lowest power. Therefore, immediately after power-up, a command byte should
be sent which sets PD1 = PD0 = 0, so that the device is in the lowest power mode, powering down between
conversions.

Start Conversion/Write Cycle

A conversion/write cycle begins when the master issues the address byte containing the slave address of the
TSC2003, with the eighth bit equal to a 0 (R/W = 0), as shown in Figure 12. Once the eighth bit has been
received, and the address matches the A1–A0 address input pin setting, the TSC2003 issues an acknowledge.
Once the master receives the acknowledge bit from the TSC2003, the master writes the command byte to the
slave (see Figure 13). After the command byte is received by the slave, the slave issues another acknowledge
bit. The master then ends the write cycle by issuing a repeated Start or a Stop condition, as shown in Figure 14.

20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

If the master sends additional command bytes after the initial byte, before sending a Stop or repeated Start
condition, the TSC2003 does not acknowledge those bytes.
The input multiplexer for the ADC has its channel selected when bits C3 through C0 are clocked in. If the
selected channel is an X-,Y-, or Z-position measurement, the appropriate drivers turn on once the acquisition
period begins.
When R/W = 0, the input sample acquisition period starts on the falling edge of SCL once the C0 bit of the
command byte has been latched, and ends when a Stop or repeated Start condition has been issued. A/D
conversion starts immediately after the acquisition period. The multiplexer inputs to the ADC are disabled once
the conversion period starts. However, if an X-, Y-, or Z-position is being measured, the respective touch screen
drivers remain on during the conversion period. A complete write cycle is shown in Figure 14.

SCL

Address Byte Command Byte

R/W
SDA 1 0 0 1 0 A1 A0 0 0 C3 C2 C1 C0 PD1 PD0 M X 0

TSC2003 TSC2003
ACK ACK

Start Acquisition Conversion

Stop or
Repeated Start

Figure 14. Complete I2C Serial Write Transmission

Read a Conversion/Read Cycle

For best performance, the I2C bus should remain in an idle state while an A/D conversion is taking place. This
prevents digital clock noise from affecting the bit decisions being made by the TSC2003. The master should wait
for at least 10 µs before attempting to read data from the TSC2003 to realize this best performance. However,
the master does not need to wait for a completed conversion before beginning a read from the slave, if full 12-bit
performance is not necessary.
Data access begins with the master issuing a Start condition followed by the address byte (see Figure 12) with
R/W = 1. Once the eighth bit has been received, and the address matches, the slave issues an acknowledge.
The first byte of serial data follows (D11 to D4, MSB first).
After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge.
The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3-D0,
followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to
indicate that the last data byte has been received. If the master acknowledges the second data byte, then the
data repeats on subsequent reads with ACKs between bytes. This is true in both 12-bit and 8-bit mode. The
master then issues a Stop condition, which ends the read cycle, as shown in Figure 15.

SCL

Address Byte Date Byte 1 Date Byte 2

SDA 1 0 0 1 0 A1 A0 R/W 0 D11 D10 D9 D8 D7 D6 D5 D4 0 D3 D2 D1 D0 0 0 0 0 1

1

TSC2003 Master Master

Start ACK ACK NACK
Stop or
Repeated Start

Figure 15. Complete I2C Serial Read Transmission

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

I2C High-Speed Operation

The TSC2003 can operate with high-speed I2C masters. To do so, the simple resistor pullup on SCL must be
changed to the active pullup, as recommended in the I2C specification.
The I2C bus operates in standard or fast mode initially. Following a Start condition, the master sends the code
00001xxx, which the slave does not acknowledge. The bus now operates in high-speed mode and remains in
high-speed mode until a Stop condition occurs. Therefore, to maximize throughput, only repeated Starts should
be used to separate transactions.
Because the TSC2003 may not have completed a conversion before a read to the part can be requested, the
TSC2003 is capable of stretching the clock until the converted data is stored in its internal shift register. Once the
data is latched, the TSC2003 releases the clock line so that the master can receive the converted data. A
complete high-speed conversion cycle is shown in Figure 16.
F/S Mode HS-Mode Enabled
S 0 0 0 0 1 X X X N

A/D Converter Power-Down Mode A/D Converter Powers Up and Begins Sampling
Sr 1 0 0 1 0 A1 A0 W A C3 C2 C1 C0 PD1 PD0 M X A

Fixed Address Part Programmable

A/D Converter Stops Sampling and Begins Conversion Using Internal Clock

Sr 1 0 0 1 0 A1 A0 R A SCLH is stretched LOW until A/D Converter is finished converting data.

A/D Converter Goes Into Power-Down Mode After Finishing Conversion (If PD0 = 0) Exit HS-Mode and Enter F/S Mode

D11 D10 D9 D8 D7 D6 D5 D4 A D3 D2 D1 D0 0 0 0 0 N P

16 Bits + Ack

S = Start = Master Controls Bus

Sr = Repeated Start
P = Stop
= Slave Controls Bus

Figure 16. High-Speed I2C Mode Conversion Cycle

Data Format
The TSC2003 output data is in straight binary format, as shown in Figure 17. This shows the ideal output code
for the given input voltage, and does not include the effects of offset, gain, or noise.
FS = Full-Scale Voltage = V REF(1)
1LSB = V REF(1)/4096

1LSB
11...111

11...110

11...101
Output Code

00...010

00...001

00...000

0V FS – 1LSB
Input Voltage (2) (V)

NOTES: (1) Reference voltage at converter: +REF – (–REF). See Figure 2.

(2) Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 2

Figure 17. Ideal Input Voltages and Output Codes

22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 TSC2003-Q1
www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

8-Bit Conversion
The TSC2003 provides an 8-bit conversion mode (M = 1) that can be used when faster throughput is needed,
and the digital result is not as critical (for example, measuring pressure). By switching to the 8-bit mode, a
conversion result can be read by transferring only one data byte.
This shortens each conversion by four bits and reduces data transfer time which results in fewer clock cycles and
provides lower power consumption.

Layout
The following layout suggestions should provide optimum performance from the TSC2003. However, many
portable applications have conflicting requirements concerning power, cost, size, and weight. In general, most
portable devices have fairly "clean" power and grounds because most of the internal components are very low
power. This situation would mean less bypassing for the converter's power, and less concern regarding
grounding. Still, each situation is unique, and the following suggestions should be reviewed carefully.
For optimum performance, care should be taken with the physical layout of the TSC2003 circuitry. The basic
SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections,
and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any
single conversion for an n-bit SAR converter, there are n "windows" in which large external transient voltages can
easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital
logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout,
and the exact timing of the external event. The error can change if the external event changes in time with
respect to the SCL input.
With this in mind, power to the TSC2003 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor
should be placed as close to the device as possible. In addition, a 1-µF to 10-µF capacitor may also be needed if
the impedance of the connection between VDD and the power supply is high.
A bypass capacitor is generally not needed on the VREF pin because the internal reference is buffered by an
internal op amp. If an external reference voltage originates from an operational amplifier, ensure that it can drive
any bypass capacitor that is used without oscillation.
The TSC2003 architecture offers no inherent rejection of noise or voltage variation in regards to using an
external reference input. This is of particular concern when the reference input is tied to the power supply. Any
noise and ripple from the supply appears directly in the digital results. While high-frequency noise can be filtered
out, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point. In many cases, this is the "analog" ground. Avoid
connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run
a ground trace directly from the converter to the power-supply entry point. The ideal layout includes an analog
ground plane dedicated to the converter and associated analog circuitry.
In the specific case of use with a resistive touch screen, care should be taken with the connection between the
converter and the touch screen. Because resistive touch screens have fairly low resistance, the interconnection
should be as short and robust as possible. Longer connections can be a source of error, much like the
on-resistance of the internal switches. Likewise, loose connections can be a source of error when the contact
resistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of error in touch screen applications (e.g., applications that
require a backlit LCD panel). This EMI noise can be coupled through the LCD panel to the touch screen and
cause "flickering" of the converted data. Several things can be done to reduce this error, such as utilizing a touch
screen with a bottom-side metal layer connected to ground. This couples the majority of noise to ground.
Additionally, filtering capacitors from Y+, Y–, X+, and X– to ground can also help.

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Link(s): TSC2003-Q1
TSC2003-Q1
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

PENIRQ Output
The pen-interrupt output function is shown in Figure 18. By connecting a pullup resistor to VDD (typically 100 kΩ),
the PENIRQ output is high. While in the power-down mode, with PD0 = 0, the Y– driver is on and connected to
GND, and the PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to
ground through the touch screen, and PENIRQ output goes low due to the current path through the panel to
GND, initiating an interrupt to the processor. During the measurement cycle for X, Y, and Z positions, the X+
input is disconnected from the PENIRQ pulldown transistor to eliminate any leakage current from the pullup
resistor to flow through the touch screen, thus causing no errors.
VDD

30kΩ to 100kΩ

VDD
PENIRQ

VDD
10kΩ
TEMP0 TEMP1

Y+
HIGH except
when TEMP0,
TEMP1 activated TEMP
DIODE

X+

Y–
ON

Y+ or X+ drivers on,
or TEMP0, TEMP1
measurements activated

Figure 18. PENIRQ Functional Block Diagram

In addition to the measurement cycles for X-, Y-, and Z-position, commands which activate the X-drivers,
Y-drivers, Y+ and X-drivers without performing a measurement also disconnect the X+ input from the PENIRQ
pulldown transistor and disable the pen-interrupt output function regardless of the value of the PD0 bit. Under
these conditions, the PENIRQ output is forced low. Furthermore, if the last command byte written to the
TSC2003 contains PD0 = 1, the pen-interrupt output function is disabled and is not able to detect when the panel
is touched. To re-enable the pen-interrupt output function under these circumstances, a command byte needs to
be written to the TSC2003 with PD0 = 0.
Once the bus master sends the address byte with R/W = 0 (see Figure 12) and the TSC2003 sends an
acknowledge, the pen-interrupt function is disabled. If the command that follows the address byte has PD0 = 0,
then the pen-interrupt function is enabled at the end of a conversion. This is approximately 10 µs (12-bit mode)
or 7 µs (8-bit mode) after the TSC2003 receives a Stop/Start condition following the reception of a command
byte (see Figure 14 and Figure 16 for further details of when the conversion cycle begins).
In both cases listed above, it is recommended that the master processor mask the interrupt which the PENIRQ is
associated with whenever the host writes to the TSC2003. This prevents false triggering of interrupts when the
PENIRQ line is disabled in the cases listed above.

24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2003-Q1

 PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)

TSC2003IPWRQ1 ACTIVE TSSOP PW 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T2003Q1
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TSC2003-Q1 :

• Catalog: TSC2003

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TSC2003IPWRQ1 TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TSC2003IPWRQ1 TSSOP PW 16 2500 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated