Data transfer between the computer and external device takes place through I/O mechanism.

One
communicates with a computer system via the I/O devices interfaced to it. The user can enter
programs and data using the keyboard on a terminal, executes the programs to obtain results and
finally the results may be displayed on monitor of the computer. Therefore, the I/O devices connected
to a computer system provide an efficient means of communication between the computer and the
outside world. These I/O devices are commonly known as peripherals and popular I/O devices used
are keyboard, monitor, printer, disk and mouse.

I/O INTERFACE AND I/O DRIVER

Every computer supports a variety of peripheral devices. To use a peripheral device, two modules are
required:
(a) I/O interface or I/O controller.
(b) I/O driver.
1. I/O Interface or I/O Controller
I/O interface is a hardware device provides a means for transferring information between central
system (i.e. CPU and main memory) and external I/O peripheral device. Peripheral devices connected
to a computer need I/O interface circuits for interfacing them with the CPU and or memory. Each
peripheral has its own I/O controller that operates the particular device. The purpose of the I/O
interface is to resolve the differences that exist between the central computer and each peripheral. The
major differences are:
Peripherals are mainly electromechanical and electromagnetic devices and their manner of
operations is different from the operation of the CPU and main memory, which are electronic
devices. Hence, a conversion of signal values may be required.
• l Data codes and formats in peripheral devices are different from the code format in the CPU
and memory.
• l The data transfer rate of the peripheral devices is usually slower than the transfer rate of the
CPU and therefore, a synchronization mechanism may be required.
• l The various peripheral devices attached to a computer have different modes of operations
and
each must be controlled so as not to disturb the operation of other peripherals connected to the
CPU.
• In order to resolve these differences, computer systems must include special hardware device
called I/O interface with each peripheral to supervise and synchronize all I/O transfers.

The linkage of the I/O interface to the central computer is via the bus. A typical communication
linkage between the central computer (i.e. CPU and main memory) and several peripheral devices is
shown in Fig. 7.1. The I/O bus consists of data lines, address lines and control lines. The magnetic
disk, printer, monitor and keyboard are used in practically any general-purpose computer. Each
peripheral device has associated with it an I/O interface unit. A device’s interface circuit constitutes
of an address decoder, the data and status registers, and the control circuitry. Each I/O interface unit
decodes the address and control signal received from the I/O bus, interprets them for the peripheral
and provides signals for the peripheral. It synchronizes the data flow and supervises the transfer
between peripheral and processor. For example, the printer controller controls the paper motion, the
printing timing and the selection of printing characters. An I/O controller may be incorporated
separately or may be physically integrated with the peripheral.
The I/O bus from the central computer is attached to all peripheral controllers. To communicate
with a particular I/O device, the processor places a device address on the address lines. The address
decoder of I/O interface monitors the address lines. When a particular I/O interface detects its own
address, it activates the path between the bus lines and the peripheral device that it controls. All
peripherals whose addresses do not correspond to the address in the bus are disabled by their
interfaces.

When the address is made available in the address lines, at that time the processor provides an
operation code in the control lines. The interface selected responds to the operation code and proceeds
to execute it. The operation code is referred to as an I/O command. The meaning of the
command depends on the peripheral type that the processor is addressing. There are four types of I/O
commands that an I/O interface may receive when it is addressed by a processor:

1. Control It is used to enable an I/O device and to give directive what to do. For example, a
magnetic tape unit may be instructed to rewind or to move forward one record. These commands are
tailored to the particular type of peripheral device.
2. Test It is used to test various status conditions associated with an I/O interface and its peripheral.
For example, the processor may want to know that the peripheral of interest is powered on and ready
for use. It also may want to know if the most recent I/O operation is completed and if any error
occurs.
3. Read This causes the I/O interface to obtain a data-item from the peripheral and place it in an
internal buffer (data register). The processor can then obtain the data item by requesting that the I/O
interface place it on the data bus.
4. Write This causes the I/O interface to take a data-item from the data bus and subsequently
transfer that data item to the peripheral.
I/O Driver
I/O driver is a software module that issues different commands to the I/O controller, for executing
various I/O operations. Following are certain operations performed by different I/O drivers:
• l Reading a file from a disk.
• l Printing some lines by the printer.
• l Displaying a message on monitor.
• l Storing some data on disk.
The I/O driver program for a given peripheral device is developed only after knowing the architecture
of the I/O controller device. The I/O driver program and I/O controller device together achieve
the I/O operation done on behave of corresponding peripheral device. An I/O operation can be
performed by calling the relevant I/O interface (or I/O controller) and passing relevant signals for
operation. After completing the I/O operation, the I/O driver returns control to the called program and
passes return signals about the completion of the operation. Figure 7.2 illustrates communication
between the I/O controller and the application program. The collection of I/O driver programs is
called BIOS (Basic Input Output Control System).

The I/O drivers for the basic peripheral devices supported by the general PC are part of the BIOS
which is physically stored in ROM part of main memory. The I/O drivers for other peripherals are
provided on the floppy diskette or CD. This program is installed in the hard disk and brought into the
RAM by bootstrap system program during booting.

Synchronous Data Transfer

In Synchronous data transfer, the sending and receiving units are enabled with same
clock signal. It is possible between two units when each of them knows the behavior of the
other. The master performs a sequence of instructions for data transfer in a predefined
order. All these actions are synchronized with the common clock. The master is designed to
supply the data at a time when the slave is definitely ready for it. Usually, the master will
introduce sufficient delay to take into account the slow response of the slave, without any
request from the slave.
The master does not expect any acknowledgment signal from the slave when data is sent by
the master to the slave. Similarly, when data from the slave is read by the master, neither
the slave informs that the data has been placed on the data bus nor the master acknowledges
that the data has been read. Both the master and slave perform their own task of transferring
data at a designed clock period. Since both devices know the behavior (response time) of
each other, no difficulty arises.
Prior to transferring data, the master must logically select the slave either by sending
slave’s address or sending “device select” signal to the slave. But there is
no acknowledgment signal from the slave to the master if the device is selected.
Timing diagram of the synchronous read operation is given below:
In this timing diagram, the master first places slave’s address in the address bus and read
signal in the control line at the falling edge of the clock. The entire read operation is over in
one clock period.
Advantages –
1. The design procedure is easy. The master does not wait for any acknowledges
signal from the slave, though the master waits for a time equal to slave’s
response time.
2. The slave does not generate an acknowledge signal, though it obeys the timing
rules as per the protocol set by the master or system designer.

Disadvantages –
1. If a slow speed unit connected to a common bus, it can degrade the overall rate
of transfer in the system.
2. If the slave operates at a slow speed, the master will be idle for some time during
data transfer and vice versa.
Asynchronous data transfer
Asynchronous input output is a form of input output processing that allows others devices
to do processing before the transmission or data transfer is done. Problem faced in
asynchronous input output synchronization – It is not sure that the data on the data bus
is fresh or not as their no time slot for sending or receiving data. This problem is solved by
following mechanism:
1. Strobe
2. Handshaking
Data is transferred from source to destination through data bus in between. 1. Strobe
Mechanism:
1. Source initiated Strobe – When source initiates the process of data transfer.
Strobe is just a
signal.
 (i) First, source puts data on the data bus and ON the strobe signal. (ii)
Destination on seeing the ON signal of strobe, read data from the data bus. (iii)
After reading data from the data bus by destination, strobe gets OFF. Signals can
be seen
as:

It shows that first data is put on the data bus and then strobe signal gets active.
2. Destination initiated signal – When destination initiates the process of data
transfer.

(i) First, the destination ON the strobe signal to ensure the source to put the
fresh data on the data bus. (ii) Source on seeing the ON signal puts fresh data on
the data bus. (iii) Destination reads the data from the data bus and strobe gets
OFF signal. Signals can be seen
as:
 It shows that first strobe signal gets active then data is put on the data bus.
Problems faced in Strobe based asynchronous input output –
1. In Source initiated Strobe, it is assumed that destination has read the data from
the data bus but there is no surety.
2. In Destination initiated Strobe, it is assumed that source has put the data on the
data bus but there is no surety.
This problem is overcome by Handshaking. 2. Handshaking Mechanism:
1. Source initiated Handshaking – When source initiates the data transfer
process. It consists of signals: DATA VALID: if ON tells data on the data bus is
valid otherwise invalid. DATA ACCEPTED: if ON tells data is accepted
otherwise not
accepted.

(i) Source places data on the data bus and enable Data valid signal. (ii)
Destination accepts data from the data bus and enable Data accepted signal. (iii)
After this, disable Data valid signal means data on data bus is invalid now. (iv)
Disable Data accepted signal and the process ends. Now there is surety that
destination has read the data from the data bus through data accepted signal.
Signals can be seen
as:
 It shows that first data is put on the data bus then data valid signal gets active
and then data accepted signal gets active. After accepting the data, first data
valid signal gets off then data accepted signal gets off.
2. Destination initiated Handshaking – When destination initiates the process of
data transfer. REQUEST FOR DATA: if ON requests for putting data on the
data bus. DATA VALID: if ON tells data is valid on the data bus otherwise
invalid
data.

(i) When destination is ready to receive data, Request for Data signal gets
activated. (ii) source in response puts data on the data bus and enabled Data
valid signal. (iii) Destination then accepts data from the data bus and after
accepting data, disabled Request for Data signal. (iv) At last, Data valid signal
gets disabled means data on the data bus is no more valid data. Now there is
surety that source has put the data on the data bus through data valid signal.
Signals can be seen
as:
 It shows that first Request for Data signal gets active then data is put on data
bus then Data valid signal gets active. After reading data, first Request for Data
signal gets off then Data valid signal.
The method that is used to transfer information between internal storage and
external I/O devices is known as I/O interface. The CPU is interfaced using
special communication links by the peripherals connected to any computer
system. These communication links are used to resolve the differences
between CPU and peripheral. There exists special hardware components
between CPU and peripherals to supervise and synchronize all the input and
output transfers that are called interface units.
Mode of Transfer:
The binary information that is received from an external device is usually
stored in the memory unit. The information that is transferred from the CPU
to the external device is originated from the memory unit. CPU merely
processes the information but the source and target is always the memory
unit. Data transfer between CPU and the I/O devices may be done in
different modes. Data transfer to and from the peripherals may be done in
any of the three possible ways
1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).
Now let’s discuss each mode one by one.
1. Programmed I/O: It is due to the result of the I/O instructions that
are written in the computer program. Each data item transfer is
initiated by an instruction in the program. Usually the transfer is
from a CPU register and memory. In this case it requires constant
monitoring by the CPU of the peripheral devices.
 Example of Programmed I/O: In this case, the I/O device does not
have direct access to the memory unit. A transfer from I/O device to
memory requires the execution of several instructions by the CPU,
including an input instruction to transfer the data from device to the
CPU and store instruction to transfer the data from CPU to memory.
In programmed I/O, the CPU stays in the program loop until the I/O
unit indicates that it is ready for data transfer. This is a time
consuming process since it needlessly keeps the CPU busy. This
situation can be avoided by using an interrupt facility. This is
discussed below.
2. Interrupt- initiated I/O: Since in the above case we saw the CPU
is kept busy unnecessarily. This situation can very well be avoided
by using an interrupt driven method for data transfer. By using
interrupt facility and special commands to inform the interface to
issue an interrupt request signal whenever data is available from
any device. In the meantime the CPU can proceed for any other
program execution. The interface meanwhile keeps monitoring the
device. Whenever it is determined that the device is ready for data
transfer it initiates an interrupt request signal to the computer. Upon
detection of an external interrupt signal the CPU stops momentarily
the task that it was already performing, branches to the service
program to process the I/O transfer, and then return to the task it
was originally performing.
• The I/O transfer rate is limited by the speed with which the
processor can test and service a device.
• The processor is tied up in managing an I/O transfer; a
number of instructions must be executed for each I/O
transfer.
• Terms:
• Hardware Interrupts: Interrupts present in the
hardware pins.
• Software Interrupts: These are the instructions
used in the program whenever the required
functionality is needed.
• Vectored interrupts: These interrupts are
associated with the static vector address.
• Non-vectored interrupts: These interrupts are
associated with the dynamic vector address.
• Maskable Interrupts: These interrupts can be
enabled or disabled explicitly.
• Non-maskable interrupts: These are always in
the enabled state. we cannot disable them.
• External interrupts: Generated by external
devices such as I/O.
• Internal interrupts: These devices are generated
by the internal components of the processor
 such as power failure, error instruction,
temperature sensor, etc.
• Synchronous interrupts: These interrupts are
controlled by the fixed time interval. All the
interval interrupts are called as synchronous
interrupts.
• Asynchronous interrupts: These are initiated
based on the feedback of previous instructions.
All the external interrupts are called as
asynchronous interrupts.
Direct Memory Access: To transfer large blocks of data at high speed, this third method is
used. A special controlling unit may be provided to allow transfer a block of data directly between a high
speed external device like magnetic disk and the main memory, without continuous intervention by the
CPU. This method iscalled direct memory access (DMA).
DMA transfers are performed by a control circuit that is part of the I/O device interface. We refer
to this circuit as a DMA controller. The DMA controller performs the functions that would normally
be carried out by the CPU when accessing the main memory. During DMA transfer, the CPU is idle
or can be utilized to execute another program and CPU has no control of the memory buses. A DMA
controller takes over the buses to manage the transfer directly between the I/O device and the main
memory.
DMA Transfer:
DMA Transfer Modes DMA transfers can be of two types: cycle stealing and block (burst)
transfer.
Memory accesses by the CPU and the DMA controllers are interlocking. Requests by DMA
devices for using memory buses are always given higher priority than processor requests. Among
different DMA devices, top priority is given to high-speed peripherals such as a disk, a high-speed
network interface or a graphics display device. Since the CPU originates most memory access cycles,
the DMA controller can be said to “steal” memory cycles from the CPU. Hence, this interlocking
technique usually called cycle stealing.
When DMA controller is the master of the memory buses, a block of memory words is transferred
in continuous without interruption. This mode of DMA transfer is known as block (burst) transfer.
This mode of transfer is needed for fast devices such as magnetic disks, where data transmission
cannot be stopped or slowed down until an entire block is transferred.
Advantages of DMA
It is a hardware method, whereas programmed I/O and interrupt I/O aresoftware methods of data
transfer. DMA mode has following advantages:
1. High speed data transfer is possible, since CPU is not involved during actual transfer, which
occurs between I/O device and the main memory.
2. Parallel processing can be achieved between CPU processing and DMA controller’s I/O operation.