UNIT-I

UNIT-IV
COA (TBC-304)

I/O organizations

[1]. Peripherals devices (Home work)

The input–output subsystem, provides communication between the CPU and peripherals.
As keyboard is a slow device, the processor became idle most of the time. To use a
computer efficiently, a large amount of programs and data must be available for processor.

Devices that are under the direct control of the computer are said to be connected on-line.
I/O devices attached to the computer are also called peripherals. There are three types of
peripherals such as input, output, and input–output peripherals. These peripherals may be
analog or digital and serial or parallel. Some of the peripherals are:

1. Mouse
2. Keyboard
3. Webcam
4. Microphone
5. Monitor
6. Speakers
7. Scanner
8. Projector
9. Printer
10.USB Flash Drive
11.External Hard Drive

(students are required to write 10 lines on each peripheral)

[2]. input-output interface

I/O interface is used to transfer data between internal storage and external I/O devices.
There must be communication link b/w Peripherals and CPU. This link is used to resolve
the differences between the central computer and each peripheral. The major differences
are:

1. Peripherals are electromechanical and electromagnetic devices and their working is

different from the working of CPU and memory. Therefore, a conversion of signal is
needed.
2. The speed of peripherals is slower than the speed of CPU. So, a synchronization is
needed to match the speed of peripherals and CPU.

1
 3. Data codes and formats of peripherals different from the format in the CPU and
memory.
4. The working of peripherals are different from each other and each must be controlled
so that they can not interfare operation of other peripherals.

To resolve these differences, computer systems include special hardware components

between the CPU and peripherals. These components are called interface units

[3]. I/O Bus and Interface Modules

A communication link between the processor and peripherals is shown in above figure. The
I/O bus has data lines, address lines, and control lines. Each peripheral device has its own
interface unit. These interfaces perform the following functions:

• It decodes the address and control received by CPU

• It manages the working of peripheral.
• It also synchronizes the speed of CPU and peripheral using buffer.

For example, the printer controller controls the paper motion, the print timing, and the
selection of printing characters.

The I/O bus is connected to all peripheral interfaces. To communicate with a device, the
processor sends the address of device in address lines. Each interface checks the incoming
address with its own address. It activates the path between the bus lines and the device. All
peripherals whose address does not matched become disabled by their interface. Now the
processor sends control signals in the control lines and data in data line.

2
Processor can generates four types of commands for peripherals:

3.1 Control command A control command tells the device what to do and how to
do.

3.2 Status command A status command is used to check the condition of devices.

3.3 Data output command When a device receives data output command it transfer
the data to processor.

3.4 Data input command When a device receives data input command it takes the
data fron data bus and store the data in its buffer.

[4]. I/O versus Memory Bus

Processor uses I/O bus to communicate with peripherals. Similarly, Processor uses memory
bus to communicate with memory. Like the I/O bus, the memory bus contains data,
address, and read/write control lines. There are three ways by which I/O bus and Memory
bus can be used:

1. Use two separate buses, one for memory and the other for I/O. (Fig-1)

2. Use one common bus for both memory and I/O but have separate control lines for
each. (Fig-2)

3. Use one common bus for memory and I/O with common control lines. (Fig-3)

Figure-1

3
 Figure-2

Figure-3

[5]. Isolated versus Memory-Mapped I/O

Many computers use one common bus to transfer information between memory or I/O and
the CPU.

Write
Read
Processor Data Bus Peripherals
Address Bus
Write
Read

Memory

4
5.1 Isolated I/O

The CPU specifies whether the address is for a memory by using read or write lines. The
I/O read and I/O write control lines are activated during an I/O transfer. The memory read
and memory write control lines are activated during a memory transfer.

In this method address of all peripherals and memory may be same. For example addresses
of peripherals starts from 0 to 100 and address of memory cells starts from 0 to 100. For
example let processor want to fetch data from memory address 50, so it passes 50 in address
line. This address is found in peripherals as well as in memory. Both of them can provide
data to processor. But at the same time processor activated read/ write control lines of
memory so only memory sends the data to processor.

5.2 Memory mapped I/O

In a memory-mapped I/O organization there are no separate Read/Write control lines.

In this method address of all peripherals and memory cells should be different. For example
if addresses of peripherals starts from 0 to 100 the address of memory cells should greater
than 100 for ex- 101 to 500. In this case if want to communicate with peripheral the it
generate addres between 0 and 100. If it wants to communicate with memory then it
generates address between 101 to 500.

[6]. Asynchronous Data Transfer

The internal operations in a digital system are synchronized by means of clock pulses.
Computer units are designed independently of each other. If two units share a common
clock for data transfer then it is called as synchronous data transfer and the two devices are
called as synchronous devices.

5
In most cases, the computer units uses its own private clock for data transfer. In that case,
the two units are said to be asynchronous to each other and the data transfer is called
asynchronous data transfer. This approach is widely used in most computer systems.

To transfer data between to asynchronous units a control signals is transmitted between

them. This signal indicate the time at which data is being transmitted. For this a strobe
signal (pulse) is sent by one of the units to indicate to the other unit when the transfer will
start. Another method commonly used method is Handshaking.

6.1 Strobe Control Method

The strobe signal may be sent by either the source or the destination unit.

• Figure A shows a source-initiated transfer. The data bus is used to send the data to
the destination unit. The source unit first places the data on the data bus. After some
delay it sends the strobe signal. The data and strobe signal remain in the active state
for a sufficient time period to allow the destination unit to receive the data. When
destination receives data, the source removes the data from the bus and disables its
strobe signal.

Data bus
Source Unit Destination
Strobe signal Unit

Fig-A

• Figure B shows a data transfer initiated by the destination unit. In this case the
destination unit sends the strobe signal to inform the source to provide the data. The
source unit responds by placing data on the data bus.

Data bus
Destination
Source Unit Strobe signal Unit

Fig-B

6
6.2 Handshaking Method

In strobe method source unit does not know that whether the destination unit received the
data or not. Similarly, a destination unit does not know that whether the source unit has
placed the data on the bus or not. The handshaking method solves this problem by using a
control signal. This signal is known as acknowledgement. Handshaking of two types

• Source initiated handshaking

• Destination initiated handshaking

A. Source initiated handshaking

(a) Block diagram

(b) Event Diagram

The “data bus” is used by source unit to send data. The “data valid” line is used by source
unit to inform destination unit that whether data is valid or not. The “Data Accepted” is
used by destination unit to inform source unit that it has received the data
(acknowledgement).

Working: Working of Source initiated handshaking is shown in figure: (b).

Step-1: the source unit places data in data bus and set Data Valid signal=1.

7
 Step-2: When destination unit found 1 in Data valid line then it takes data from data
bus. After this it sets Data Accepted signal=1. It works as acknowledgement.

Step-3: By this signal source unit understand that destination has received the data.
The it sets Data valid signal =0.

Step4: Now destination unit sets Data Accepted signal=1

B. Destination Source initiated handshaking

(a) Block diagram

(b) Event Diagram

The “data bus” is used by source unit to send data. The “data valid” line is used by source
unit to inform destination unit that whether data is valid or not. The “Ready for data” is
used by destination unit to inform source unit that it needs data

Working: Working of destination initiated handshaking is shown in figure: (b).

Step-1: the destination unit sends a signal to source unit by setting Ready for data=1

Step-2: when source unit receives this signal then it places data in data bus and set
Data Valid signal=1.

Step-3: When destination unit found 1 in Data valid line then it takes data from data
bus. After this it disable Ready for data signal. It works as acknowledgement.

8
 Step-4: By this signal source unit understand that destination has received the data.
Then it disable Data valid signal.

[7]. modes of transfer

Data transfer between the CPU and I/O devices may be done in one of three possible ways
(modes):

1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)

A. Programmed I/O

Programmed I/O operations uses I/O instructions (computer program). Instructions are used
to transfer the data. In the programmed I/O method, the I/O device does not have direct
access to memory. The transfer of data, CPU executes several instructions. Some
instructions may be needed to verify that the data are available from the device and to count
the numbers of words transferred. In this, the CPU waits in a program loop until the I/O
operation is started by peripherals. Once a data transfer is initiated, the CPU is required to
monitor the interface to see when a transfer can again be made. This is a time-consuming
process since it keeps the processor busy needlessly.

Example of Programmed I/O

An example of data transfer from an I/O device through an interface into the CPU is shown
in Fig. The device transfers bytes of data one at a time as they are available. When a byte of
data is available, the device places it in the I/O bus and enables its data valid line. The
interface accepts the byte into its data register and enables the data accepted line. The
interface sets a bit in the status register that we will refer to as an F or “flag” bit. The device
can now disable the data valid line, but it will not transfer another byte until the data accepted
line is disabled by the interface. This is same as the handshaking.

9
B. Interrupt-Initiated I/O

The CPU performance can be improved by using an interrupt facility. Interfaces use special
commands to issue an interrupt request signal to CPU. In the meantime the CPU can
execute another program. The interface monitors the device. When the interface determines
that the device is ready for data transfer, it generates an interrupt request to the computer.
Upon detecting the external interrupt signal, the CPU momentarily stops the task it is
processing, branches to a service program to process the I/O transfer, and then returns to the
task it was originally performing.

In principle, there are two methods for branching accomplishing this. One is called vectored
interrupt and the other, non-vectored interrupt. In a non-vectored interrupt, the branch
address is assigned to a fixed location in memory. In a vectored interrupt, the branch
address is provide by interface to CPU.

C. DMA

The data transfer is slower than the speed of CPU. DMA is a hardware that controls the data
transfer and it makes CPU free. So, CPU can do other important tasks. This transfer
technique is called direct memory access (DMA). In DMA, the interface transfers data into
and out of the memory unit. The CPU activates DMA by sending the starting address and
the number of words needed to be transferred.

During DMA transfer, processor leaves the bus system for DMA. Following figure shows
block diagram of DMA controller and signals for DMA transfer.

10
 DMA Controller

Here:-
1. DS (DMA Select)- processor set DS=1 to activate DMA.
2. RS (Register Select)-
CPU selects DMA registers to store values (such as starting address and no.of words to be
transferred).
3. RD( Read) & WR (Write)-
It is used for reading and writing purpose.
4. BR (Bus request)-
The DMA use this line to send a request to processor to release the BUS system.
5. BG (Bus Grant)-
When Processor leave the bus system for DMA then it sets BG=1.
6. Interrupt-
when data transfer is completed then DMA send a singal through this line. Processor can also use this
line to check whether data transfer has been completed or not.
7. DMA Request- It is used by I/O devices to send a request to DMA.
8. DMA Acknowledgement- DMA send response by this line to I/O devices.
9. Address register- processor stores starting address of data in this register.
10. Word count register- processor stores total no of word (to be transferred) in this register.
11. Control Register- processor stored control signals in this register.

11
 12. Data Bus Buffer- It is used to store data.
13. Data Bus- DMA uses this bus to transfer data

Signals for DMA transfer

C.1 DMA Transfer (working of DMA)

DMA Initialization
Processor starts DMA by sending following information to DMA:

• Starting address of data (in address register).

• Total number of words to be transferred ( in word count register)
• Control signals (in control register)
• A signal to start DMA. ( using DMA select line)

Working of DMA

1. When an I/O devices wants to transfer data, it sends request to DMA (using DMA
request line).
2. Now DMA sends bus request (BR=1) to processor to leave the bus system (using BR
line).
3. When processor receives this signal, it stores its current work. Now processor sends
above 4 information to DMA and leave the bus system and inform DMA by BG line
( using BG line {BG=1}).
4. When DMA receives BG signal it activates DMA acknowledgement line to inform
I/O device and starts data transfer.
5. At every transfer, value of WC register is decremented by 1.
6. When WC=0, DMA sets BR=0 and sends an interrupt signal to CPU.

12
 7. Now CPU checks WC register. It is 0 so CPU sets BG=0 and starts using the Bus
system for its own purpose.

[8]. Input-Output Processor (IOP)

Generally, the device interface communicate with the CPU. A computer may use one or more
external processors. These processors are called IO Processor. These processor
communicates with all I/O devices directly. As shown in figure, such configuration can has
a memory unit, and a number of processors (CPU and IOPs). Each IOP takes care of input
and output tasks, relieving the CPU.

The IOP is similar to a CPU except that it is designed to handle I/O processing only. Unlike
the DMA controller, the IOP can fetch and execute its own instructions. In addition, the IOP
can perform other processing tasks, such as arithmetic, logic, branching, and code translation.

13
The memory unit can communicate with each processor by means of direct memory access.
The IOP provides a path for transfer of data between various peripheral devices and the
memory unit. IOP operates independent of the CPU.

The data formats of peripheral devices differ from memory and CPU data formats. The IOP
must structure data words. For example, it receives 4 bytes from an input device and pack
them into one 32-bit word before the transfer to memory.

In most computer systems, the CPU is the master while the IOP is a slave processor. The
CPU is assigned the task of initiating all operations, but I/O instructions are executed by IOP.
CPU provide operations to start an I/O transfer and also to test I/O status conditions.

CPU—IOP Communication

The sequence of operations are shown in the following flowchart.

The CPU sends an instruction to test the IOP path.

The IOP responds by sending its status.

The CPU sends the instruction to start I/O transfer by sending the address. This memory
address tells the IOP where to start?

The CPU can now continue with another program while the IOP is busy with the I/O
program.

When data transfer is completed, the IOP sends an interrupt request to the CPU.

The CPU read the status from the IOP. The IOP responds by placing the contents of its
status report into a specified memory location.

The status word indicates whether the transfer has been completed or any errors occurred
during the transfer.

14
[9]. Serial Communication

A data communication processor is an I/O processor that distributes and collects data from
many remote terminals connected through telephone and other communication lines. It is a
specialized I/O processor designed to communicate directly with data communication
networks. A communication network may consist of any of a wide variety of devices, such
as printers, interactive display devices, digital sensors, or a remote computing facility. With
the use of a data communication processor, the computer can service fragments of each
network demand in an interspersed manner and thus have the apparent behavior of serving
many users at once. In this way the computer is able to operate efficiently in a time-sharing
environment. The most striking difference between an I/O processor and a data
communication processor is in the way the processor communicates with the I/O devices. An
I/O processor communicates with the peripherals through a common I/O bus that is comprised
of many data and control lines. All peripherals share the common bus and use it to transfer

15
information to and from the I/O processor. A data communication processor communicates
with each terminal through a single pair of wires. Both data and control information are
transferred in a serial fashion with the result that the transfer rate is much slower. The task of
the data communication processor is to transmit and collect digital information to and from
each terminal, determine if the information is data or control and respond to all requests
according to predetermined established procedures. The processor, obviously, must also
communicate with the CPU and memory in the same manner as any I/O processor.

The way that remote terminals are connected to a data communication processor is via
telephone lines or other public or private communication facilities. Since telephone lines were
originally designed for voice communication and computers communicate in terms of digital
signals, some form of conversion must be used. The converters are called data sets, acoustic
couplers, or modems (from “modulator-demodulator”). A modem converts digital signals into
audio tones to be transmitted over telephone lines and also converts audio tones from the line
to digital signals for machine use. Various modulation schemes as well as different grades of
communication media and transmission speeds are used.

A communication line may be connected to a synchronous or asynchronous interface,

depending on the transmission method of the remote terminal. An asynchronous interface
receives serial data with start and stop bits in each character.

Synchronous transmission does not use start-stop bits to frame characters and therefore makes
more efficient use of the communication link. Highspeed devices use synchronous
transmission to realize this efficiency. The modems used in synchronous transmission have
internal clocks that are set to the frequency that bits are being transmitted in the
communication line. For proper operation, it is required that the clocks in the transmitter and
receiver modems remain synchronized at all times. The communication line, however,
contains only the data bits from which the clock information must be extracted. Frequency
synchronization is achieved by the receiving modem from the signal transitions that occur in
the received data. Any frequency shift that may occur between the transmitter and receiver
clocks is continuously adjusted by maintaining the receiver clock at the frequency of the
incoming bit stream. The modem transfers the received data together with the clock to the
interface unit. The interface or terminal on the transmitter side also uses the clock information
from its modem. In this way, the same bit rate is maintained in both transmitter and receiver.

Contrary to asynchronous transmission, where each character can be sent separately with its
own start and stop bits, synchronous transmission must send a continuous message in order
to maintain synchronism. The message consists of a group of bits transmitted sequentially as
a block of data. The entire block is transmitted with special control characters at the beginning

16
and end of the block. The control characters at the beginning of the block supply the
information needed to separate the incoming bits into individual characters.

One of the functions of the data communication processor is to check for transmission errors.
An error can be detected by checking the parity in each character received. Another procedure
used in asynchronous terminals involving a human operator is to echo the character. The
character transmitted from the keyboard to the computer is recognized by the processor and
retransmitted to the terminal printer. The operator would realize that an error occurred during
transmission if the character printed is not the same as the character whose key he has struck.

In synchronous transmission, where an entire block of characters is transmitted, each

character has a parity bit for the receiver to check. After the entire block is sent, the transmitter
sends one more character that constitutes a parity over the length of the message. This
character is called a longitudinal redundancy check (LRC) and is the accumulation of the
exclusive-OR of all transmitted characters. The receiving station calculates the LRC as it
receives characters and compares it with the transmitted LRC.

The calculated and received LRC should be equal for error-free messages. If the receiver
finds an error in the transmitted block, it informs the sender to retransmit the same block once
again. Another method used for checking errors in transmission is the cyclic redundancy
check (CRC). This is a polynomial code obtained from the message bits by passing them
through a feedback shift register containing a number of exclusive-OR gates. This type of
code is suitable for detecting burst errors occurring in the communication channel.

Data can be transmitted between two points in three different modes: simplex, half-duplex,
or full-duplex. A simplex line carries information in one direction only. This mode is seldom
used in data communication because the receiver cannot communicate with the transmitter to
indicate the occurrence of errors. Examples of simplex transmission are radio and television
broadcasting. A half-duplex transmission system is one that is capable of transmitting in both
directions but data can be transmitted in only one direction at a time. A pair of wires is needed
for this mode. A common situation is for one modem to act as the transmitter and the other
as the receiver. When transmission in one direction is completed, the role of the modems is
reversed to enable transmission in the reverse direction. The time required to switch a half-
duplex line from one direction to the other is called the turnaround time. A full-duplex
transmission can send and receive data in both directions simultaneously. This can be
achieved by means of a four-wire link, with a different pair of wires dedicated to each
direction of transmission. Alternatively, a two-wire circuit can support full-duplex
communication if the frequency spectrum is subdivided into two nonoverlapping frequency
bands to create separate receive and transmit channels in the same physical pair of wires.

17
The communication lines, modems, and other equipment used in the transmission of
information between two or more stations is called a data link. The orderly transfer of
information in a data link is accomplished by means of a protocol. A data link control protocol
is a set of rules that are followed by interconnecting computers and terminals to ensure the
orderly transfer of information. The purpose of a data link protocol is to establish and
terminate a connection between two stations, to identify the sender and receiver, to ensure
that all messages are passed correctly without errors, and to handle all control functions
involved in a sequence of data transfers. Protocols are divided into two major categories
according to the message-framing technique used. These are character-oriented protocol and
bit-oriented protocol.

18