COA (CoSc 2041)

Chapter V
Input-Output Organization
Peripheral Devices
Input Devices
•Keyboard, Mouse
•Optical input devices- Card Reader, Paper Tape Reader, Bar code reader, Digitizer, OMR
•Magnetic Input Devices- Magnetic Stripe Reader
•Screen Input Devices- Touch Screen, Light Pen
•Analog Input Devices
Output Devices
•Card Puncher, Paper Tape Puncher
•CRT
•Printer (Dot Matrix, Ink Jet, Laser)
•Plotter
Input / Output Interface
Provides a method for transferring information between internal storage (such as memory and
registers) and external I/O devices
• Resolves the differences between the computer and peripheral devices
– Peripherals are Electromechanical Devices
– CPU or Memory is an Electronic Device
– Data Transfer Rate
» Peripherals - Usually slower
» CPU or Memory - Usually faster than peripherals
• Some kinds of Synchronization mechanism may be needed
– Unit of Information
» Peripherals – Byte, Block, …
» CPU or Memory – Word
– Data representations may differ in Peripheral devices compared to CPU/Memory

I/O Bus and Memory Bus

Memory Bus is for information transfers between CPU and the Main Memory. I/O Bus is for
information transfers between CPU and I/O devices through their I/O interface.
Physical organization
* Many computers use a common single bus system for both memory and I/O interface units.
- Use one common bus with common control lines for both functions
- Use one common bus but separate control lines for each function
- Some computer systems use two separate buses, one to communicate with memory and
the other with I/O interfaces.

I/O Bus
- Communication between CPU and all interface units is via a common I/O Bus
- An interface connected to a peripheral device may have a number of data registers, a control
register, and a status register
- A command is passed to the peripheral by sending to the appropriate interface register.
- Transfer of data, control, and status information is always via the common I/O Bus.

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I/O Bus and Interface Modules

Each peripheral has an interface module associated with it. An Interface does the following;
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller.
- Synchronizes the data flow and supervises the transfer rate between peripheral and CPU or
memory
I/O Interface

Programmable Interface
- Information in each port can be assigned a meaning depending on the mode of operation of
the I/O device
→ eg: Port A = Data; Port B = Command; etc..
- CPU initializes (loads) each port by transferring a byte to the Control Register
→ CPU can define the mode of operation of each port
→ By changing the bits in the control register, it is possible to change the interface
characteristics

Isolated v/s Memory Mapped I/O

Different methods are there to perform input/output operation between the CPU and peripheral
devices in a computer. The major two methods are Isolated I/O and memory mapped I/O.
Isolated I/O
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- Separate I/O read/write control lines in addition to memory read/write control lines
- Separate (isolated) memory and I/O address spaces.
- Distinct input and output instructions.

Memory mapped I/O

- A single set of read/write control lines (no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space-reduces memory address range
available
- No specific input or output instruction-the same memory reference instructions can be used for
I/O transfers also.
- Considerable flexibility in handling I/O operations.

Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that control signals be
transmitted between the communicating units to indicate the time, at which data is being
transmitted.
- No common clock
Two Asynchronous Data Transfer Methods are Strobe pulse and Handshaking
Strobe pulse
- A strobe pulse is supplied by one unit to indicate the other unit when the transfer has to occur.
Handshaking
- A control signal is accompanied with each data transmission to indicate the presence of data.
- The receiving unit responds with another control signal to acknowledge receipt of the data.
Strobe Control
* Employs a single control line with each data transfer
* The strobe may be activated by either the source or the destination unit

The source unit that initiates the transfer has no way of knowing whether the destination unit has
actually received data. The destination unit that initiates the transfer has no way of knowing
whether the source has actually placed the data on the bus. To solve this problem, the
HANDSHAKE method introduces a second control signal to provide a reply to the unit that
initiates the transfer

Handshaking
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Handshaking provides a high degree of flexibility and reliability because the successful
completion of a data transfer relies on active participation by both units. If one unit is faulty, data
transfer will not be completed - Can be detected by means of a timeout mechanism.

Source-Initiated Transfer Using Handshake

Destination-Initiated Transfer Using Handshake

Modes of Transfer
There are 3 major different Data Transfer Modes (I/O techniques) between the central computer
(CPU or memory) and peripherals, and those are
1) Program Controlled I/O
2) Interrupt Driven/initiated I/O
3) Direct Memory Access (DMA)

1) Program Controlled I/O

In Program Controlled I/O, CPU has direct control over I/O method-like Sensing status,
Read/write commands, even transferring data. CPU waits for I/O module to complete operation,
so causes wastage of time. CPU is dedicated to the task of I/O and can therefore transfer data at a
higher rate. The data transfer is very like memory access (CPU viewpoint). Each device is given
a unique identifier. CPU commands contain identifier (address).
How does it work:-
• CPU requests I/O operation.
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• I/O module performs operation.
• I/O module sets status bits.
• CPU checks status bits periodically.
• I/O module does not inform CPU directly.
• I/O module does not interrupt CPU.
• CPU may wait or come back later.

What is an Interrupt?
An interrupt is a signal from a device attached to a computer or from a program within the
computer that causes some disturbance for the Running Process (executed by the CPU ) of the
computer and figure out what to do next. After the interrupt signal is sensed, the computer either
resumes running the program it was running or begins running another program. Interrupts can
be generated by Software or the Hardware. But CPU will handle all the Interrupts very carefully
and will also provide response to the various interrupts.
Interrupt Processing:
• Processor checks for interrupt by an interrupt signal
• If no interrupt, CPU will fetch next instruction
• If interrupt pending:
— Suspend execution of current program
— Save context
— Set PC to start address of interrupt handler routine
— Process interrupt
— Restore context and continue interrupted program

Priority Interrupt

Priority determines which interrupt is to be served first when two or more requests are made
simultaneously. Also it determines which interrupts are permitted to interrupt the CPU while
another is being serviced. Higher priority interrupts can make requests while servicing a lower
priority interrupt.
Priority Interrupt by Software
- Priority is established by the order of requesting devices (interrupt sources)
- Flexible, since it is established by software.

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- Low cost since it needs a very little hardware and is very slow.
Priority Interrupt by Hardware
- Require a priority interrupt manager which accepts all the interrupt requests to determine the
highest priority request
- Fast, since identification of the highest priority interrupt request is identified by the hardware.
- Each interrupt source has its own interrupt vector to access directly to its own service routine.

Software Priority Interrupt – Polling

Polling Scheme
 Identifies the highest-priority by means of software.
» Program polls the different interrupt sources in sequence.
 The IRQ (interrupt request) bit in the status register is set when a device interrupts.
• The Interrupt service routine polls the I/O devices connected to the bus.
• The first device encountered with its IRQ bit set, is serviced as the highest priority device.
• Easy to implement, but time consuming process on checking the IRQ bits of all devices, though
some devices may not be requesting service.

Software Polling Chart

Hardware Priority Interrupt – Daisy_Chain

The hardware priority function can be established by either a serial or a parallel connection of
interrupt lines. The serial connection is called daisy chaining method. In daisy chaining method,
all the devices are connected in serial. The device with the highest priority is placed in the first
position, followed by lower priority devices and last, the lowest as shown in the below diagram.

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The interrupt request line is common to all or any devices. The CPU responds to an interrupt
request by enabling the interrupt acknowledge line. This signal is received by the first device at
its PI input. If the first device has pending interrupt, it blocks the acknowledge signal from
following device by putting zero within the PO output. It then proceeds to insert its own interrupt
vector address (VAD) into the bus for the CPU to use throughout the interrupt cycle. If the first
device is not requesting an interrupt, the acknowledge signal passes on to following device
through the PO output. This procedure is outlined in the above diagram.
A device with PI=1 and PO=0 is that the one with the very best priority that’s requesting an
interrupt, and this device places its VAD on the information bus. The farther the device is from
the primary position; the lower is its priority. If the device doesn’t have pending interrupts, it
transmits the acknowledgement signal to following device by putting PO=1 as output.

2) Interrupt Driven (or Initiated) I/O

In interrupt initiated I/O, it overcomes the waiting process of CPU and there is no repeated
checking of device’s status by the CPU. Instead, I/O module interrupts the CPU when the device
is ready by monitors the I/O device. When the interface identified that the I/O device is ready for
data transfer, it generates an interrupt request to the CPU. Upon detecting an interrupt, CPU may
pause the task it is doing, branches to the interrupt handling service. After completing that task,
the CPU will returns to the task it was performing.
How does it work:-
• CPU issues read command
• I/O module gets data from peripheral whilst CPU does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data

3) DMA (Direct Memory Access)

Transferring large blocks of data at high speed, between External devices & Main Memory, with
minimal intervention by the processor is called direct memory access (DMA). DMA transfers are
performed by a control circuit that is part of the I/O device interface, referred as a DMA
controller. Although a DMA controller can transfer data directly between I/O device and
Memory, its operation must be under the control of a program executed by the processor.

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Request by DMA devices for using the bus are always given higher priority than processor
requests. Among different DMA devices, top priority is given to high-speed peripherals such as a
disk, a high speed network interface, etc.

DMA Controller in a Computer System

Since the processor originates most memory access cycles, the DMA controller can be said to
“steal” memory cycles from the processor. Hence, this interweaving technique is usually called
cycle stealing. The DMA controller may transfer a block of data without interruption. This is
called block/burst mode

To initiate transfer of a block of words, the processor sends the following data to controller
– The starting address of the memory block
– The word count (amount of data to be transferred)
– Control to specify the mode of transfer such as read or write
– A control to start the DMA transfer
Actual transfer of data is done directly between the device and memory through DMA controller,
freeing CPU for other tasks. DMA controller sends an interrupt to the processor upon
completion.

DMA Operation

Input / Output Processor (IOP)

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The IOP is a processor that is separate from the main Processor or CPU designed to handle only
input/output processes. A channel command word (CCW) is an instruction to a specialized I/O
channel processor. It is used to initiate an I/O operation, such as "read" or "write" on a channel-
attached device. IOP communicate with peripherals through a common I/O bus (data, address,
control bus)
- Processor with direct memory access capability that communicates with I/O devices directly.
- Can access the memory by cycle stealing.
- Fetch and execute its own instructions
» IOP instructions are specifically designed to facilitate I/O transfer.
» DMAC must be set up entirely by the CPU.
- Designed to handle the details of I/O processing.

Channel / CPU Communication

Serial Communication

Modem
- Convert digital signals into audio tones to be transmitted over telephone lines
- Various modulation schemes are used (FM, AM, PCM)
Block transfer
- An entire block of characters is transmitted in synchronous transmission
- Transmitter sends one more character (error check) after the entire block is sent

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3 Transmission Systems
- Simplex : one direction only
- Half-duplex : both directions but only one direction at a time
- Full-duplex : both directions simultaneously
Data Link
- The communication lines, modems, and other equipments used in the transmission of
information between two or more stations

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