Memory Design and Testing

– ELL749

Kaushik Saha
Contact: ksaha@ee.iitd.ac.in
 Course Logistics
• Class will meet twice a week (1.5hrs + 1.5hrs)
• 1 hr teaching, 0.5 hr project review
• Grading Policy
• Project
• Project Review - 60
• Every class will project review
• every project group will present its progress every
alternate week
• Project Document - 20
• Majors – 20
• Course evaluation has 80% component of project
• Project relies heavily on circuit design, schematic entry,
simulation and layout skills
• requires familiarity with backend VLSI CAD tools – Virtuoso, HSPICE,
DRC, LVS
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Texts
• Semiconductor Memories, A Handbook of Design,
Manufacture and Application (2nd Ed) – Betty
Prince
• John Wiley & Sons UK, ISBN 0 471 92465 2; 0 471
94294 2 (pbk)
• Journal articles and Web material
• Course material will be made available on
• USB drive
• Course newsgroup

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 Agenda of Topics
• 1) Memory hierarchy in digital systems
• 2) Static RAM
• a. Types
• b. Overall architecture
• c. SRAM Cell
• i. Design
• ii. Layout
• iii. Noise issues and margins
• iv. Assembly of core
• d. Peripheral circuitry
• i. Decoding
• ii. Array conditioning for r/w
• iii. Sensing
• iv. Writing
• v. Synchronisation
• 3) Dynamic RAM
• a. Types
• b. Cell design
• c. Assembly of core
• i. Core architectures
• d. Peripheral circuitry
• i. Sensing
• ii. Elevated voltage supplies
• e. Modern high speed DRAM
• i. EDO, 4
• ii. SDR,
• iii. DDR
Agenda of Topics cont’d
• 4) Non volatile memories
• a. ROM
• i. Array design
• b. EPROM
• i. Cell and array design
• c. EEPROM
• i. Tunneling phenomena
• ii. EEPROM cell
• 1. Hot carrier based operation
• 2. Tunneling based operation
• d. Flash memories
• i. Cell operation and design
• ii. Types of modern high density flash memories
• 1. NOR flash
• 2. NAND flash

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Classification of Memories
RWMemory NVRWM ROM

Random Non-Random
Access Access EPROM Mask
EEPROM Programmed

FLASH PROM (Fuse

SRAM (Static) FIFO (Queue) Programmed)
DRAM LIFO (Stack)
(Dynamic) SR (Shift
Register)
CAM (Content
Addressable)

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Feature Comparison Between Memory Types

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Memory selection : cost and performance
• DRAM, EPROM
• Merit : cheap, high density
• Demerit : low speed, high power
• SRAM
• Merit : high speed or low power
• Demerit : expensive, low density
• Large memory with cost pressure :
• DRAM
• Large memory with very fast speed :
• SRAM or
• DRAM main + SRAM cache
• Back-up main for no data loss when power failure
• SRAM with battery back-up
• EEPROM

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The Need for Innovation in Memory Industry

• The learning rate (viz. the constant b) is the highest for the memory
industry
• Because prices drop most steeply among all ICs
• Due to the nature of demand + supply
• Yet margins must the maintained
• Techniques must be applied to reduce production cost
• Often, memories are the launch vehicles for a technology node
• Leads to volatile nature of prices

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 Memory Hierarchy of a Modern Computer System

• By taking advantage of the principle of locality:

• Present the user with as much memory as is available in the cheapest
technology.
• Provide access at the speed offered by the fastest technology.

Processor

Control Tertiary
Secondary Storage
Storage (Tape)
Second Main
(Disk)
On-Chip Level Memory
Registers

Cache
Datapath Cache (DRAM)
(SRAM)

Speed (ns): 1s 10s 100s 10,000,000s 10,000,000,000s

(10s ms) (10s sec)
Size (bytes): 100s Ks Ms Gs Ts
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 How is the hierarchy managed?
• Registers <-> Memory
• by compiler (programmer?)
• cache <-> memory
• by the hardware
• memory <-> disks
• by the hardware and operating system (virtual memory)
• by the programmer (files)

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 Memory Hierarchy Technology

• Random Access:
• “Random” is good: access time is the same for all locations
• DRAM: Dynamic Random Access Memory
• High density, High power, cheap, slow
• Dynamic: need to be “refreshed” regularly
• SRAM: Static Random Access Memory
• Low density, Lower power, expensive, fast
• Static: content will last “forever”(until lose power)
• “Not-so-random” Access Technology:
• Access time varies from location to location and from time to time
• Examples: Magnetic disks, Optical drives

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 Main Memory Background
• Performance of Main Memory:
• Latency: Cache Miss Penalty
• Access Time: time between request and word arrives
• Cycle Time: time between requests
• Bandwidth: I/O & Large Block Miss Penalty (L2)
• Main Memory is DRAM : Dynamic Random Access Memory
• Dynamic since needs to be refreshed periodically Addresses divided into 2 halves
(Memory as a 2D matrix):
• RAS or Row Access Strobe
• CAS or Column Access Strobe
• Cache uses SRAM : Static Random Access Memory
• No refresh (6 transistors/bit vs. 1 transistor)
Size: DRAM/SRAM 4-8
Cost/Cycle time: SRAM/DRAM 8-16

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Memory Interfaces
• Address i/ps
• Maybe latched with strobe signals
• Write Enable (/WE)
• To choose between read / write
• To control writing of new data to memory
• Chip Select (/CS)
• To choose between memory chips / banks on system
• Output Enable (/OE)
• To control o/p buffer in read circuitry
• Data i/os
• For large memories data i/p and o/p muxed on same pins,
• selected with /WE
• Refresh signals

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 Memory - Basic Organization

S0 Word 0

• N words
S1 Word 1
Single
• M bits per word
Storage
S2 Word 2
Cell
• N select lines

• 1:N decoder

• very inefficient design

SN-2 Word N-2
• difficult to place and route
SN-1 Word N-1

M bit output word

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Memory - Real Organization
Array of R x C words
------------- columns ------------ CxM
S0
C of M bit words row 0

------------- rows R------------

C of M bit words row 1

C of M bit words row 2

Log2R Row
Address Decoder
Lines
C of M bit words row R-2

C of M bit words row R-1

SR-1
- - - - CxM bits - - - -
Log2C
Address Column Select
Lines

N=R*C M bit data word

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Memory - Organization and Cell Design Issues

• aspect ratio (height : width) should be relative square

• Row / Column organisation (matrix)
• A_R = log2(R); A_C = log2(C)
• A_R + A_C = N_address_bits
• N = 2N_address_bits = R*C
• number of rows should be power of 2
• number of bits in a row
• sense amplifiers to amplify the voltage from each memory cell
• R -> 2A_R row decoder
• C -> 2A_C column decoder
• implement M of the column decoders (M bits, one per bit)
• M = output word width

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 Array-Structured Memory Architecture
L address bits – K bit column address, L-K bit row address

Problem: ASPECT RATIO or HEIGHT >> WIDTH

2L-K Bit Line

Storage Cell

AK

Row Decoder
AK+1 Word Line

AL-1

M.2K
Sense Amplifiers / Drivers Amplify swing to
rail-to-rail amplitude

A0
Column Decoder Selects appropriate
AK -1 word

Input-Output
(M bits)

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