Digital Implementation of Constant Power Load

(CPL), Active Resistive Load, Constant Current

Load and Combinations
Sameer Arora, Poras T. Balsara and Dinesh K. Bhatia
Department of Electrical Engineering, The University of Texas at Dallas, Richardson, Texas, USA
sameer.arora@utdallas.edu, poras@utdallas.edu, dinesh@utdallas.edu

Abstract—Cascaded converters need to be tightly regulated to In this paper, a digital implementation of various loads and
have better system performance and faster dynamic response. load conditions is proposed, which can be used to emulate
One of the major issues in cascaded converters is that they different loads and loading conditions used to design power
behaves as a constant power load (CPL) when tightly regu-
lated. The current through a CPL decreases/increases with the converters. The paper is organized as follows: In section II, a
increase/decrease of voltage across it, respectively. As a result, review of the constant power load is presented along with the
a CPL has negative incremental impedance, which causes a corresponding linear model. In section III, the proposed digital
destabilizing effect. In order to study the converter’s behavior implementation of a load is presented implementing CPL, ac-
with constant power load, a novel digital implementation of tive resistor, constant current and combinations. Experimental
constant power load is proposed which emulates a DC/DC
converter as a CPL. The digital implementation is controlled results are discussed in section IV. Finally, applications and
by a DSP which has the ability to be configured as a CPL, conclusions are included in section V.
an active resistor load, constant current load or combinations.
II. CPL AND P RIOR W ORK
Further, the load can be dynamically changed.
Index Terms—Digital, Constant Power Load (CPL), Resistive A. Constant Power Loads
load, Constant current, DSP. Constant power load exhibits positive instantaneous
impedance, but, a negative incremental impedance. This
I. I NTRODUCTION means that although the instantaneous impedance (V /I > 0)
of the CPL is positive, the delta change in the impedance
In a distributed multi-converter power architecture, if the (ΔV /ΔI < 0) is negative. This can be explained mathemat-
dynamic response of the fed converter is faster than the ically as follows, for a constant power P , the relationship of
feeding converter then the fed converter acts as a CPL that voltage and current is given as P = V I.
can cause stability issues. However, if the feeding converter is Taylor series expansion for a CPL at an operating point
faster than the load converter, then the feeding converter can I = P/V is given as
compensate for the disturbance. This regulates the input of P P ∂i P P
the load converter, before the feedback of the load converter i= ≈ + v̂ = − 2 v̂ + higher order terms (1)
v V ∂v V V
reacts on the disturbance [1][2]. The phenomenon of CPL
Notation: The signal values are represented by lower case
in a DC/DC converter can also be related to loop gain and
letters (v), steady state values by upper case letter (V ) and
bandwidth. To prevent destabilization behavior, the bandwidth
small signal values by a lower case letter with a hat (v̂).
and loop gain of the feeding converter must be more than the
Linear model of CPL: Consider the graph shown in the Fig.
fed converter [3].
1 for a constant power of 8W . The constant power load can
Another common source of CPL is electric motors which be approximated as a line, such that for the average values P
consume a major portion of the energy produced in developed and V at the operating point, the slope is given by di/dv =
countries. It is estimated that during the 21st century, 90% of −P/V 2 and the y-intercept is given by 2P/V
the electrical energy generated in developed countries would
P P
be processed by power electronics, among which 60% would i = − 2v + 2 (2)
be dedicated to motor drives [6]. When a motor operates in V V
constant power mode, (P = τ ω = const) where τ is the From equation (2), a CPL can be approximated as a negative
torque and ω is the angular momentum, for a DC/AC inverter impedance and a current source, given as follows:
driving the electric motor with tightly regulated speeds, for the V2
RCP L = −
speed-torque having one to one characteristics, constant speed P (3)
leads to constant torque and therefore it acts as a constant P
ICP L =2
power load. V
The dynamic behavior of constant power loads is equivalent From (1)(2), it can be concluded that large signal current
to a dynamic negative resistance destabilizing the DC bus sees a positive impedance, but the small signal current sees
and hence the system. Furthermore, CPLs impact the power a negative impedance. Fig. 2 shows the equivalent schematic
quality and system reliability. [1][2][4][5]. for a constant power load.
978-1-5090-2757-6/16/$31.00 
c 2016 IEEE
 12-bit DAC to set the voltage bias of the current source circuit.
Further, in order to achieve higher power CPL (or high power
resistive load or higher current load), multiple current source
cells can be implemented in parallel as shown in the block
diagram. This might have small variations due to mismatches
of the BJTs and the sense resistors, but this allows a significant
increase in the implementation of a high power CPL. Fig. 4
shows the experimental prototype of the digitally implemented
load using two current source circuits.

Fig. 1: Graph of CPL for P = 8W

Fig. 3: Block Diagram

Fig. 2: Equivalent Schematic for a CPL

B. Prior Work
In [2] the authors have implemented analog CPL (A-CPL)
using a conventional analog current source. The major issues
with A-CPL are that it can implement only one type of
load at a time, either CPL, resistive or constant current load.
Additionally, the current information is set by calibration of
resistors and manual switching between modes to set the bias
of the current source circuit. In most practical scenarios, loads
always exist in combinations, which cannot be implemented
with A-CPL. Further, A-CPL cannot change the load dynam-
ically.
Another work, as in [7] uses the Norton amplifier using
the same current source circuit configuration to implement
a CPL. The work presented shares the same shortcomings
as in [2]. It requires manual configuration and cannot change Fig. 4: Digital Implementation of load
load dynamically. Further, the work in [7] can only implement
A. Implementation of CPL, Resistive, and Constant Current
CPL.
load
Overall, the systems lack flexibility, require greater hard-
ware complexity, the accuracy of the implementation is de- An op-amp connected in negative feedback follows the
pendent on system components (multiplier in [2] and poten- axiom that the amplifier’s high open loop gain ensures that
tiometer in [7]) and requires manual configuration. the voltage difference between input terminals is zero.
Consider the current source circuit shown in Fig. 3. For
III. P ROPOSED D IGITALLY I MPLEMENTED L OAD the implementation of a CPL (P ), sampling the instantaneous
The proposed digital implementation of a load is used to output voltage (V ), the instantaneous current is given by the
implement CPL, resistive load, constant current load or any relationship I = P/V . This current flowing through the sense
combinations of these. The circuit implementation uses the resistor would induce a voltage of (P × Rsense /V ) across
conventional analog current source circuit, where the current it. Therefore, based on the negative feedback property of the
information is calculated using a DSP processor. Fig. 3 shows opamp, the bias voltage is given by, I ∗ = P × Rsense /V .
the overall block diagram for the digital implementation. All The prototype circuit is shown in Fig. 4, where Rsense = 1Ω.
the various type of loads are implemented by changing the bias The proposed device samples at a much faster rate than a
of the current source circuit. The circuit uses the internal 12- DC/DC converter ensuring CPL operation and achieving a
bit ADC to sample the instantaneous voltage and an internal high dynamic response.
 For the implementation of an active resistor (R), the corre-
sponding instantaneous current is calculated using the relation
I = V /R. If this current flows through the sense resistor, the
voltage across Rsense is equal to V × Rsense /R. Therefore,
the bias voltage can be calculated as I ∗ = V × Rsense /R (by
op amp negative feedback).
Furthermore, for the implementation of constant current
load, irrespective of the sampled output voltage (V ), the bias
voltage of the current source circuit is set by I ∗ = I × Rsense
for a given current sink load.
B. Implementation of Combination of loads
The resistive load is a linear element, but for the CPL,
which is a non-linear element, the digital implementation is
based on the linearized model discussed in section II. Since
sampling is done at a high rate, it can be assumed that the CPL Fig. 6: Implementation of CPL for 9 W .
linearized model is applicable. Using the small-signal model,
effective current of the circuit can be calculated with various
combinations of loads. The schematic for the combination of
CPL and a resistive load is shown in Fig. 5.

Fig. 5: Equivalent Schematic for a CPL and Resistor

IV. E XPERIMENTAL R ESULTS

The proposed digital implementation of load given in
Fig. 7: Step change in CPL from 5W to 9W at 0 Ω resistance
Fig. 3 was implemented using the development board with
at 30 V
ARM DSP, STM32F429-discovery. The configurations and
the values were set using the live watch window of IAR IDE.
OP-467 is a high-speed op-amp having a wide bandwidth by
Analog devices. 2SC6144SG is an NPN transistor with a
typical current gain (β) of 335 and power rating of 25W by
On-semi. The sense resistors have 1Ω resistance with a power
rating of 25W . Fig. 4 shows the prototype circuit of the digital
implementation of load using two cell current source.
A. Constant Power Load operation
The plot shown in Fig. 6 is a constant power load for
9W when the dynamic voltage is changed between 18V to Fig. 8: Resistive load implementation R = 50 Ω
32V . The percentage error in the variation of CPL is ≤ 1%.
Further, Fig. 7 shows the behavior of the device for a step resistance from 75Ω to 40Ω load. The high dynamic response
change from 5W to 9W . The steady state value of the CPL is verified, for the step change in active resistance the dynamic
is achieved in less than 2.5μs, validating a high dynamic settling is less than 2.5μs.
response of the circuit. The output current is measured by
the measuring the voltage across the Rsense resistor. For the C. Constant current load operation
prototype implementation the Rsense = 1Ω. Fig. 10 shows measurement results of constant current load
implemented for 120 mA.
B. Resistive load operation
An active resistor of 50Ω was implemented, where the plot D. Combination Load operation
in Fig. 8 shows the corresponding experimental results. The For a combination load implementation, a CPL of 5W in
steady state behavior is evaluated by changing the voltage combination with 1kΩ active resistance was implemented. Fig.
from 11V to 15V . Additionally, Fig. 9 shows a step change in 11 shows how the device behaves as a combination load of
Fig. 9: A step change in resistance 75 Ω to 40 Ω at 14 V
input. Change in dynamic resistance in < 2.5μs

Fig. 12: Mismatch between current through the sense resistor

for the two current source circuits

perform load transient. The high sampling rate ensures faster

response time. Therefore, the digital implementation of a load
behave as a CPL when implemented as load for a DC/DC
converters. For most of the practical scenarios in a distributed
system, loads exist as a combinational load of constant power
load and constant voltage load. The digital implementation of
load offers numerous advantage over the work demonstrated
in [2] and in [7]. The digital implementation offers a much
Fig. 10: Constant current implementation Ic = 120mA
faster dynamic response of < 2.5μs in contrast to < 50μs
in [2]. Further, it has the ability to implement combinational
load, dynamically change load/loading condition, perform
load transients and does not require manual configuration.
This device can be used to test the converter under different
scenarios and can be easily integrated with other digital
or computer instrumentation prevalent in power electronics
testing laboratories these days.
R EFERENCES
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12 shows the mismatch in the current through the sense [6] S. Banerjee and G. Verghese, Nonlinear Phenomena in Power Electron-
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V. A PPLICATIONS AND C ONCLUSIONS
A digitally implemented load is proposed that can be used
as various kinds of load. The device can be used to under-
stand converters under test for various loading conditions and