1318 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO.

4, APRIL 2010

Discontinuous-Conduction Mode DC/DC Converters

Feeding Constant-Power Loads
Amir M. Rahimi, Student Member, IEEE, and Ali Emadi, Senior Member, IEEE

Abstract—One of the major issues in multiconverter power- output filter of power-electronic inverters [15]. In literature
electronic systems, which exist in different land, sea, air, and [16], the implementation of this technique on dc/dc converters
space vehicles, is the stability problem imposed by constant-power was presented, and the technique was used to stabilize the
loads (CPLs). The research work done in this field has been
focused mainly on continuous-conduction mode of operation. In converter loaded by a CPL. Nearly all of the aforementioned
this paper, we study the case when the loaded converter operates in methods and the research that has been done so far on power-
discontinuous-conduction mode (DCM). We prove that the open- electronic converters loaded by CPLs are based on converter
loop dc/dc converters operating in DCM are stable when they are operation in continuous-conduction mode (CCM). This is be-
loaded by CPLs. Furthermore, we present that the problem of cause converters are usually designed to operate in CCM due
feedback design for a converter operating in DCM and loaded
by a CPL can be translated into a conventional feedback-design to better regulation of the output voltage and less inductor-
task for the same converter with a resistive load. Simulation and current ripple for a specific load. In addition, modeling the
experimental results verify the presented discussion. converters is usually more difficult in discontinuous-conduction
Index Terms—Constant-power loads (CPLs), dc distributed mode (DCM) as compared with the CCM operation. Therefore,
power systems, dc/dc converters, discontinuous-conduction mode more research was required to address the problem for DCM-
(DCM), multiconverter power-electronic systems, negative- operated converters and it was the motive for this paper.
impedance instability. In this paper, we will focus on DCM operation of dc/dc
converters loaded by CPLs. Modeling the converters in DCM
I. I NTRODUCTION with resistive load has been reported in the literatures [17]–[20].
A more comprehensive work, which examines and compares
M ULTICONVERTER power-electronic systems exist in
electric, hybrid, and plug-in hybrid land vehicles as well
as other sea, undersea, air, and space vehicles [1], [2]. These
six methods of modeling pulse-width modulated converters
in DCM, has been reported in [21]. In these papers, usu-
systems, which are mainly of dc type, are also referred to ally, state-space averaging, circuit averaging, or average-switch
as dc distributed power systems and their modeling has been method are used to derive the nonlinear equation of the output
addressed in [3]. They consist of different power-electronic voltage when the converter has resistive load. Then, using
converters which connect different buses. Therefore, there are standard linearization techniques, the small-signal control-to-
many converters in these systems, which are effectively loaded output transfer function of the converter is obtained, and the
by other converters. When a converter is tightly regulated, stability of the converter with the resistive load is analyzed
it draws a constant amount of power at its input and acts in s-domain. In [22], average-switch method has been used
like a constant-power load (CPL) for its feeder converter. A to write the converter equations in voltage-mode and current-
CPL exhibits negative incremental resistance, which tends to mode controls. Then, the stability of the open-loop converter
destabilize the feeder system, whether it is an input filter [24] has been investigated in s-domain when it is loaded by a CPL.
or another converter [4]. A large amount of research work In [22], it is concluded that with the voltage-mode control,
has been done to overcome this problem, and many methods the open-loop DCM-operated buck converter is stable with
have been proposed and tested [5]–[12]. Among these methods CPL. While we have used the time-domain analysis, a similar
are feedback linearization [5], synergetic control [9], pulse- conclusion is obtained in Section III of this paper.
adjustment technique [10], phase-plane analysis [11], and ac- A few of the authors have considered the detailed model of
tive damping. Active damping was primarily used to stabilize the converters in DCM, which includes the high-frequency pole
the input filter of ac/dc converters [13], [14] as well as the of the converter [17], [18], [20], [21]. In multiconverter power-
electronic systems, the frequency of oscillations (if they hap-
pen) is usually far below the switching frequencies. Therefore,
Manuscript received February 10, 2009; revised July 21, 2009. First in this paper, the conventional state-space averaging method is
published August 18, 2009; current version published March 10, 2010.
A. M. Rahimi was with the Electric Power and Power Electronics Center, used which ignores the high-frequency pole of the model of the
Department of Electrical and Computer Engineering, Illinois Institute of Tech- converter in DCM. Using the averaging method, the switching
nology, Chicago, IL 60616-3793 USA. He is now with International Rectifier, section of the converter is modeled as a controlled current
Irvine, CA 92618 USA (e-mail: arahimi1@irf.com).
A. Emadi is with the Electric Power and Power Electronics Center, Depart- source. Then, the output-voltage equation of the converter with
ment of Electrical and Computer Engineering, Illinois Institute of Technology, a CPL is obtained, and, using time-domain analysis, it is shown
Chicago, IL 60616-3793 USA (e-mail: emadi@iit.edu). that basic converters loaded by CPLs are stable. Furthermore, it
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. is shown that the design of the feedback loop for the buck and
Digital Object Identifier 10.1109/TIE.2009.2029514 buck–boost converters loaded by CPLs can be translated into a

0278-0046/$26.00 © 2010 IEEE

RAHIMI AND EMADI: DISCONTINUOUS-CONDUCTION MODE DC/DC CONVERTERS FEEDING CONSTANT-POWER LOADS 1319

Fig. 2. Typical inductor current for a dc/dc converter operating in DCM.

stability have been explained in detail in [26]. In converter-level

design, this destabilizing effect is not considered, but in system-
level design, this effect should be taken into account. When
there are several levels of cascaded converters, our approach to
Fig. 1. Cascaded configurations: (a) composed of several levels of converters stabilize the system is to stabilize each converter with its load
and (b) composed of two converters and an input filter.
at each level. Therefore, for the example shown in Fig. 1(a),
conventional feedback-design task for the same converter with converter #2 should be stabilized when loaded by a level-1
resistive load. load, . . ., and converter #(N + 1) should be stabilized by the
This paper is organized as follows. In Section II, a short level-N load, which has already been stabilized. In a cascaded
discussion on the CPLs and their destabilizing effect is pre- chain, if there is an input filter between the converters, the filter
sented. In Section III, it is shown that the buck converter in itself is considered a level. Therefore, for the example shown in
DCM loaded by a CPL is stable. Next, in Sections IV and Fig. 1(b), the LC filter should be stabilized with a level-1 load
V, similar discussion on buck–boost and boost converters is before the stability of converter #2 is investigated with a level-2
presented. In Section VI, the feedback-loop design problem load. For such a filter, the inductor is usually designed to operate
for dc/dc converters operating in DCM and loaded by CPLs in CCM. Therefore, the methods used to stabilize the input
is discussed. Afterward, in Section VII, experimental results, filter of closed-loop converters, like the methods discussed in
which verify the validity of the discussions, are presented. [12] and [23]–[26], can be used to make this filter stable. If the
Finally, the concluding remarks end this paper in Section VIII. inductor of this filter is operating in DCM, which might happen
when the inductor is the stray inductance of the wires, just like
the case of the buck converter operating in DCM, the filter will
II. CPL S be stable (refer to Section III). Moreover, if the stray inductance
In multiconverter power-electronic systems, different buses of the wires is negligible and the load converter has an input
have been connected by dc/dc converters. Therefore, there capacitor, it is added to the output capacitor of the feeder
might be several converters connected in cascade, as shown converter when the stability of the feeder converter is analyzed.
in Fig. 1(a). In a cascaded configuration, when the load con- In this paper, with respect to the aforementioned explanation,
verter tightly regulates its output voltage, assuming its load is without losing the generality of the discussion, we investigate
constant, the power which is delivered to its output becomes the stability of a cascaded system composed of two converters.
constant. Therefore, assuming a constant efficiency for the So far, the methods introduced to mitigate the destabilizing
load converter, it would sink a constant power from the feeder effect of CPLs have used the same simplified topology [5]–[12].
converter. Hence, the relationship of the voltage and current of In addition, they have assumed that the feeder converter oper-
such a load, which is called CPL, is expressed as follows: ates in CCM. However, in the next sections, we show that the
CPLs cannot destabilize a feeder converter which is operating
P
i= . (1) in DCM.
v
Equation (1) is based on the assumption of ideal CPL behav- III. B UCK C ONVERTER IN DCM W ITH CPL
ior which, as far as stability is concerned, is the worst case
Consider a buck converter operating in DCM with typical
assumption [24], [26]. The incremental resistance of a CPL
inductor current as shown in Fig. 2. In each cycle, the inductor
can be obtained by differentiating (1) with respect to the volt-
current starts from zero and, before the end of the cycle (at t2 in
age, i.e.,
Fig. 2), it returns to zero. Therefore, the oscillation between
 −1 L and C can be in progress for a time span equal to t2 ,
∂i V2
RCPL = RInc. = =− . (2) which is much lesser than the period of oscillation of the LC
∂v P
filter. At the beginning of the next cycle, everything starts from
The negative incremental resistance calculated in (2) can make the beginning without any effect remaining from the previous
the damping of the output LC filter of the feeder converter neg- cycle. That is, in each cycle, the inductor current has no memory
ative. In this case, this LC filter behavior becomes oscillatory, of the previous cycles. Hence, no oscillation is formed and no
and, therefore, the feeder converter and the cascaded system oscillation is seen at the output capacitor voltage and inductor
become unstable. This characteristic and the mechanism of in- current.
1320 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 4, APRIL 2010

TABLE I (2) is RCPL ∼ = −(182 /20) ∼ = −16 Ω, but, as was predicted, the
S PECIFICATION OF THE S IMULATED B UCK C ONVERTER
circuit is nonoscillatory and stable.
Before proceeding to analytically prove the aforementioned
discussion, it is required to calculate the amounts of CPL and
the constant-current load that make a buck converter operate
in critically DCM (CDCM). Suppose a load equal to PCPL
takes the buck converter to CDCM. Then, the inductor-current
waveform would be equal to that shown in Fig. 2, except that t2
and T overlap. We have
V in − V out V in − d · V in
IP = ·d·T = ·d·T
L L
V in · d · T
= · (1 − d) (3)
L
IP PCPL
Io = = (4)
2 V out
where IP is the peak inductor current shown in Fig. 2. From (3)
Fig. 3. Typical response of a buck converter in DCM mode to input- and load- and (4), the minimum CPL that takes the converter into CCM
step changes. is calculated as follows:

V in2 · d2 · T
PCPL (CDCM) = (1 − d). (5)
2·L
In addition, with respect to (3), the minimum constant-
current load that takes the converter into CCM can be calculated
as follows:
IP V in · d · T
IConst. (CDCM) = Io = = · (1 − d). (6)
2 2·L
Now, consider a buck converter operating in DCM with the
current waveform shown in Fig. 2. In each switching cycle,
the amount of energy delivered to the output capacitor consists
of two parts. The amount of energy delivered to the output
Fig. 4. Typical response of a buck converter in DCM loaded by a CPL to capacitor during the time that the switch is on is given by
input- and load-step changes.
d·T d·T
V in − V out
The statement mentioned before is verified by simulating a W1 = iL · V out dt = t · V out dt
L
typical buck converter, whose parameter values are given in 0 0
Table I. At t1 = 10 ms, a 1-V input-voltage step has been V in − V out
applied, and, at t2 = 30 ms, the load has been changed to = · (d · T )2 · V out. (7)
2L
75 Ω. The resulting output waveform is shown in Fig. 3. No
oscillation is observed, and, in fact, the response of the output The amount of energy delivered to the output capacitor, when
voltage looks like the response of a first-order system. The the diode is on, is given by
circuit has been in DCM operation throughout the transitions.  2
The intuitive result of the previous discussion is that, in 1 1 V in − V out
W2 = L · IP = L2
·d·T
DCM, the output filter of an open-loop converter cannot os- 2 2 L
cillate. Therefore, we expect that, when a converter in DCM is 1
loaded by a CPL, the negative equivalent resistance of the CPL = (V in − V out)2 · (d · T )2 . (8)
2L
has no effect on the LC filter and cannot make it oscillatory and
unstable. To verify this hypothesis, a simulation was conducted Therefore, the average power delivered to the output at each
using the buck converter defined by Table I. The converter switching cycle is given by
was loaded with a pure CPL of 20 W, and the circuit was W1 + W 2 1
simulated with fSW = 12.5 kHz to make sure that the converter PBuck = = · d2 · T · (V in − V out) · V in. (9)
T 2L
remains in DCM. At t1 = 10 ms, a 1-V input-voltage step was
applied, and, at t2 = 30 ms, a resistive load of 300 Ω was Using (9), the converter can be modeled as a controlled current
added to the output. The output voltage is shown in Fig. 4. The source. With a CPL at the output, the equivalent circuit is shown
equivalent resistance of the CPL at this output voltage given by in Fig. 5.
RAHIMI AND EMADI: DISCONTINUOUS-CONDUCTION MODE DC/DC CONVERTERS FEEDING CONSTANT-POWER LOADS 1321

Fig. 5. Model of the buck converter in DCM loaded by a CPL.

Using (9) and the model shown in Fig. 5, the equation of the
output voltage of the converter is obtained, i.e.,
Fig. 6. Chart describing the behavior of (21).
iBuck = iC + iCPL (10)
  Therefore
d2 · T V in PCPL dvout  
· V in · −1 = +C (11) d ·T
2
V in PCPL dvout vout
2L vout vout dt · V in · −1 = +C + .
 2  2L vout vout dt R
d ·T 1 d2 · T dvout (19)
· V in2 − PCPL · − · V in = C .
2L vout 2L dt
Equation (19) can be written as follows:
(12)  2 
d ·T 1 d2 · T vout dvout
·V in −PCPL ·
2
− ·V in− =C .
We define “a” and “b” as follows: 2L vout 2L R dt
(20)
d2 · T
a= · V in2 − PCPL (13)
2L If “a” and “b” are defined as in (13) and (14), with the
d ·T
2 assumption made in (15), “a” and “b” are positive, and (20)
b= · V in. (14) can be written as
2L
a vout dvout
Since DCM operation is assumed, with respect to (5), we have − −b=C (21)
vout R dt
d ·T
2
PCPL < · V in2 . (15) or equivalently,
2L
Considering (15), “a” is always positive. “b” is also positive −vout
2
− b · R · vout + a · R dvout
=C . (22)
by definition. Therefore, (12) can be written as follows: R · vout dt

a dvout The roots of the numerator of the right-hand-side fraction are

−b=C , where a, b > 0. (16) given by
vout dt
√
If for a given set of the parameter values, CPL and initial b · R + b2 · R 2 + 4 · a · R
V1 = <0
output voltage vout (0) > a/b, the left-hand side of (16) will −2
be negative. Therefore, dvout /dt will be negative. Hence, by √
b · R − b2 · R 2 + 4 · a · R
the passing of time, vout will decrease and approach a/b. V2 = > 0. (23)
−2
However, it will never pass a/b because, at the moment when
vout = (a/b), the right-hand side of (16) becomes zero, and, Therefore, the behavior of the differential equation given by
therefore, vout will not change any more. On the other hand, (21) can be interpreted by the chart shown in Fig. 6. This
if for a given set of parameters and initial conditions 0 < chart shows that no matter what the initial output voltage is,
vout (0) < a/b, the left-hand side of (16) becomes positive, and, it asymptotically approaches the final value of V2 . Hence, the
therefore, dvout /dt will be positive. Hence, vout will increase system is stable.
and approach a/b; however, by the same argument, it will never It can be shown that as R approaches infinity, V2 , given by
pass a/b. Therefore, it is concluded that, provided the condition (23), approaches V out(∞), given by (17), i.e.,
given in (15) is satisfied and the converter stays in DCM, the   2
output voltage will be stable and nonoscillatory because, for R→∞ b2 · R2 + 4 · a · R + 2 ab − b · R
any given initial output voltage, it will asymptotically increase V2 ∼=
2
or decrease toward the final value of a/b given by  2
b · R + 2 ab − b · R
d2 ·T
a · V in2 − PCPL 2L · PCPL =
vout (∞) = = 2L
= V in − . 2
b d2 ·T
· V in d2 · T · V in  
2L
(17) b · R + 2b − b · R
a
a
= = (24)
2 b
In case the load is not purely CPL and there is a resistive
load, the output-voltage equation is where “a” and “b” are defined by (13) and (14).
To check the model of the buck converter in DCM given
iBuck = iC + iCPL + iR . (18) by (9), a computer simulation has been performed. For this
1322 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 4, APRIL 2010

Fig. 9. Model of the buck–boost converter in DCM, loaded by a CPL and a

resistive load.

cycle, which is equal to the average diode current, can be

expressed as follows:
IP V in · T
Io = ID = (1 − d) = · d · (1 − d). (27)
2 2L
On the other hand, with a pure CPL as the load, the output
current can be written as follows:
PCPL PCPL
Fig. 7. Output-voltage waveforms obtained from simulation of the buck Io = = . (28)
converter and the buck converter model given by (9) with parameter values V out V in · 1−d
d
given in Table I.
From (27) and (28), the CPL, which takes the converter to
CDCM, is calculated, i.e.,
1
PCPL (CDCM) = · V in2 · d2 · T. (29)
2L
The previous value is exactly equal to the power which the buck–
Fig. 8. Buck–boost converter. boost converter delivers to the output in DCM. Therefore, to
simulation, the same parameter values which resulted in the keep the converter in DCM, the following inequality must hold:
waveform shown in Fig. 4 were used. That is, the model of 1
PCPL < · V in2 · d2 · T. (30)
the buck converter, shown in Fig. 5, has been loaded by a 2L
20-W CPL and input- and load-step changes have been applied However, if the load is a pure CPL, with the aforementioned
at t1 = 10 ms and t2 = 30 ms, respectively. The resulting assumption, the output capacitor will continuously be charged,
output-voltage waveform along with the waveform shown in and the output voltage will grow to infinity. Hence, to have a
Fig. 4 is shown in Fig. 7. limited final output voltage, an arbitrary resistive load is re-
The waveforms are very similar except that the waveform quired as well. Now, we show that with these two assumptions,
obtained from simulating the model does not have switching the buck–boost converter with the CPL will be stable. The
ripple, and the dc value of the waveform resulting from the buck–boost converter in DCM can be modeled as a controlled
circuit simulation is a little lower due to the voltage drops across current source. The current of this current source is equal to
the switches. the converter power given by (26) divided by the output voltage
as shown in Fig. 9. The equation of the output voltage in this
IV. B UCK –B OOST C ONVERTER IN DCM W ITH CPL situation is given by
Our approach for the buck–boost converter in DCM loaded V in2 · d2 · T dvout PCPL vout
=C + + . (31)
by a CPL is similar to that of the buck converter. We show that 2L · vout dt vout R
this converter is also stable when loaded by a CPL provided
In steady state, the previous equation can be written as
that there is an arbitrary amount of resistive load. Fig. 8 shows
a buck–boost converter. If the converter operates in DCM, the V in2 · d2 · T v2
− PCPL = out . (32)
inductor current will be as shown in Fig. 2. 2L R
In DCM, the energy transferred to the output in each cycle is
Equation (32) means that the power required by the CPL is
equal to
subtracted from the power which the converter delivers, and
 2 the excess power gives rise to the output voltage to a point
1 1 V in 1
W = L · IP = L
2
·d·T = V in2 · (d · T )2 . where the resistor power becomes equal to the surplus power.
2 2 L 2L
(25) Assuming the converter is stable, the final output voltage in
steady state can be calculated from (32) as follows:
Therefore, the power of the converter, which is averaged   
throughout one cycle, is V in2 · d2 · T
V out(∞) = R · − PCPL . (33)
1 2L
P = V in2 · d2 · T. (26)
2L To prove the stability, (31) is written as
Now, the minimum CPL which takes the converter to the V in2 ·d2 ·T
boundary of CCM operation is calculated. In the boundary R· 2L − PCPL − vout
2
dvout
=C . (34)
condition, the average output current of the converter in each R · vout dt
RAHIMI AND EMADI: DISCONTINUOUS-CONDUCTION MODE DC/DC CONVERTERS FEEDING CONSTANT-POWER LOADS 1323

Fig. 12. Model of the boost converter in DCM loaded by a CPL.

After doing mathematical calculations and simplification,

(36) can be written as
Fig. 10. Chart describing the behavior of (33). V out · (V in · d · T )2
W = . (37)
2L · (V out − V in)
Hence, the power of the DCM-operated boost converter aver-
aged over one cycle can be expressed as follows:
W V out · V in2 · d2 · T
PBoost = = . (38)
Fig. 11. Boost converter. T 2L · (V out − V in)
The zeros of the numerator in the right-hand side of (34) To continue the discussion, the minimum CPL which takes
are ±V out(∞). Therefore, the behavior of the differential the converter to the border of DCM must be calculated. If
equation given by (34) can be interpreted by the chart shown in the converter operates in CDCM, the average converter output
Fig. 10. current can be expressed as follows:
Similar to the discussion presented for the buck converter,
the chart shown in Fig. 10 shows that if the initial capacitor IP · (1 − d) PCPL PCPL
Io = ID (ave.) = = = V in . (39)
voltage (V out(0)) is less than V out(∞) given by (33), the 2 V out 1−d
output voltage will rise toward V out(∞), and, if V out(0) >
V out(∞), the output voltage will fall and approach V out(∞). Therefore, the CPL which takes the converter into CDCM
However, vout (t) never passes this final value because, at the operation is
moment when vout (t) = V out(∞), the rate of change of the V in2 · d · T
output voltage becomes zero (dvout /dt = 0), and vout remains PCPL (CDCM) = . (40)
2L
unchanged. This means that the output voltage of an open-
loop buck–boost converter in a DCM loaded by a parallel Consider a boost converter in DCM loaded by a CPL; using
combination of a CPL and an arbitrary resistor asymptotically (38), the converter can be modeled as a controlled current
approaches the final value given by (33). Therefore, the con- source as shown in Fig. 12.
verter is nonoscillatory and stable. Using Fig. 12, the equation of the output voltage of the
converter can be written as

V. B OOST C ONVERTER IN DCM W ITH CPL V in2 · d2 · T dvout PCPL

=C + . (41)
2L · (vout − V in) dt vout
In this section, we present that the open-loop boost converter
in DCM loaded by a CPL is nonoscillatory and stable. The Assuming that the system is stable, the final output voltage in
schematic of a boost converter is shown in Fig. 11. steady state can be calculated as
In DCM, the current of the inductor is as shown in Fig. 2.
The time t2 can be calculated as follows: 2L · PCPL · V in
V out(∞) = . (42)
2L · PCPL − V in2 · d2 · T
V out − V in V in
IP = (t2 − d · T ) IP = d·T In (42), in order to have a positive final voltage, the denominator
L L
V in · d · T should be positive, which gives us another restriction for the
⇒ t2 = + d · T. (35) amount of CPL, i.e.,
V out − V in
If the time origin is moved to the point t1 = d · T , the energy V in2 · d2 · T
PCPL > . (43)
transferred to the output in each cycle can be calculated as 2L
follows: The inequality given by (43) could be predicted from the
t2
−d·T output-power expression of the boost converter in DCM. If the
load of the boost converter is very light, the output voltage will
W= iL · V out dt
grow much greater than the input voltage. In this condition,
0 the power of the converter, which is given in (38), can be
V in·d·T

V out−V in   approximated by
V in V out − V in
= V out · d·T− t dt. (36) V in2 · d2 · T
L L V out  V in ⇒ PBoost ∼
= . (44)
0 2L
1324 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 4, APRIL 2010

In this case that the power of the boost converter is independent

of the output voltage, if the amount of the CPL is less than the
amount given by (44), the output voltage will grow infinitely. If
there is a resistive load parallel with the CPL, the case becomes
similar to the case of the buck–boost converter, which was
discussed in Section IV, and there will be a bounded final output Fig. 13. Equivalent buck converter in DCM with output-voltage equation
voltage. given by (53).
In addition, it can be shown that the final voltage calculated
in (42) is greater than V in since, if we assume that it is less than VI. F EEDBACK -L OOP D ESIGN
V in, we reach an impossible inequality A. Buck Converter

V out(∞) ≤ V in As stated earlier, the equation for the output voltage of the
buck converter in DCM loaded by a CPL is given by (12). This
⇒ 2L · PCPL · V in ≤ 2L · PCPL · V in − V in3 · d2 · T equation can be rewritten as follows:
 
d2 · T PCPL · 2L
⇒ 0 ≤ −V in3 · d2 · T. (45) · V in2 −
2L d2 · T

To evaluate the stability of the circuit shown in Fig. 12, (41) is 1 d2 · T dvout
· − · V in = C . (50)
written as follows: vout 2L dt

V in2 · d2 · T PCPL dvout We define a new parameter V in1 as follows:

− =C
2L · (vout − V in) vout dt PCPL · 2L
V in21 = V in2 − . (51)
d2 · T
vout · (V in2 · d2 · T − 2L · PCPL ) + 2L · V in · PCPL
⇒ If (15) is satisfied, then V in1 defined previously will be positive
2L · vout · (vout − V in) and real, and (50) can be written as follows:
dvout d2 · T 1 d2 · T
=C . (46) · V in21 · −
dt 2L vout 2L
Therefore, dvout
· (V in + V in1 − V in1 ) = C . (52)
dt
vout − 2L·V in·PCPL
2L·PCPL −V in2 ·d2 ·T dvout Equation (52) can be written as
2L·vout ·(vout −V in)
= −C . (47)
dt
2L·PCPL −V in2 ·d2 ·T d2 · T 1 d2 · T
· V in21 · − · V in1
2L vout 2L
We define
d2 · T dvout
2L · vout · (vout − V in) = · (V in − V in1 ) + C . (53)
K1 = . (48) 2L dt
2L · PCPL − V in2 · d2 · T
The previous equation is the output-voltage equation of the
With respect to (43) and since the output voltage is always same converter with the same output voltage and operating with
greater than the input voltage, K1 is always positive. There- the same duty cycle but with an input voltage reduced to V in1 .
fore, with respect to (42) and (48), (47) can be written as Furthermore, instead of the CPL, there is a constant-current
follows: load given by (54) at the output, and the equivalent circuit is
shown in Fig. 13.
vout − V out(∞) dvout d2 · T
= −C . (49) ILoad = · (V in − V in1 ). (54)
K1 > 0 dt 2L
Therefore, if the initial value of the output voltage is greater Therefore, the problem of the feedback-loop design of the
than V out(∞), dvout /dt will be negative, and vout will de- converter with a CPL and input voltage of V in is translated
crease and approach V out(∞). Likewise, if the initial output into the design of the feedback for the same converter with
voltage is less than V out(∞), dvout /dt will be positive, and reduced input voltage and a constant-current source as the load.
vout will increase and approach V out(∞). Changing in either This is a conventional feedback-design task for a buck converter
direction, the output voltage will never pass V out(∞) because, operating in DCM.
if it reaches V out(∞), dvout /dt becomes zero, and the output It is essential to be shown that if the original converter with
voltage remains unchanged. Therefore, the output voltage of an CPL is operating in DCM, the converter with modified input
open-loop boost converter in DCM with CPL asymptotically voltage and load will be in DCM, too. In order to achieve this,
approaches the final value given by (42), and is not oscillatory we present that even if the converter operates in CDCM, the
or unstable. converter with modified input voltage will operate in DCM. In
RAHIMI AND EMADI: DISCONTINUOUS-CONDUCTION MODE DC/DC CONVERTERS FEEDING CONSTANT-POWER LOADS 1325

Fig. 14. Response of the DCM-operated buck converter with CPL and the
equivalent converter with conventional load to load-step changes. Fig. 15. Controller designed for the DCM-operated buck converter.

order to do so, the PCPL from (5) is substituted into (51) to

calculate V in in terms of V in1 , i.e.,
1
V in = √ · V in1 . (55)
d
Now, (54) can be rewritten as
V in1 · d · T √
ILoad = · ( d − d) (56)
2·L
where V in1 is defined by (51). However, according to (6), the
minimum required current which takes the converter shown in
Fig. 13 into CCM is equal to
Fig. 16. Response of the DCM-operated buck converter in the example with
V in1 · d · T the designed controller to load and input steps.
IConst. = · (1 − d). (57)
2·L A simple controller in the form of an integrator plus a lead
The value in (57) is greater than the value given by (56); compensator can be used. We have used the controller shown in
therefore, the converter shown in Fig. 13 will remain in DCM. Fig. 15, which has the following transfer function:
As an example, consider the buck converter with parameters ve 485 · (1 + s/256.4)
given in Table I is operating with d = 0.5 and fsw = 12.5 kHz. (s) ≈ . (59)
vout s
Operating with this low frequency guarantees the converter
operation in DCM. Assume that a CPL of 20 W is applied to With this controller, assuming the amplitude of the triangular
the output of the converter. If the converter operates in CCM, signal in the modulator is unity, the loop will have a crossover
it becomes unstable because, considering (2), the equivalent frequency of about 0.5 kHz. Now, this controller, which was
negative impedance of the load is much lesser than 100 Ω in designed using the equivalent converter, is used for the original
value. According to (53), the equivalent converter has an input buck converter with CPL. The response of the closed-loop
voltage of 21.6 V [refer to (51)] with a 100-Ω resistive load converter to input- and load-step changes, which has been
in parallel with a 0.44-A current source. Fig. 14 shows the obtained by PSpice simulation, is shown in Fig. 16. The 0.2-A
response of the open-loop operated converter and the equivalent load step has been applied at 5 ms, and the −1-V input step
converter to a 0.2-A load step. The responses are very similar, has been applied at 25 ms. The converter has been in DCM
which is expected, except that the equivalent converter shows operation throughout the entire simulation time.
less switching ripple in its output voltage. The reason is that
the input voltage has been reduced, while the duty cycle is the
B. Buck–Boost Converter
same. Since it has a similar dynamic response, the controller is
designed for the equivalent converter which has a conventional The equation describing the output voltage of the buck–boost
load. For simplicity, assume that the output voltage should be converter in DCM with a load composed of a CPL parallel with
regulated at 16 V. Therefore, the average duty cycle will be 0.5. a resistive load is given by (31). This equation can be rewritten
For small perturbation around the operating point, the current as follows:
source has no effect on the dynamic response, and the converter  
d2 · T 2L · PCPL 1 dvout vout
with the resistive load, which operates in DCM, can be modeled V in −
2
· =C + .
by a first-order system [22]. Neglecting the high-frequency 2L d2 · T vout dt R
(60)
pole, the control-to-output transfer function of the equivalent
converter is We define a new parameter V in1 as follows:
vout 5.85 PCPL · 2L
(s) = . (58) V in21 = V in2 − . (61)
d 1 + s/258 d2 · T
1326 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 4, APRIL 2010

TABLE II was gradually increased until it made the system oscillatory

S PECIFICATION OF THE C OMPONENTS U SED FOR I MPLEMENTATION
OF THE B UCK C ONVERTER IN THE E XPERIMENT
at about 7.0 W. At this time, the output voltage was 6.43 V,
the switching frequency was 20 kHz, and the converter was
operating in CCM.
In CCM, using the averaging method [28], the equations of a
buck converter loaded by a CPL in parallel with a resistive load
can be written as follows:
L didtL = d · V in − vo − iL · RL
(63)
C dvdt = iL − R1
o vo

where R1 = RLoad RCPL and RCPL is defined by (2). Hence,

Considering (30), V in1 defined previously is real and positive,
the transfer function is
and (60) can be written as follows:
1
d2 · T 1 dvout vout vo (s) = d(s) · V in · .
V in21 · =C + . (62) LC · s + R1 + RL C · s + 1 + R
2 L
R1
L
2L vout dt R
(64)
Equation (62) is the output-voltage equation of the same con-
verter with the same parameters, duty cycle, and output voltage Using (64), the poles of the system are calculated and given by
but with a reduced input voltage. Moreover, the load of this (65), shown at the bottom of the page.
converter is only the resistive portion of the load of the previous In brief, to have a stable CCM-operated buck converter, the
converter. Therefore, the problem of the feedback design in real part of the poles should be negative, which impose the
translated into a conventional problem of feedback design for a stability condition
buck–boost converter in DCM. We need to show that the latter L
< RL · C, R1 = RCPL ||RLoad . (66)
converter is also operating in DCM. This is straightforward |R1 |
since the duty cycle is the same, and the input voltage has been
More discussion about the stability of CCM-operated con-
reduced; the IP shown in Fig. 2 is reduced. However, the output
verters loaded by CPLs can be found in [26].
voltage is the same. Therefore, the slope of the falling inductor
For the experiment previously discussed, since the OSCON
current, when diode conducts, remains the same. Hence, the
capacitors have very low equivalent series resistance (and
inductor current reaches zero even faster than the previous case,
RLoad ≈ ∞), all of the damping resistances can be modeled
and the new converter stays in DCM.
by an equivalent inductor resistance. Moreover, since the mini-
mum power that makes the system oscillatory has been applied,
VII. E XPERIMENTAL V ERIFICATION using (66), the equivalent inductor resistance can be calcu-
To conduct the experiments, a CPL was required. There lated as
were two options. The first option was to implement a tightly (6.43 V)2
regulated closed-loop converter, and the second choice was to RCPL = − = −5.89 Ω (67)
7.0 W
utilize electronic components to make a circuit which exhibits L
RL (Eq.) = = 224 mΩ. (68)
CPL characteristics. For this latter implementation, the idea C · |RCPL |
presented in [27] was used, and an analog CPL (A-CPL) was
implemented. The comparison of this A-CPL with an imple- Considering the resistance of the wirings, the switches, and the
mented closed-loop converter has been presented in [16]. The source, the value given in (68) is reasonable. The amount of
results of this comparison show that the A-CPL resembles an CPL was increased to 10.5 W, and, while the duty cycle was
ideal CPL much better than a typical closed-loop converter. constant, the switching frequency was reduced. Meanwhile,
Therefore, this A-CPL has been used to get the experimental the output voltage was captured at a few different switching
results presented in this section. frequencies. The resulting waveforms are shown in Fig. 17(a).
In Fig. 17(a), it can be noticed that, at fSW = 20 kHz and
fSW = 6.5 kHz, the converter is unstable because it is oper-
A. Open-Loop Buck Converter in DCM Loaded by CPL
ating in CCM. As the frequency is decreased, the switching
An open-loop buck converter with the parameters given in ripple is increased. At fSW = 4.45 kHz, the system is oper-
Table II was implemented. The input was connected to a 24-V ating at CDCM, and the LC oscillations have vanished and
NiMH battery with internal resistance of less than 100 mΩ, and the only ripple at the output voltage is the switching ripple.
the output was connected to the A-CPL. The amount of the CPL As the frequency is decreased further down to 3.8 kHz, the

2
− L
R1 + RL · C ± L
R1 + RL · C −4·L·C · 1+ RL
R1
p1 , p2 = (65)
2·L·C
RAHIMI AND EMADI: DISCONTINUOUS-CONDUCTION MODE DC/DC CONVERTERS FEEDING CONSTANT-POWER LOADS 1327

Fig. 18. Response of a DCM-operated open-loop buck converter to an input

voltage step when it is loaded by a pure CPL.

TABLE III
S PECIFICATION OF THE C OMPONENTS U SED FOR I MPLEMENTATION
OF THE B OOST C ONVERTER IN THE E XPERIMENT

Fig. 17. Output voltage of the open-loop buck converter loaded by a pure
10.5-W CPL at different switching frequencies. (a) Experimental results.
(b) Simulation results.

system remains stable (nonoscillatory). The voltage rise in the battery. The A-CPL is used as the load. An amount of CPL
DCM because of the frequency decrease can be predicted by is chosen to result in an oscillatory CCM-operated converter.
(17). In addition, to compare the experimental and simulation Afterward, while the duty cycle and the load are held constant,
results, a PSpice simulation was performed on a buck converter the switching frequency is decreased until the system reaches
with the parameters given in Table II. The resulting waveforms the CDCM operation. At this moment, the LC oscillations
are shown in Fig. 17(b), which are very comparable with the vanish, and the only ripple at the output voltage of the converter
experimental results. The frequency that the converter enters is the switching ripple. If the frequency is decreased further,
CDCM can be calculated by (5), which is about 5.16 kHz. This the system enters the DCM and remains stable. The results are
is slightly different in the experimental results. The reason is shown in Fig. 19.
that the inductor value was assumed to be constant, whereas it
slightly changes with frequency and the inductor current. VIII. C ONCLUSION
In another experiment, the buck converter in DCM has been
loaded by a pure 7.4-W CPL. With this CPL, the converter In this paper, the operation and stability of basic dc/dc
would have been unstable if it was operating in CCM. An input converters in DCM loaded by CPLs have been investigated.
step voltage was applied and the output voltage was observed. Time-domain models of the converters in DCM, which, in each
The resulting waveform, which is shown in Fig. 18, is compa- case, is a controlled current source, were extracted. Using time-
rable with the waveforms shown in Figs. 3 and 4. It confirms domain analysis, it was shown that the open-loop buck and
that the response of the DCM-operated buck converter with boost converters in DCM are stable when they are loaded by
CPL is like the response of a first-order system as discussed CPLs. The buck–boost converter is also stable provided that
in Section III. there is an arbitrary resistive load parallel with the CPL. Inves-
tigating the problem reveals that there are two reasons for the
stability of the mentioned converters with CPLs. First, in each
B. Open-Loop Boost Converter in DCM Loaded by CPL
switching cycle, the inductor current does not have any memory
An open-loop boost converter with the parameters given in of the past cycles, and, therefore, the output LC filter cannot
Table III was implemented. The input voltage is provided by become oscillatory. Second, as a result of a disturbance, if the
a one-cell Li-ion battery in parallel with a laboratory power output voltage of the converter is changed in one direction,
supply to prevent the long-term voltage drop due to discharging the average converter power in each cycle either changes in
1328 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 4, APRIL 2010

[6] R. Zhang, F. C. Lee, D. Boroyevich, and M. Hengchun, “New high power,

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RAHIMI AND EMADI: DISCONTINUOUS-CONDUCTION MODE DC/DC CONVERTERS FEEDING CONSTANT-POWER LOADS 1329

Amir M. Rahimi (S’05) received the B.S. and Ali Emadi (S’98–M’00–SM’03) received the B.S.
M.S. degrees in electrical engineering from Sharif and M.S. degrees (with highest distinction) in
University of Technology, Tehran, Iran, in 1999 and electrical engineering from Sharif University of
2001, respectively, and the Ph.D. degree in electrical Technology, Tehran, Iran, and the Ph.D. degree in
engineering from Illinois Institute of Technology, electrical engineering from Texas A&M University,
Chicago, in 2008. College Station.
From 2002 to 2005, he was a Research Engineer He is currently with Illinois Institute of Tech-
with Niroo Research Institute, Tehran, Iran. From nology, Chicago, where he is the Harris Perlstein
2007 to 2008, he was a Coop System Engineer with Endowed Chair Professor of Engineering and the
Volterra Semiconductor Corporation, Fremont, CA. Director of the Electric Power and Power Electronics
Since 2009, he has been with International Rectifier, Center and Grainger Laboratories. He is also the
Irvine, CA. His major research interests include dc/dc power electronic con- Founder, President, and Chief Technology Officer of Hybrid Electric Vehicle
verters and IC design for power management. Technologies, Inc., Chicago—a university spin-off company of Illinois Institute
of Technology. He is the author/co-author of over 250 papers as well as several
books, including Vehicular Electric Power Systems (Marcel Dekker, 2003) and
Modern Electric, Hybrid Electric, and Fuel Cell Vehicles (CRC Press, 2009).
He is also the Editor of the Handbook of Automotive Power Electronics and
Motor Drives (Marcel Dekker, 2005).
Dr. Emadi was an Associate Editor of the IEEE T RANSACTIONS ON
I NDUSTRIAL E LECTRONICS and IEEE T RANSACTIONS ON V EHICULAR
T ECHNOLOGY. He was the General Chair of the 2005 IEEE Vehicle Power
and Propulsion and SAE Future Transportation Technology Joint Conference.
He was named the Eta Kappa Nu Outstanding Young Electrical Engineer of
the Year 2003 by virtue of his outstanding contributions to hybrid-electric
vehicles. He was the recipient of the 2005 Richard M. Bass Outstanding Young
Power Electronics Engineer Award and the 2004 Sigma Xi/IIT Award for
Excellence in University Research. He directed a team of students to design
and build a novel motor drive, which won the First Place Overall Award of
the 2003 IEEE/DOE/DOD International Future Energy Challenge for Motor
Competition.