®

RT6936

PMIC for TFT-LCD TV Panels

General Description Features
The RT6936 offers a compact power supply solution to  9.5V to 14.7V Input Supply Voltage
provide all voltages required by a TFT-LCD panel. With its  0.5A to 2.25A Boost Converter for VON with 15V to
high current capabilities, the device is ideal for large screen 45V Programmable Output and OCP
monitor panels and LCD TV applications with 12V supply  2A Inverting Buck-Boost Converter for VOFF with
voltage. The RT6936 is available in the WQFN-40L 6x6 −5V to −27V Programmable Output
package.  0.1A Negative OP for VSS Regulator with −4V to
−25V Programmable Output
 Switching Frequency Selectable for VON and VOFF
Ordering Information
 VON/VOFF/VSS have Temperature Compensation
RT6936
Package Type Function
QW : WQFN-40L 6x6 (W-Type)  VOFF ΔV Function
(Exposed Pad-Option 1)  Fault Analysis and Monitor Function
Lead Plating System  4-CH Scan Driver
G : Green (Halogen Free and Pb Free)  ASG Error Detect Function
Note :  4-Bit Programmable ASG Error with EEPROM
Richtek products are :  Programmable Sequencing
 RoHS compliant and compatible with the current require-  Over-Temperature Protection
ments of IPC/JEDEC J-STD-020.  I2C-Compatible Interface for Register Control
 Suitable for use in SnPb or Pb-free soldering processes.  Thin 40-Lead WQFN Package
 RoHS Compliant and Halogen Free

Pin Configuration
Applications
(TOP VIEW)
 TFT-LCD TV Panel
SEQ_OUT

LXP/CSP
GATEP
FAULT

PGND
TRDY

NTC2

VON
NTC

Marking Information
VL

40 39 38 37 36 35 34 33 32 31
RT6936GQW : Product Number
BANK_SEL 1 30 CKVB4
SDA 2 29 CKVCS4
RT6936 YMDNN : Date Code
SCL 3 28 CKV4 GQW
CPV1 4 27 CKVB3 YMDNN
CPV2 5 26 CKVCS3
GND CKV3
CPV3 6 25
CPV4 7 24 CKVB2
STV 8 23 CKVCS2
41
A0 9 22 CKV2
AGND 10 21 CKVB1
11 12 13 14 15 16 17 18 19 20
VSS
VSS_P
VOFF
VIN
LXN

CKV_FB1
CKV_FB2

CKV1
CKVCS1
STVP

WQFN-40L 6x6

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RT6936 Preliminary

Typical Application Circuit

HVIN
C9 12V
RT6936 L1 D1
RNTC 2.2µF 22µH SR26
TSM1A103 VON
36 34 31V
NTC GATEP Q1 C8
SI2308 4.7µFx2
32
LXP/CSP
R1 R10
R2 R11
20k 0.1
R9
31 0
VON
3.3V RNTC2
TSM1A103 C7
35 1µF
NTC2
33
PGND
R3
R4 14 VSS
VSS
C6 -7.6V
2.2µF

11 VIN
VIN
9 C5 12V
A0 A0 10µF

40 D2
VL SR26
12 VOFF
C1 LXN -12V
2.2µF C4
L1 10µF
22µH
R8
10
AGND 13 0
VOFF
C3
1µF

3.3V
15
VSSP VSSP (To Panel)
C2
R5 R6 10µF
4.7k 4.7k 18
STVP STVP (To Panel)
2
(From T-CON) SDA SDA
3 CKV1,CKV2 19,22,25,28 CKV1,CKV2 (To Panel)
(From T-CON) SCL SCL CKV3,CKV4 CKV3,CKV4
8 R7
(From T-CON) STV STV 100
CKVCS1,CKVCS2 20,23,26,29
CPV1,CPV2 4,5,6,7 CPV1,CPV2 CKVCS3,CKVCS4
(From T-CON)
CPV3,CPV4 CPV3,CPV4
CKVB1,CKVB2 21,24,27,30 CKVB1,CKVB2
(To Panel)
1 CKVB3,CKVB4 CKVB3,CKVB4
(From T-CON) BANK_SEL BANK_SEL 16,17
CKV_FB1,CKV_FB2 CKV_FB1,CKV_FB2 (From Panel)
39
(From T-CON) TRDY TRDY
38
SEQ_OUT SEQ_OUT (To RT6929 SEQ_IN)
37
FAULT FAULT (To RT6929 FAULT)

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 Preliminary RT6936
VON Boost Application Circuits
HVIN
C9
GATEP 2.2µF L1
VON
22µH
BOOST LXP/CSP
Temp.
Compensation

R9
FBP 0
VON VON
C7 C8 31V
1µF 4.7µF x 2

NTC RNTC
TSM1A103

R1
R2

Figure 1. VON Control I : Sync-Boost

Register Address = 11h, Data = 00xxxxx1 or 01xxxxx1.

HVIN
C9
2.2µF L1
22µH
GATEP
VON D1
BOOST SR26
LXP/CSP VON
C8 31V
Temp.
Compensation 4.7µF x 2

R9
FBP 0
VON
C7
1µF
NTC RNTC
TSM1A103

R1
R2

Figure 2. VON Control II : Async-Boost used External Diode

Register Address = 11h, Data = 10xxxxx1.

L1
22µH
HVIN
C9
D1 2.2µF
Q1 SR26
VON
SI2308
GATEP 31V
VON C8
BOOST 4.7µF x 2
LXP/CSP
Temp. R10 R11
Compensation 20k 0.1

R9
FBP VON 0
C7
1µF
NTC RNTC
TSM1A103

R1
R2

Figure 3. VON Control III : Async-Boost used External MOS and External Diode
Register Address =11h, Data = 11xxxxx1.
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RT6936 Preliminary

VOFF Buck-Boost Application Circuits

VIN

LXN

L2 VOFF
22µH Inverting
3.3V Buck-Boost

R8
VOFF 0 VOFF FB3
-12V
C4 C3
10µF 1µF

Figure 4. VOFF Control I : Sync-Buck-Boost

Register Address = 11h, Data = xx0xxxx1.

VIN

D2
SR26
VOFF LXN
-12V VOFF
L2
C4 R8 22µH Inverting
10µF 0
3.3V Buck-Boost

VOFF FB3

C3
1µF

Figure 5. VOFF Control II : Async-Buck-Boost

Register Address = 11h, Data = xx1xxxx1.

VOFF Operating Frequency for Different Type Inductor

Operating Frequency (kHz) Coil Inductor = 22H Chip Inductor = 6.8H
450 ○
600 ○
750 ○
900 ○ ○
1200 ○
1350 ○
1500 ○
1800 ○
2250 ○
2700 ○

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 Preliminary RT6936
Timing Diagram
VIN >1 sec
VIN, GD UVLO_R VIN-4V UVLO_F UVLO_R
(From RT6929) GD

VDD1 TDischarge<200ms
VDD1
(From RT6929) 1.75V

3ms 1.35V CDLY

CDLY
(From RT6929)

RESET RESET
(From RT6929)

VDD3 VDD3
1.5ms
(From RT6929)

VDD2 VDD2
1.5ms
(From RT6929)

3ms TRDY
TRDY
(From T-CON)

I2C Command
Control DC-DC Gamma ACC/DCC
VON
TRDY = 1 & RT6936 Register Address 11h[0] = 1,
VSS_P, IC is enabled immediately.
VOFF
(From RT6936) VSS_P
VOFF

SEQ_OUT SEQ_OUT
3ms
(From RT6936)

AVDD
TRDY = 1 & SEQ_IN = 1, RT6929 Register
Address 14h[0] = 1, IC is enabled immediately. HAVDD
AVDD, HAVDD
(From RT6929) AVDD*0.11

FAULT DLY1 SS=5ms FAULT

VON

VON VON_UVLO
(From RT6936)
DLY2 5ms
STV SS=5ms DLY3 STV
(From RT6936)
CPVx First Rising Edge
CPVx
(From RT6936)

Scan Driver Enable

CKVx

CKVx
(From RT6936)
Pull High
CKVBx

CKVBx
(From RT6936)
Pull High
STVP
High Impedance
STVP
(From RT6936) High Impedance

Figure 6. Normal Power Sequence

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RT6936 Preliminary

IC Standby
 TRDY = 0
 Register Address = 11h[0] = 0

Table 1. IC Shutdown Function

Shutdown Operation
Address Name
Channel Shutdown IC Shutdown
00h VON_NT_Bank1 VON_NT_Bank1= 00h VON_NT_Bank1 > E0h, VON_NT_Bank1 < 4Ah
01h VOFF_NT_Bank1 VOFF_NT_Bank1= 00h VOFF_NT_Bank1 > 86h, VOFF_NT_Bank1 < 18h
02h VSS_Bank1 VSS_Bank1 = 00h VSS_Bank1 > 7Ch, VSS_Bank1 < 13h
03h VON_NT_Bank2 VON_NT_Bank2 = 00h VON_NT_Bank2 > E0h, VON_NT_Bank2 < 4Ah
04h VOFF_NT_Bank2 VOFF_NT_Bank2 = 00h VOFF_NT_Bank2 > 86h, VOFF_NT_Bank2 < 18h
05h VSS_Bank2 VSS_Bank2 = 00h VSS_Bank2 > 7Ch, VSS_Bank2 < 13h
06h VON_LT VON_LT = 00h VON_LT > E0h, VON_LT < 4Ah
07h VOFF_LT VOFF_LT = 00h VOFF_LT > 86h, VOFF_LT < 18h
09h VSS_HT VSS_HT = 00h VSS_HT > 7Ch, VSS_HT < 13h
VON-VOFF > 60V

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 Preliminary RT6936
51
CKV1
4.7nF
CKVB1 51

4.7nF
51
CKV2
4.7nF
CKVB2 51

CPV 4.7nF
(Function 51
Generator)
CKV3 4.7nF
CKVB3 51

4.7nF
51
CKV4 4.7nF
CKVB4 51

4.7nF

Figure 7. Output Loading of CKVx/CKVBx

Trigger (50%) Method 1 (ns)

Method 2 (ns)

150kHz

Specification
Δns < ±0.01 x (1/150k) should be guaranteed at the same Load and
the CPV of 150kHz (Oscilloscope Bandwidth = 500MHz)
Figure 8. Measurement Method

CPVx

VON TF_CKVCSx

TF_CKVx

CKVx or
CKVBx TR_CKVx

VOFF
TR_CKVCSx
Figure 9. Propagation Delay Time of CKVx, CKVBx (STV = GND)

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RT6936 Preliminary

STV

TF_STVP

STVP
TR_STVP

Figure 10. Propagation Delay Time of STVP (CKV1 = L)

VON

80%
TR TF

20%
VOFF

Figure 11. Rising Time and Falling Time of CKVx, CKVBx (STV = H) and STVP (CKV1 = L)

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 Preliminary RT6936
ASG Error Detect Method
1 Frame
STV

Level Setting
Programmable
Error Normal Error Error Normal

CKV_FBx

Figure 12 . STV 64 Time Count : Setting Error Count DetectData Writing (01)

1 Frame

STV

Error Normal Error Error Normal

Level Setting
Programmable
CKV_FB1

Normal Normal Normal Normal Normal

Level Setting
Programmable
CKV_FB2

Final Decision
Error Normal Error Error Normal

Figure 13. Dual Operating Detect Method

CKV Output Condition
A0 = 0 : Slave Address : 48h; Data Normal : 00h ; Fault : A5h
A0 = 1 : Slave Address : 68h; Data Normal : 00h ; Fault : A5h

1 Frame

STV

VON

CKVx
(Normal)

VOFF

VON

CKVx
(Fault)

VOFF

Figure 14. SCAN DRIVER Output Ratio During ASG Error

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RT6936 Preliminary

ASG Carry Waveform

 Normal Waveform (One Signal)

1 Frame

STV
VON

CKV_FBx

Set Level

VSS

VOFF

 Error Waveform Type (Normal Level Multi-Signal)

1 Frame

STV
VON

Set Level

VOFF

 Error Waveform Type (Low Level Signals, or No Signal)

1 Frame

STV
VON

Set Level
Low Level

VSS

VOFF

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 Preliminary RT6936
ASG Error

 A5h when power on.

Normal Output with Slave Address 48h/68h data = 00h

Data : 00h Data : A5h

VON
CKVx Delay
CKVx
Output

CKV_FBx VOFF

No Load Detect Error Detect Fault Output Fault Output Fault Output
(32 Frame) (64 Frame) ( Ex : 1:31) ( Repetition) ( Repetition)

When IC detects Error more than

Setting Count,
Data Conversion (00h or A5h)
and Fault CKVx Output.

 Abnormal Output with Slave Address 48h/68h data = A5h when power on.

Data : A5h

VON
CKVx Delay
CKVx
Output

CKV_FBx VOFF

Fault Output Fault Output Fault Output Fault Output Repetition

( Ex : 1:31) ( Repetition) ( Repetition) ( Repetition)

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RT6936 Preliminary

Functional Pin Description

Pin No. Pin Name Pin Function
Bank select input for VON/VOFF/VSS of 2D/3D;
1 BANK_SEL
0 = output bank 1, 1 = output bank 2.
2 SDA DATA I/O pin for the I2C serial interface.
3 SCL Clock input pin for the I2C serial interface.
4 CPV1 SCAN driver clock signal 1 input pin.
5 CPV2 SCAN driver clock signal 2 input pin.
6 CPV3 SCAN driver clock signal 3 input pin
7 CPV4 SCAN driver clock signal 4 input pin.
8 STV SCAN driver start signal input pin.
9 A0 Slave address assignment.
10 AGND Analog ground.
Supply voltage input of VOFF buck-boost converter and VL internal
11 VIN
regulator.
12 LXN Switching node of VOFF inverting converter.
13 VOFF Power input of SCAN driver. VOFF Inverting Feedback Input.
14 VSS VSS negative linear regulator output.
15 VSS_P VSS discharge switch output.
16 CKV_FB1 ASG carry feedback signal input1.
17 CKV_FB2 ASG carry feedback signal input2.
18 STVP SCAN driver start signal output pin.
19 CKV1 SCAN driver clock signal 1 output pin.
20 CKVCS1 SCAN driver CKV1 charge share pin.
21 CKVB1 SCAN driver clock signal 1 inverting output pin.
22 CKV2 SCAN driver clock signal 2 output pin.
23 CKVCS2 SCAN driver CKV2 charge share pin.
24 CKVB2 SCAN driver clock signal 2 inverting output pin.
25 CKV3 SCAN driver clock signal 3 output pin.
26 CKVCS3 SCAN driver CKV3 charge share pin.
27 CKVB3 SCAN driver clock signal 3 inverting output pin.
28 CKV4 SCAN driver clock signal 4 output pin.
29 CKVCS4 SCAN driver CKV4 charge share pin.
30 CKVB4 SCAN driver clock signal 4 inverting output pin.
31 VON VON boost feedback input and power input of SCAN driver.
Switching node of VON boost converter or switch current sensing input for
32 LXP/CSP
VON boost converter.

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 Preliminary RT6936
Pin No. Pin Name Pin Function
33 PGND Power ground.
34 GATEP Gate drive output for VON boost converter.
35 NTC2 Slope setting pin for temperature compensation of the VSS converter.
Slope setting pin for temperature compensation of the VON and VOFF
36 NTC
converter
37 FAULT FAULT signal (DATA EN, SCP, TSD, UVLO) output & enable signal input.
38 SEQ_OUT AVDD/HAVDD (RT6929) enable signal output.
39 TRDY Enable signal input from T-CON.
40 VL Internal linear regulator output.
Power ground. The exposed pad must be soldered to a large PCB and
41 (Exposed Pad) PGND
connected to PGND for maximum power dissipation.

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RT6936 Preliminary

Functional Block Diagram

VL
Internal Thermal A0
VIN
Regulator Shutdown
DAC SEQ_OUT
2
UVLO I C TRDY
VL Interface BANK_SEL
Register SCL
100k
SDA
Sequence
FAULT
10µA Control CKV_FB1
CKV_FB2
GATEP
NTC VON LXP/CSP
Boost
NTC2 Temp
Compensation
VSS
Regulator FBP
VSS
Temp VON
Compensation

VOFF
3.2V
FBS

VSS_P
VIN
Dis-
SCAN Charge
LXN Driver STV
VOFF Control CPVx
Inverting
3.3V Buck-Boost VON
Temp
Compensation x4
FB3 L/S CKVx

VOFF
VOFF
PGND NTC x4 CKVCSx
L/S

AGND
VON VON

x4
STVP L/S L/S CKVBx

VOFF VOFF

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 Preliminary RT6936
Absolute Maximum Ratings (Note 1)
 VIN to PGND ---------------------------------------------------------------------------------------------------------------- −0.3V to 20V
 VIN to LXN ------------------------------------------------------------------------------------------------------------------- −0.3V to 50V
 VOFF, VSS to PGND ---------------------------------------------------------------------------------------------------- −30V to 0.3V
 VON, LXP/CSP to PGND ------------------------------------------------------------------------------------------------ −0.3 to 50V
 NTC, NTC2, SDA, SCL, CPVx, STV, TRDY, BANK_SEL, A0,
GATEP, FAULT, SEQ_OUT, VL to AGND ---------------------------------------------------------------------------- −0.3 to 6V
 CKVFB1, CKVFB2, VSS_P, STVP, CKVx, CKVBx, CKVCSx to PGND ------------------------------------ −30 to 47V
 VON to VOFF -------------------------------------------------------------------------------------------------------------- 60V
 Power Dissipation, PD @ TA = 25°C
WQFN-40L 6x6 ------------------------------------------------------------------------------------------------------------ 3.69W
 Package Thermal Resistance (Note 2)
WQFN-40L 6x6, θJA ------------------------------------------------------------------------------------------------------- 27.1°C/W
WQFN-40L 6x6, θJC ------------------------------------------------------------------------------------------------------ 4.9°C/W
 Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
 Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
 Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------- 2kV
MM (Machine Model) ----------------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

 Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VIN = 12V, VON = 31V, VOFF = −12V, VSS = −7.6V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Supply Current
Input Voltage Range VIN 9.5 -- 14.7 V
VIN Under-Voltage Lockout VIN Falling 7.7 8.15 8.6 V
VUVLO
Threshold VIN Rising 8.5 8.8 9.1 V
VIN Under-Voltage Lockout
VUVLO_HYS 0.5 0.65 0.8 V
Hysteresis

VON Start-up Trigger VON Falling 6.8 7.25 7.7 V

VON_SS
Voltage VON Rising 7.6 7.9 8.2 V
VON Start-up Trigger
VON_SS_HYS 0.5 0.65 0.8 V
Voltage Hysteresis
Quiescent Current into VIN IQ_VIN LXP/CSP, LXN No Switching -- 3.3 -- mA

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RT6936 Preliminary

Parameter Symbol Test Conditions Min Typ Max Unit

VL Output Voltage VL 4.5 5 5.5 V
VL Start Threshold Voltage VL_START -- 4.1 -- V

VL Stop Threshold Voltage VL_STOP -- 3.5 -- V

VL UVLO Hysteresis VL_ HYS -- 0.6 -- V

EEPROM Write Guarantee 1000 -- -- Count

Thermal Shutdown
150 165 180 °C
Threshold
Thermal Shutdown
-- 20 -- °C
Hysteresis
Internal Oscillator
Oscillator Frequency11 FOSC11 Initial Frequency 10h[3:2] = “00” 360 450 540 kHz
Oscillator Frequency12 FOSC12 Initial Frequency 10h[3:2] = “01” 480 600 720 kHz
Oscillator Frequency13 FOSC13 Initial Frequency 10h[3:2] = “10” 600 750 900 kHz
Oscillator Frequency14 FOSC14 Initial Frequency 10h[3:2] = “11” 720 900 1080 kHz
Oscillator Frequency21
FOSC21 Initial Frequency “00” x 2 720 900 1080 kHz
(VOFF)
Oscillator Frequency22
FOSC22 Initial Frequency “01” x 2 960 1200 1440 kHz
(VOFF)
Oscillator Frequency23
FOSC23 Initial Frequency “10” x 2 1200 1500 1800 kHz
(VOFF)
Oscillator Frequency24
FOSC24 Initial Frequency “11” x 2 1440 1800 2160 kHz
(VOFF)
Oscillator Frequency31
FOSC31 Initial Frequency “00” x 3 1080 1350 1620 kHz
(VOFF)
Oscillator Frequency32
FOSC32 Initial Frequency “01” x 3 1440 1800 2160 kHz
(VOFF)
Oscillator Frequency33
FOSC33 Initial Frequency “10” x 3 1800 2250 2700 kHz
(VOFF)
Oscillator Frequency34
FOSC34 Initial Frequency “11” x 3 2160 2700 3240 kHz
(VOFF)
BOOST Converter (VON)
Soft Start Period TSS_VON 4 5 6 ms
Register Address = 00h/03h/06h,
Adjustable Normal VON
VON 8 bits, VON = 15V to 45V, 15 -- 45 V
Output Voltage Range
[4Ah to E0h]
VON Regulation Voltage
VON_NT No Load, ±3.0% Error 30.07 31 31.93 V
(Normal Temp Default)
VON Regulation Voltage No load, ±3.0% Error,
VON_LT 36.86 38 39.14 V
(Low Temp Default) NTC Option 10h[4] = 0
VON x VON x VON x
VON Fault Trip Level VFT_VON VON Falling, 0Ch[0] = 0 V
0.7125 0.75 0.7875

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 Preliminary RT6936
Parameter Symbol Test Conditions Min Typ Max Unit
Register Address = 0Dh,
(Internal MOS) [7:5] = 111
LXP/CSP Current Limit ILIM_LXP/CSP VON_OCP[7:5] Control 2.25 2.8 3.35 A
OCPLevel from 0.5A to
2.25A, 1 Step 0.25A
LXP/CSP Maximum Duty DMAX_LXP/CSP -- 90 -- %
LXP/CSP to PGND
RDS(ON)_LXP_LG ILXP/CSP = 0.2A 0.3 0.5 0.7 
N-MOSFET On-Resistance
LXP/CSP to VON RDS(ON)_LXP
ILXP/CSP = 0.2A 0.3 0.5 0.7 
N-MOSFET On-Resistance /CSP_UG
LXP/CSP to PGND
N-MOSFET Leakage ILEAK_ LXP_LG VLXP/CSP  PGND = 45V -- -- 5 A
Current
LXP/CSP to VON
N-MOSFETLeakage ILEAK_ LXP_UG VON  VLXP = 45V -- -- 5 A
Current
Load Regulation 0 < ILOAD < 0.2A 1 -- 1 %
VIN = 9.5 to 14.7V,
Line Regulation 1 -- 1 %
ILOAD = 0.1A
VON Over-Voltage
VON_OVP VON Rising 45.6 47.5 49.4 V
Protection
Sense Resistor = 0.1
Register Address = 0Dh,
LXP/CSP Threshold (External MOS) [7:5] = 111
VLXP/CSP 0.225 0.28 0.335 V
Voltage VON_OCP[7:5] Control OCP
Level from 0.05V to 0.225V, 1
step = 0.025V
GATEP High Voltage VGPH 2 -- VL V
GATEP Low Voltage VGPL 0 - 1 V
Register Address = 0Eh,
[5:4] = 00 GATEP_SR[5:4],
GATEP ON-Resistance RGP_UG 10/20/40/80 -- 10 -- 
IGATEP = 10mA for External
MOS
Output Resolution RESVON -- 0.2 -- V
Integral Non-Linearity INLVON 1 -- 1 LSB
Differential Non-Linearity DNLVON 1 -- 1 LSB
Device Temperature Control
NTC Source Current INTC 9 10 11 A
DTC Gain (VON) GainVON NTC Select = 0 -- 1.5 -- V/V
DTC Gain (VOFF) GainVOFF NTC Select = 1 -- 2 -- V/V
Register Address = 09h,
DTC Gain (VSS) GainVSS -- 0.5 -- V/V
VSS_HT_Sel [7] = 0
NTC Hysteresis NTCHYS For VON and VOFF -- 50 -- mV

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RT6936 Preliminary

Parameter Symbol Test Conditions Min Typ Max Unit

Negative BUCK-BOOST Converter (VOFF)
Soft Start Period TSS_VOFF 2.4 3 3.6 ms
VIN Overvoltage
VOVP_VIN VIN Rising, Hysteresis = 0.3V 15 -- 18 V
Protection
Register Address =
Adjustable Normal VOFF
VOFF 01h/04h/07h, 8 bits, VOFF_NT 27 -- 5 V
Output Voltage Range
= 5V to 27V [18h to 86h]
VOFF Regulation
Voltage (Normal Temp VOFF_NT No load, ±3.0% Error 12.36 12 11.64 V
Default)
VOFF Regulation
No load, ±3.0% Error,
Voltage (Low Temp VOFF_LT 22.66 22 21.34 V
NTC Option 10h[4] = 1
Default)
VOFF x VOFF x VOFF x
VOFF Fault Trip Level VFT_VOFF VOFF Falling V
0.7125 0.75 0.7875
VIN to LXN MOSFET
RDS(ON)_LXN_LG ILXN = 0.2A 0.6 1 1.4 
On-Resistance
LXN to VOFF MOSFET
RDS(ON)_LXN_UG ILXN = 0.2A 0.3 0.5 0.7 
On Resistance
Frequency Select 10h[1:0] =
LXN Current Limit ILIM_LXN2,3 1 1.25 1.5 A
x2, x3
Initial Frequency 10h[3:2] =
LXN Current Limit ILIM_LXN1 2 2.5 3 A
x1
LXN Maximum Duty DMAX_LXN -- 90 -- %
VIN to LXN Leakage
ILeak_LXN_LG VIN - VLXN = 40V -- -- 5 A
Current
LXN to VOFF Leakage
ILeak_LXN_HG VLXN - VOFF = 40V -- -- 5 A
Current
Load Regulation 0 < ILOAD <0.2A 1 -- 1 %
VIN = 9.5 to 14.7V,
Line Regulation 1 -- 1 %
ILOAD = 0.1A
VOFF Over-Voltage
VOVP_VOFF 27.5 28.5 30 V
Protection
Output Resolution RESVOFF -- -0.2 -- V
Integral Non-Linearity INLVOFF 1 -- 1 LSB
Differential Non-Linearity DNLVOFF 1 -- 1 LSB
VOFF Discharge ON
RON_DIS_VOFF -- 100 -- 
Resistance
VOFF V Function
V Voltage VDelta V = VSS  VOFF 1.6 4 14 V
Output Resolution VRES -- 0.2 -- V
V Voltage VVDelta No load, ±3% Error 3.88 4 4.12 V

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 Preliminary RT6936
Parameter Symbol Test Conditions Min Typ Max Unit
Negative Regulator (VSS)
Soft-Start Period TSS_VSS 2.4 3 3.6 ms
Register Address =
Adjustable Normal VSS 02h/05h/09h, 8bits,
VSS 25 -- 4 V
Output Voltage Range VSS = 4V to 25V. [13h to
7Ch]
VSS Regulation Voltage
VSS_NT No load, ±3% Error 7.83 7.6 7.37 V
(Normal Temp Default)
VSS x VSS x VSS x
VSS Fault Trip Level VFT_VSS VSS Falling V
0.7125 0.75 0.7825
Output Voltage Swing VOFF
VOL_VSS IVSS = 10mA -- -- V
Low +0.2
VSS = 7.6V, Source or
VSS Continuous Current IVSS_CC 100 -- -- mA
Sink
VSS_P SW On VSS VSS_P,
RVSS_P -- 1.2 -- 
Resistance IVSS_P = 10mA
Discharge SW ON
RON_DIS IDIS = 10mA -- 75 -- 
Resistance
Output Resolution Res -- 0.2 -- V
Integral Non-Linearity INLVSS 1 -- 1 LSB
Differential Non-Linearity DNLVSS 1 -- 1 LSB
Sequence Control Pins SEQ_OUT, FAULT
FAULT Trigger Duration TDFAULT 2.5 3 3.5 ms
FAULT Pull Up
RSEQ 100 -- -- k
Resistance
FAULT High Level VOHFAULT 2 -- -- V
Output
Voltage Low Level VOLFAULT -- -- 1 V

Pull Low Voltage (FAULT) ION = 3mA -- -- 0.4 V

SEQ_OUT High Level VSEQ_OUT_OH IOUT = 2mA VL 0.2 VL 0.1 VL 0.01 V
Output
Voltage Low Level VSEQ_OUT_OL IOUT = 2mA 0.01 0.1 0.2 V
Logic Signals SDA, SCL, CPVx, STV, TRDY, BANK_SEL, A0

Input High-Level VIH 1.5 -- -- V

Voltage Low-Level VIL -- -- 0.8 V

A0 Pull Up Resistance RA0 VL Pull Up 100 -- -- k

TRDY Pull Down
RTRDY 100 -- -- k
Resistance
BANK_SEL Input current IIN_BANK_SEL VBANK_SEL= 2V 9.3 13.3 17.3 A
SDA, SCL Input current IIN_SDA/SCL VSDA/SCL= 2V 2 0 2 A

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RT6936 Preliminary

Parameter Symbol Test Conditions Min Typ Max Unit

CPVx Pull Down
RCPV 100 -- -- k
Resistance
STV Pull Down Resistance RSTV 100 -- -- k
SDA_ACK ON Voltage VACK ISDA = 3mA -- -- 0.4 V
SCL Frequency FCLK -- -- 1 MHz
High Period tHIGH 0.3 -- -- s
SCL Period
Low Period tLOW 0.4 -- -- s
SCL Rise Time tR_SCL -- -- 0.12 s
SCL Fall Time tF_SCL -- -- 0.12 s
Start Condition Hold Time tHD_STA 0.25 -- -- s
Start Condition Setup Time tSU_STA 0.25 -- -- s
SDA Hold Time tHD_DAT 50 -- -- ns
SDA Setup Time tSU_DAT 50 -- -- ns
ACK Delay Time tPD -- -- 0.35 s
ACK Hold Time tHD -- 0.1 -- s
Stop Condition Setup Time tSU_STO 0.25 -- -- s
Bus Free Time tBUF 0.5 -- -- s
Bus Capacitance CB -- -- 400 pF
Spike Rejection Pulse
tL -- 0.05 -- s
Width
Monitoring Function
VON Voltage Resolution RESM_VON -- 4 -- Bit
Voltage Monitoring
TLVON 3 -- 3 %
Tolerance
Die Temperature
RESDT -- 4 -- Bit
Resolution
Die Temperature
TLDT 7 -- 7 %
Monitoring Tolerance
Scan Driver
VON-VOFF -- -- 60 V
VON Quiescent Current IQ_VON No Switching -- 1.3 -- mA
VOFF Quiescent Current IQ_VOFF No Switching -- 1.45 -- mA
CPVx Input Frequency FCPV -- -- 150 kHz

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 Preliminary RT6936
Parameter Symbol Test Conditions Min Typ Max Unit
CKVx, VON VON VON
Logic-High VOH ISOURCE = 10mA V
CKVBx 0.15 0.05 0.02
Output VOFF + VOFF + VOFF+
Logic-Low VOL ISINK = 10mA V
Voltage 0.02 0.05 0.15
VON  VON VON 
Logic-High VOH ISOURCE = 10mA V
STVP 0.3 0.15 0.05
Output
Voltage VOFF+ VOFF + VOFF+
Logic-Low VOL ISINK = 10mA V
0.05 0.15 0.3
STVP Output Rising Slew
Slew+STVP 100 1000 -- V/s
Rate
RLOAD = 51, CLOAD = 4.7nF
STVP Output Falling Slew
Slew-STVP 100 1000 -- V/s
Rate
STVP Rising Edge
Tpr-STVP -- 90 150 ns
Propagation Delay Time
No capacitive Load
STVP Falling Edge
Tpf-STVP -- 90 150 ns
Propagation Delay Time
CKVx Output Rising Slew
Slew+CKVx 700 1000 1300 V/s
Rate
CKVx Output Falling Slew
Slew-CKVx 700 1000 1300 V/s
Rate FCPVx = 85kHz, STV= 3.3V,
CKVBx Output Rising RLOAD = 51, CLOAD = 4.7nF
Slew+CKVBx 700 1000 1300 V/s
Slew Rate
CKVBx Output Falling
Slew-CKVBx 700 1000 1300 V/s
Slew Rate
CKVx Rising Edge
Tr-CPVx_CKVx -- 90 150 ns
Propagation Delay Time
CKVx Falling Edge
Tf-CPVx_CKVx -- 90 150 ns
Propagation Delay Time
No capacitive Load
CKVBx Rising Edge
Tr-CPVx_CKVBx -- 90 150 ns
Propagation Delay Time
CKVBx Falling Edge
Tf-CPVx_CKVBx -- 90 150 ns
Propagation Delay Time
CKVxCS Rising Edge
Tcsr-CPVx_CKVx -- 150 300 ns
Propagation Delay Time FCPVx = 85kHz, STV = 0V, No
CKVxCS Falling Edge capacitive Load
Tcsr-CPVx_CKVBx -- 150 300 ns
Propagation Delay Time
Propagation Delay Time ⊿Tf_cs_typ = ⊿Tf_ckv_typ
1 0 1 %
Relative Variation = 1/150kHz
08h [1:0] = 0h 0.85 1.13 1.41

Scan Driver OCP Filter 08h [1:0] = 1h 1.7 2.27 2.84

TFLT s
Check 08h [1:0] = 2h 3.4 4.53 5.66
08h [1:0] = 3h 5.95 7.93 9.91

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RT6936 Preliminary

Parameter Symbol Test Conditions Min Typ Max Unit

0Ch, CKVOCP Level [4:1] = 1h 14 28 34
0Ch, CKVOCP Level [4:1] = 2h 40 47 54
0Ch, CKVOCP Level [4:1] = 3h 60 71 82
0Ch, CKVOCP Level [4:1] = 4h 80 94 108
0Ch, CKVOCP Level [4:1] = 5h 100 118 136
0Ch, CKVOCP Level [4:1] = 6h 120 141 162
0Ch, CKVOCP Level [4:1] = 7h 140 165 190
Scan Driver OCP Filter TILIM_ CKVx,
0Ch, CKVOCP Level [4:1] = 8h 160 188 216 mA
Check CKVBx
0Ch, CKVOCP Level [4:1] = 9h 180 212 244
0Ch, CKVOCP Level [4:1] = Ah 200 235 270
0Ch, CKVOCP Level [4:1] = Bh 220 259 298
0Ch, CKVOCP Level [4:1] = Ch 240 282 324
0Ch, CKVOCP Level [4:1] = Dh 260 306 352
0Ch, CKVOCP Level [4:1] = Eh 280 329 378
0Ch, CKVOCP Level [4:1] = Fh 300 353 406
ASG Error Detect Function
CKV_FB1,2 Input Range VCKV_FB1,2 VOFF -- VON V
CKV_FB1,2 Pull Down
RCKV_FB1,2 100 -- -- k
Resistance (to VSS)
VON VON
ASG Error Detect Voltage VASG_DET -- V
*1/8 *7/8
No Load Detect Voltage NL_DET 0Bh[4:3] = 01 4 -- -- V

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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 Preliminary RT6936
Typical Operating Characteristics
VON Boost Efficiency vs. Load Current VOFF Inverting Efficiency vs. Load Current
100 100
All Ext.
95 95

90 Async 90
Async

Efficiency (%)
Efficiency (%)

85 85
All Int.
80 80
Sync
75 75

70 70

65 65
VIN = 12V, VON = 31V VIN = 12V, VOFF = −12V
60 60
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Load Current (A) Load Current (A)

VON/VOFF Initial Switching Frequency

vs. Input Voltage VON Output Voltage vs. Load Current
1000 31.48

900 FREQ_SEL = 3

31.46
Frequency (kHz)

Output Voltage (V)

800 FREQ_SEL = 2

700
FREQ_SEL = 1 31.44 Async
600
All Ext.
500 FREQ_SEL = 0
31.42 All Int.
400
VIN = 12V
300 31.4
9 10 11 12 13 14 15 0 0.04 0.08 0.12 0.16 0.2
Input Voltage (V) Load Current (A)

VOFF Output Voltage vs. Load Current VSS Output Voltage vs. Load Current
-11.95 -7.5

-11.97 Sync -7.6

Output Voltage (V)
Output Voltage (V)

-11.99 -7.7
Async

-12.01 -7.8

-12.03 -7.9

VIN = 12V VIN = 12V

-12.05 -8
0 0.04 0.08 0.12 0.16 0.2 0 0.02 0.04 0.06 0.08 0.1
Load Current (A) Load Current (A)

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RT6936 Preliminary

VON DNL Error vs. Output Voltage VON INL Error vs. Output Voltage
1.0 1.0
0.8 0.8
0.6 0.6
DNL Error (LSB)

0.4 0.4

INL Error (LSB)

0.2 0.2
0.0 0.0
All Int.
-0.2 Async -0.2
-0.4 All Ext. -0.4 All Ext.
All Int.
-0.6 -0.6 Async
-0.8 -0.8
VIN = 12V, No Load VIN = 12V, No Load
-1.0 -1.0
15 20 25 30 35 40 45 15 20 25 30 35 40 45
Output Voltage (V) Output Voltage (V)

VOFF DNL Error vs. Output Voltage VOFF INL Error vs. Output Voltage
1.0 1.0
0.8 0.8
0.6 0.6
DNL Error (LSB)

0.4 0.4
INL Error (LSB)

Sync
0.2 0.2 Async
0.0 0.0
Sync
-0.2 -0.2
Async
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
VIN = 12V, No Load VIN = 12V, No Load
-1.0 -1.0
-27 -21 -15 -9 -3 -27 -23 -19 -15 -11 -7 -3
Output Voltage (V) Ouptut Voltage (V)

VSS DNL Error vs. Output Voltage VSS INL Error vs. Output Voltage
1.0 1.0
0.8 0.8
0.6 0.6
DNL Error (LSB)

0.4 0.4
INL Error (LSB)

0.2 0.2
0.0 0.0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
VIN = 12V, No Load VIN = 12V, No Load
-1.0 -1.0
-27 -23 -19 -15 -11 -7 -3 -27 -23 -19 -15 -11 -7 -3
Output Voltage (V) Output Voltage (V)

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 Preliminary RT6936

Power On Power Off

VOFF
(10V/Div)
VSS VOFF
(5V/Div) (10V/Div)
VSSP
(5V/Div) VSS
(5V/Div)

VSSP
(20V/Div)
VON VON
(20V/Div) (20V/Div)
VON = 31V, VOFF = −12V, VSS = −7.6V,
VON = 31V, VOFF = −12V, VSS = −7.6V VSS Disch, Option = 1

Time (2ms/Div) Time (2ms/Div)

Scan Driver Function Scan Driver OCP Function

VON = 31V, OCP Level : 40mA,
STV VOFF = −12V FAULT OCP Counter : 4
(5V/Div) (5V/Div)

CPV1 CPV1
(5V/Div) (10V/Div)

CKV1 CKV1
(20V/Div) (14V/Div)

CKVB1 IPMOS/INMOS
IMAX = 149mA, IMIN = 155mA
(20V/Div) (140mA/Div)
Time (20ms/Div) Time (2ms/Div)

ASG No Load Detect Function ASG Error Detect Function

STV STV
(5V/Div) (5V/Div)
CKV_FB1, 2 CKV_FB1, 2
(5V/Div) (5V/Div)
ASG_NoLoad_Cnt: Disable,
ASG_NoLoad_Cnt : 4/32,
ASG_Err_Cnt : Disable

CPV1 CPV1
ASG_Err_Cnt : 4/64

(5V/Div) (5V/Div)

CKV1 CKV1
(20V/Div) (20V/Div)

Time (5ms/Div) Time (5ms/Div)

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RT6936 Preliminary

I2C Command
Single I2C Register Write Protocol
A0 = 0
S 0 1 0 0 0 1 0 0 A Register Address A D7 D6 D5 D4 D3 D2 D1 D0 A P
(Slave Address)

A0 = 1
S 0 1 0 0 0 1 1 0 A Register Address A D7 D6 D5 D4 D3 D2 D1 D0 A P
(Slave Address)

Single I2C Register Read Protocol

A0 = 0
S 0 1 0 0 0 1 0 0 A Register Address A S 0 1 0 0 0 1 0 1 A
(Slave Address) (Slave Address)
D7 D6 D5 D4 D3 D2 D1 D0 A P

A0 = 1
S 0 1 0 0 0 1 1 0 A Register Address A S 0 1 0 0 0 1 1 1 A
(Slave Address) (Slave Address)
D7 D6 D5 D4 D3 D2 D1 D0 A P

Multiple I2C Register Write Protocol

A0 = 0
S 0 1 0 0 0 1 0 0 A Register Address A D7 D6 D5 D4 D3 D2 D1 D0 A
(Slave Address)
D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A P

A0 = 1
S 0 1 0 0 0 1 1 0 A Register Address A D7 D6 D5 D4 D3 D2 D1 D0 A
(Slave Address)
D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A P

Multiple I2C Register Read Protocol

A0 = 0
S 0 1 0 0 0 1 0 0 A Register Address A S 0 1 0 0 0 1 0 1 A
(Slave Address) (Slave Address)
D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A P

A0 = 1
S 0 1 0 0 0 1 1 0 A Register Address A S 0 1 0 0 0 1 1 1 A
(Slave Address) (Slave Address)
D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A P

Note 5. I2C Register Data Address is 0100010x(A0=0) or 0100011x(A0=1).

Note 6. ASG Error Detect Register/EEPROM Address is 0100100x(A0=0) or 0110100x(A0=1).
Note 7. Fault Analysis & Monitoring Registor is 0101010x(A0=0) or 0101011x(A0=1).

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 Preliminary RT6936
Register Map
Address Name Description Default Value Resolution Range 00h Function

00h VON (Bank1) [7:0] VON_NT_Bank 1 31V (9Ah) 0.2V 15V to 45V, (4Ah to E0h) VON Shutdown

01h VOFF (Bank1) [7:0] VOFF_NT_Bank 1 -12V (3Bh) 0.2V -5V to -27V, (18h to 86h) VOFF Shutdown

02h VSS (Bank1) [7:0] VSS_Bank 1 -7.6V (25h) 0.2V -4V to -25V, (13h to 7Ch) VSS Shutdown

03h VON (Bank2) [7:0] VON_NT_Bank 2 31V (9Ah) 0.2V 15V to 45V, (4Ah to E0h) VON Shutdown

04h VOFF (Bank2) [7:0] VOFF_NT_Bank2 -12V (3Bh) 0.2V -5V to -27V, (18h to 86h) VOFF Shutdown

05h VSS (Bank2) [7:0] VSS_Bank2 -7.6V (25h) 0.2V -4V to -25V, (13h to 7Ch) VSS Shutdown
VON Temp.
06h Compensation (Low [7:0] VON_LT 35V (AEh) 0.2V 15V to 45V, (4Ah to E0h) VON Shutdown
Temp)
VOFF Temp.
07h Compensation (Low [7:0] VOFF_LT -20V (63h) 0.2V -5V to -27V, (18h to 86h) VOFF Shutdown
Temp)
00h : Function OFF
VSS - VOFF [7:2] V 00h 0.2V
01h to 3Fh : 1.6V to 14V

08h 00 : 0.85s
[1:0] CKV_OCP_Det 01 : 1.7s
CKV OCP Detect Time 1h
Time 10 : 3.4s
11 : 5.95s
0 : ON
VSS NTC2 Option [7] VSS_NTC2 0h
1 : OFF
09h VSS Temp.
Compensation (High [6:0] VSS_HT -9V (2Ch) 0.2V -4V to -25V, (13h to 7Ch) VSS Shutdown
Temp)
(4counts to 64counts)
ASG Error Detect Count [7:4] ASG_Err_Cnt 3h 4(N+1)
[of the 64 counts window]
00 : 4 Counts
01 : 8 Counts
No Load Detect Count for
0Ah [3:2] ASG_NoLoad_Cnt 1h 4(N+1) 10 : 16 Counts
ASG Error Detect
11 : 32 Counts [of the 32
counts window]

ASG Error Output Status 00 : Function disable

[1:0] ASG_Err_Out 3h
ASG Error 01 : 31, 10: 63, 11: 127
0 : Shutdown
No Load Detect Option [7] [7] ASG_NoLoad_Sel 1h 1 : Skip (Don’t achieve ASG
Error Detect )
0 : Shutdown
Status of ASG Error [6] [6] ASG_Err_Status 0h 1 : Low Frame (Achieve
Low frame output)
ASG Error Data Change 0 : No Change
[5] ASG_Err_Data 0h
(Only EEPROM) [5] 1 : Change
0Bh
00 : Function Disable
(Ignore level for 32frame)
No Load Detect Level [4:3] ASG_NL_Level 1h 01 : 4V
10 : 8V
11 : 10V
000 : Function Disable
ASG Error Detect Level [2:0] ASG_Err_Level 5h 8 001 to 111 : VON*1/8 to
VON*7/8

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RT6936 Preliminary

Address Name Description Default Value Resolution Range 00h Function

0 : Apply NTC2
Aging Mode Option [7] Aging_Mode_Sel 1h
1 : Bank2(Don’t apply NTC2)
00 : 4 Counts
01 : 8 Counts
CKV OCP Detect Count [6:5] CKV_OC_Cnt 1h
10 : 16 Counts
0Ch 11 : 32 Counts
0000 : Function Disable
CKV OCP Level [4:1] CKV_OC_Level 0h 20mA 0001 to 1111 : 20mA to
300mA
Applied Point for VON 0 : at Initial OLP
[0] VON_Det_Cnt_Sel 0h
Detect Count 1 : at OLP 95%
Internal MOSFET = 0.5A to
VON OCP Level [7:5] VON_OCP_Level 3h 0.25A
2.25A
00 : Default (75%)
01 : 80%
VON OLP Level [4:3] VON_OLP_Level 0h 5%
10 : 85%
11 : 90%

0Dh 00 : Disable
VON OCP Current Detect 01 : 64 Counts
[2:1] VON_OCP_Cnt 0h 64 Counts
Count 10 : 128 Counts
11 : 256 Counts

0 : 1.5ms
VON Shut-down Time
[0] VON_SD_Time 1h 1.5ms 1 : 3ms (Min : 2.5ms,
after OLP
Typ. : 3ms, Max : 3.5ms)

00 : 1kV/s
01 : 100V/s
CKV Slew Rate [7:6] CKV_SR 0h
10 : 50V/s
11 : 15V/s

00 : 10
RON for GATEP Slew 01 : 20
[5:4] GATEP_SR 0h 2^(N+1)
Rate 10 : 40
11 : 80
0Eh
00 : 100% (Default)
VON FET Switching Slew 01 : 75%
[3:2] VON_FET_SR 0h
Rate 10 : 50%
11 : 25%

00 : 100% (Default)
VOFF FET Switching Slew 01 : 75%
[1:0] VOFF_FET_SR 0h
Rate 10 : 50%
11 : 25%

VON Delay Time [7:4] DLY2 0h 5ms 0ms to 75ms

0Fh
Eagle Delay Time [3:0] DLY3 0h 5ms 0ms to 75ms

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 Preliminary RT6936
00h
Address Name Description Default Value Resolution Range
Function
0 : ON
TSD Option [7] TSD_Sel 0h
1 : OFF
00 : Function OFF (Include Fault)
Monitoring Low Frame 01 : 8Frame
[6:5] Monit_LF_Set 2h
Setting 10 : 32Frame
11 : 128Frame
0 : VON
NTC Option [4] NTC 0h
1 : VOFF
10h
00 : 450kHz
01 : 600kHz
Initial frequency [3:2] Init_Freq 2h 150kHz
10 : 750kHz (Default)
11 : 900kHz
00 : Initial Frequency
01 : X2
VOFF Frequency Select [1:0] VOFF_Freq_Sel 0h
10 : X3
11 : X3
0 : Intermal
VON Diode Option [7] VON_Diode_Sel 0h
1 : External

0 : Intermal
VON FET Option [6] VON _FET_Sel 0h
1 : External
0 : Intermal
VOFF Diode Option [5] VOFF_Diode_Sel 0h
1 : External
11h 0 : Disable
VSS Discharge Option [4] VSS_Disch_Sel 1h
1 : Enable
[3:1] Bank_Sel
Transient Time for Bank 000 : Disable
Transient Time_VON, 0h 1.5ms
Select 001 to 111 : 1ms to 10ms
VOFF, VSS

0 : Standby
Start-up Enable [0] Start-up Enable 1h
1 : Enable

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RT6936 Preliminary

Fault Analysis & Monitoring

Address Name Description Default Value Resolution Range

Die Temperature [7:4] Die_Temp 5°C 75°C to 150°C

00h
ASG Error Count [3:0] ASG_Err_Cnt 4 Count 4 count to 64count

01h VON Voltage [7:4] VON 2V 13V to 43V

0 : Normal
Analog EN [6] Analog_EN
1 : Error
0 : Normal
I2C [5] I2C
1 : Error
0 : Normal
Wrong Data [4] Wrong Data
1 : Error
02h
0 : Normal
No-load [2] No_Load
1 : Error
0 : Normal
ASG Error [1] ASG_Err
1 : Error
0 : Normal
CKV OCP [0]CKV_OCP
1 : Error
0 : Normal
VON OVP [6] VON_OVP
1 : Error
0 : Normal
VON OLP [5] VON_OLP
1 : Error
0 : Normal
VOFF OVP [4] VOFF_ OVP
1 : Error
0 : Normal
03h VOFF OLP [3] VOFF_OLP
1 : Error
0 : Normal
VSS OLP [2] VSS_OLP
1 : Error
0 : Normal
VON-VOFF [1] VON-VOFF
1 : Error
0 : Normal
TSD [0] TSD
1 : Error

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 Preliminary RT6936
Fault Type Fault Judgment
2
When the I C enable signal is not detected in 10 seconds(typ.) after
I2C Error
releasing VIN UVLO
Analog EN When the TRDY signal from T-con is not detected in 10 seconds(typ.)
(Masking “Low” during the operation) after completion of I2C communication.
Wrong DATA When any register data is out of range
When any output voltage is over the OVP detect level 10 times (When
OVP
STV signal starts , the OVP function resets the OVP level count)
OLP When the IC is latched in shut-down condition due to the SCP
TSD When the IC falls to TSD condition irrespective of TSD on/off option.
When all outputs are latched in shut-down condition due to the CKV OCP
CKV OCP
irrespective of CKV OCP option
When the different voltage between VON(2D/3D) and VOFF(2D/3D)
VON-VOFF becomes higher than 60V 10times (When STV signal starts, the subtract
function resets the count)
No-load When the IC detects the no-load status in case of shut-down option only.
ASG Error When the IC falls to ASG Error condition irrespective of ASG option

Monitoring Data
Code Die Temp. (°C) ASG Error Count (Times) VON Voltage (V)
0000 70 to 75 01 to 04 0 to 13
0001 75 to 80 05 to 08 13 to 15
0010 80 to 85 09 to 12 15 to 17
0011 85 to 90 13 to 16 17 to 19
0100 90 to 95 17 to 20 19 to 21
0101 95 to 100 21 to 24 21 to 23
0110 100 to 105 25 to 28 23 to 25
0111 105 to 110 29 to 32 25 to 27
1000 110 to 115 33 to 36 27 to 29
1001 115 to 120 37 to 40 29 to 31
1010 120 to 125 41 to 44 31 to 33
1011 125 to 130 45 to 48 33 to 35
1100 130 to 135 49 to 52 35 to 37
1101 135 to 140 53 to 56 37 to 39
1110 140 to 145 57 to 60 39 to 41
1111 145 to 150 61 to 64 41 to 43

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RT6936 Preliminary

Application Information
The RT6936 is a multi-functional power solution for LCD from 4Ah to E0h. Refer to Register Map and Output Code
panels. The RT6936 contains a negative regulator VSS Table. The output voltage can be disabled by I2C register
and a triple high-voltage scan driver to drive an ASG 00h / 03h data setting 00h. If VON setting is over E0h or
(Amorphous Silicon Gate) circuit on TFT glass for GIP under 4Ah, IC will shut down.
panels. Moreover, a Boost converter and a negative Buck-
Boost regulator with temperature compensation are also VON Boost Over-Voltage Protection
included to provide adjustable regulated VON and VOFF In case, VON pin is above 47.5V (typ.), the converter turns
to generate gate high and gate low voltages. Two converters the MOSFET switch off. As soon as the output voltage
are both operate with selectable switching frequency by falls below the over voltage threshold, the converter
setting I2C register 10h[3:2] and 10h[1:0]. resumes operation.

VON Boost Converter VON Boost Over-Current Protection

The non-synchronous Boost converter generates high level The RT6936 can limit the peak current to achieve over
voltage to the level shifter. The Boost circuit be used the current protection. The IC senses the inductor current that
external MOS. The converter's temperature compensation is flowing into the LXP/CSP pin during an ON period. The
feature allows for different VON level at a certain external or internal N-MOSFET will be turned off if the
temperature range. peak inductor current reaches 2.8A (typ.). The OCP can
be achieved by setting the I2C Register address is 0Dh
VON Boost Soft-Start and VON_OCP 0Dh[7:5] control OCP level from 0.5A to
The VON Boost converter has an internal soft-start to 2.25A with setting internal N-MOSFET. When setting
reduce the input inrush current. When the converter is external N-MOSFET, VON OCP 0Dh[7:5] control OCP
enabled, the output voltage rises slowly from VIN to VON. sense voltage level from 0.05V to 0.225V.
The soft-start time is around 5ms.
VON Boost Over-Current Protection
VON Boost Output Voltage Setting As shown in Figure 15 and Figure 16.When OCP occurred,
The output voltage can be achieved by setting the I2C IC will latch in shutdown. The OLP level of VON is
Register 00h and Register 03h. The VON setting is from controllable by setting I2C Register 0Dh [4:3]. VON have
15V to 45V when Register 00h and Register 03h data only two shutdown time (1.5ms or 3ms) after OLP and
controlled by setting I2C Register 0Dh [0].

VON Voltage
100%
90%
85%
80%
75%
Shut down after Shut down after
(1.5ms or 3ms) (1.5ms or 3ms)
Shut down after
Shut down after (1.5ms or 3ms)
(1.5ms or 3ms)

(1.5ms or 3ms)
VON Current

OCP Level

Figure 15. VON OLP Setting Level after OCP Occurred

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 Preliminary RT6936
VON Voltage
100%
95%

Shut down after

OCP Clock count at OLP
Shut down after
OCP Clock count

Count

VON Current

Figure 16. Applied Point for VON Detect Count

VON Temperature Compensation VON Voltage

The VON output voltage is temperature compensated by VON (NTC Setting) =

VON_LT (MAX.) 45V VNTC x 1.5 x (217 / 8)
setting I2C Register 10h bit [4] = 0 and fully adjustable
VON_LT (Default) 35V
from VON_NT to VON_LT by setting I2C Register 00h
VON_NT (Default) 31V
(Bank1)/03h (Bank2) and Register 06h. The external
VON_NT (MIN.) 15V
resistive between pins NTC and GND allows programming
voltage of different temperature. The thermal compensation
VNTC Voltage Temperature
function block and curve are shown in Figure 17 and
Figure 18. VNTC_LT (MAX.) 1.1060V

VNTC_LT (Default) 0.8602V

VL
5V VNTC_NT (Default) 0.7619V

VNTC_NT (MIN.) 0.3687V

10µA Higher Input
x1.5 Selector Lower Input
VNTC
Selector
VON T2 T1 Temperature
R1 1.8V
RNTC 217k
VON Figure 18. VON Temperature Compensation Curve
R2 DAC Normal Output
I2C Voltage 8k
BUS 1.8V
I/F
SET
DAC Max. Peak Voltage
Temp. Comp.

Figure 17 . VON Temperature Compensation Function

Block

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RT6936 Preliminary

VNTC = INTC x [(RNTC // R1) + R2] If the VNTC < VON_NT(Default)   8   1.5, VON = VON_NT
 217 
Where INTC is the reference current and the typical value
is 10μA. The VON voltage can be set as the following If the VNTC > VON_LT(Default)   8   1.5, VON = VON_LT
 217 
equation. Comparators should have the hysteresis function at
boundary Region A and B. As shown in Figure 19. (The
noise of VNTC is possible to occur the oscillation at the
boundary region)

VNTC

VNTC R1
RNTC

VREF (Max)
R2
VON

VREF (Max) VREF (Min)

VNTC

VNTC

VNTC_High : Typ+50mV

VREF (Min)
VNTC_Typ : Typ

About About VNTC_Low : Typ-50mV

2°C 2°C

Boundary Region A Boundary Region B Temperature

Figure 19. VON Temperature Compensation Hysteresis

Boost Inductor Selection Note that the saturated current of inductor must be greater
The inductor value depends on the maximum input current. than IPEAK. The inductance can eventually be determined
As a general rule the inductor ripple current is 20% to according to the following equation :
   VIN    VOUT  VIN 
40% of maximum input current. If 40% is selected as an 2

example, the inductor ripple current can be calculated L

0.4   VOUT   IOUT(MAX)  fOSC
2
according to the following equation :
where fOSC is the switching frequency. For better system
VOUT  IOUT(MAX)
IIN(MAX)  performance, a shielded inductor is preferred to avoid EMI
  VIN
problems.
IRIPPLE  0.4  IIN(MAX)
Boost Diode Selection
Wher η is the efficiency of the Boost converter, IIN(MAX) is
the maximum input current and IRIPPLE is the inductor ripple Schottky diode is a good choice for an asynchronous
current. The input peak current can be obtained by adding Boost converter due to its small forward voltage. However,
the maximum input current with half of the inductor ripple when it selects Schottky diodes, important parameters
current as shown in the following equation : such as power dissipation, reverse voltage rating and
pulsating peak current should all be taken into
IPEAK = 1.2 x IIN(MAX)

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 Preliminary RT6936
consideration. For better performance, it is recommended
to choose a suitable diode with reverse voltage rating
ΔIL
greater than the maximum output voltage and its average
current rating must exceed the average output current. Input Current Inductor Current

Boost Input Capacitor Selection

Low ESR ceramic capacitors are recommended for input
capacitor applications. Low ESR will effectively reduce Output Current

the input ripple voltage caused by the switching operation. Time

4.7μF x 2 low ESR ceramic capacitors are sufficient for

(1-D)TS Output Ripple
most applications. Nevertheless, this value can be Voltage (ac)
decreased for applications with lower output current
Time
requirement. Another consideration is the voltage rating
ΔVOUT1
of the input capacitor, which must be greater than the
maximum input voltage.
Figure 20. The Output Ripple Voltage without the
Boost Output Capacitor Selection Contribution of ESR

Output ripple voltage is an important index for estimating

the performance. This portion consists of two parts, one
Over-Temperature Protection
is the product of IIN and ESR of output capacitor, another
part is formed by charging and discharging process of The RT6936 equips an Over Temperature Protection (OTP)
output capacitor. As shown in Figure 20, ΔVOUT1 can be to prevent the excessive power dissipation from
evaluated based on the ideal energy equalization. overheating. The OTP will shut down switching operation
According to the definition of Q, the Q value can be while junction temperature exceeds 165°C. Main converter
calculated as the following equation : starts switching while junction temperature is cooled by
approximately 20°C. Prevent the maximum junction
1  1   1 
Q   IIN  IL  IOUT    IIN  IL  IOUT   temperature over around 125°C to maintain the continuous
2  2   2 
operation.
VIN 1
   COUT  VOUT1
VOUT fOSC
Negative VOFF Buck-Boost Converter Soft-Start
where fOSC is the switching frequency and the ΔIL is the The Buck-Boost converter has an internal soft-start to
inductor ripple current. Move COUT to the left side to reduce the input inrush current. When the converter is
estimate the value of VOUT1 as the following equation : enabled, the output voltage falls slowly from zero to VOFF.
The maximum soft-start time is around 3ms.
D  IOUT
VOUT1 
  COUT  fOSC
VOFF Buck-Boost Output Voltage Setting
Finally, the output ripple voltage can be determined as The output voltage can be achieved by setting the I2C
the following equation : Register 01h / 04h. The VOFF setting is from −5V to
D  IOUT −27V when Register 01h or 04h data from 18h to 86h.
VOUT  IIN  ESR 
  COUT  fOSC Refer to Register Map and Output Code Table. The output
voltage can be disabled by I2C Register 01h / 04h / 07h
data setting 00h. If VOFF setting is over 86h or under 18h
or |VON − VOFF| > 60V, IC will shut down.

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RT6936 Preliminary

1. Converter Duty Cycle : VOFF Buck-Boost Over-Voltage Protection

 VOUT
D= In case of VOFF pin falls below −28.5V(typ.), the converter
VIN   VOUT
turns the MOSFET switch off. As soon as the VOFF pin
2. Maximum output current : rises higher than the over voltage threshold, the converter
 V D 
IOUT =  ILPEAK  IN   1  D  will resume operation.
 2fs  L 
3. Peak switch current : VOFF Buck-Boost Fault Protection
I V D
ILPEAK = OUT  IN The Buck-Boost converter has a fault protection feature
1 D 2fs  L
to protect the IC when the output becomes shorted to
VOFF Buck-Boost Inductor Selection GND. This is achieved by using the comparator to monitor
The Buck-Boost converter is able to operate with 10μH to the VOFF voltage. This function can disable the Buck-
47μH inductors, but a 22μH inductor is typical. The main Boost converter if VOFF above VOFF x 0.75 and keeps
parameter for inductor selection is the saturation current 3ms. The Buck-Boost converter will turn on until power
of the inductor which should be higher than the peak switch on again.
current as calculated in the Design Procedure section with
VOFF Temperature Compensation
additional margin to cover for heavy load transients.
Another important parameter is the inductor DC resistance. There is a thermal compensation feature in the RT6936.
Usually, lower DC resistance has higher efficiency. The Thermal compensation mode can be selected with the
type and core material of the inductor influence the control register 10h[4]. If the 10h[4] = 1, VOFF temperature
efficiency as well. compensation function is enabled. The VNTC voltage can
be compensated via external thermal sensing element
VOFF Buck-Boost Diode Selection and resistors, which determine the slope of the
To achieve high efficiency, a Schottky diode should be compensation. The thermal compensation function block
used. The reverse voltage rating should be higher than and curves are shown in Figure 21 and Figure 22.
the maximum output voltage of the Buck-Boost converter.
VOFF Temperature Compensation
The average rectified forward current, IAVG, the Schottky
VL(5V)
diode needs to be rated for, is equal to the output current,
IOUT. 10uA Higher Input
Selector Lower Input
VNTC Selector
PD = IAVG x VFORWARD X2
VOFF
3.3V-(VNTC X 2)
R1 1.8V
VOFF Buck-Boost Output Capacitor Selection RNTC
290.3k
SET
For the best output voltage filtering, low ESR ceramic I2C
DAC Temp Reference Voltage (Max)
BUS 1.8V
R2
capacitors are recommended. One 10μF/X7R or two 4.7μF/ I/F 20k
VOFF
DAC
X7R output capacitors with sufficient voltage ratings in Normal Reference Voltage (Min.)
3.3V
parallel are adequate for most applications. Additional
Figure 21 . VOFF Temperature Compensation Function
capacitors can be added to improve load transient
Block
regulation.

VOFF Buck-Boost Over-Current Protection

The RT6936 can limit the peak current to achieve over
current protection. The IC senses the inductor current that
is flowing into the LXN pin during an on period. The internal
P-MOSFET will be turned off if the peak inductor current
reaches 2.5A (typ.)

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 Preliminary RT6936
Temperature
VSS Discharge Function
VOFF_NT (MAX.) -5V The VSS discharge function can be achieved by setting
VOFF_NT (Default) -12 the I2C Register address 11h[4]. If the 11h[4] is set high,
VOFF_LT (Default) -22
VOFF (NTC Setting) VSS discharge function is enabled and the switch S1 is
VOFF_LT (MIN.) -25 = 3.3- VNTC x 2 x 15.5
turned on and S2 is turned off. Thus, VSSP equals VON.
If the 11h bit [4] is set low, the function is disabled. Then
VOFF Voltage
VNTC Voltage S1 is turned off and S2 is turned on. Thus, VSSP equals
VSS. As show in Figure 23 and Figure 24.
VNTC_LT (MAX.) 0.9129V
VNTC_LT (Default) 0.8161V VON
VNTC_NT (Default) 0.4935V VOFF
S1
VNTC_NT (MIN.) 0.2677V
VSS Linear Controller VSS_P
T2 T1 Temperature & Discharge
S2
Figure 22. VOFF Temperature Compensation Curves

VNTC = INTC x [(RNTC // R1) + R2]

Where INTC is the reference current and the typical value Figure 23 . VSS Discharge Function Block
is 10μA. The VOFF voltage can be set as the following
(V)
equation.
If the VNTC < 3.3 − VOFF_NT(Default) ÷2 ÷15.5,
VON
VOFF = VOFF_NT When VIN UVLO, Switch On

If the VNTC > 3.3 − VOFF_LT(Default) ÷ 2 ÷15.5,

VOFF = VOFF_LT AVDD

VSS Regulator Soft-Start GND

(ms)
The VSS regulator can provide negative voltage. It has an
VSS_P
internal soft-start to reduce the input inrush current. When
VOFF
the regulator is enabled, the output voltage rises slowly t_Dish
from 0V to negative VSS. The typical soft-start time is
Figure 24. VSS Discharge Function Curve
around 3ms.

VSS Regulator Output Voltage Setting VSS Temperature Compensation

2 The VSS thermal compensation mode can be selected
The output voltage can be achieved by setting the I C
Register 02h / 05h. The VSS setting is from −4V to −25V with the control register 09h[7]. If the 09h[7] = 0, VSS
when Register 02h / 05h data from 13h to 7Ch. Refer to temperature compensation function is enabled. The VNTC2
Register Map and Output Code Table. The output voltage voltage can be compensated via external thermal sensing
can be disabled by setting I2C Register 02h / 05h data element and resistors, which determine the slope of the
00h. If VSS setting is over 7Ch or under 13h, IC will shut compensation. The thermal compensation function block
down. and curve are shown in Figure 25 and Figure 26.

VSS Regulator Fault Protection

The VSS regulator has a fault protection. This function
can disables the VSS regulator if protect circuit is
detected, VSS falls below VSS x 0.75 and keeps 3ms.
The VSS regulator will turn on until power on again

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 RT6936 Preliminary
3.3 V Amplitude (V)

3.2 V
Higher Input
R3 Selector Lower Input
Selector Normal
RNTC2
VSS NTC
VNTC2
V
3.2-(VNTC2 x 0.5) High Temp
R4 1.8V
600k VSS
SET
DAC Temp Reference Voltage (Min.)
I2C VOFF
BUS 1.8V
I/F 40k
VSS T1 T2
DAC Temperature (°C)
Normal Reference Voltage (Max.)
3.2V Figure 27. ΔV (VSS − VOFF) Function Curves
Figure 25 . VSS Temperature Compensation Function
Scan Driver Level Shifter
Block
The level shifter which generates high voltage signals for
VSS Voltage
VSS (NTC2 Setting)
driving the TFT-LCD panel. Each single high-voltage scan
VSS_NT (MAX.) -4V = 3.2-VNTC2 x 0.5 x16 driver receives logic-level inputs of CPVx and generates
VSS_NT (Default) -7.6V two high-voltage outputs of CKVx, CKVBx. The device
VSS_HT (Default) -9V
receives a logic-level input of STV and generates a high-
VSS_HT (MIN.) -25V
voltage output of STVP. These outputs are swings from
VOFF (−12 V) to VON (31V) and are used to drive the
Temperature
VNTC2 Voltage
ASG circuit and charge/discharge the capacitive loads of
VNTC2_HT (MAX.) 3.525V the TFT-LCD. The RT6936 implements a charge share
VNTC2_HT (Default) 1.525V function which could reduce power dissipation.
VNTC2_NT (Default) 1.35V

VNTC2_NT (MIN.) 0.9V

Scan Driver Under-Voltage-Lockout
The under voltage lockout function ensures that the input
T2 T1 Temperature voltage is high enough for reliable operation. When VON
Figure 26. VSS Temperature Compensation Curves is smaller than 7.9V, the IC will shut down and all output
signals are at high impedance state. At the rising edge of
(RNTC2 // R3)
VNTC2 = 3.3  STV, the Scan Driver Output (CKVx/CKVBx) should be
 NTC2 // R3  +R4
R
reset.
Where INTC2 is the reference voltage and the typical value
is 3.2V. The VON voltage can be set as the following Scan Drive Logic Chart
equation. Table 3. Toggle State is Reset by Rising Edge of STV
If the Input Output
VNTC2 < (3.2 - VSS_NT(Default )  0.5  16, VSS = VSS_NT STV CPV1 STVP
If the Low Don’t Care Low
VNTC2 > (3.2 - VSS_HT(Default) )  0.5  16, VSS = VSS_HT High Low High
High High High Impedance
ΔV (VSS-VOFF) Function
Input Output
VOFF should be variable according to VSS voltage. The
STV CPVx CKVx CKVBx CKVCSx
variable VOFF voltage should be maintained to ΔV = (VSS
High High
− VOFF). If VOFF (= VSS − ΔV) is lower than −27V, VOFF Low Low ON
Impedance Impedance
should be clamped to −27V. ΔV Function is disable at Rising
Low Toggle State Toggle State OFF
VOFF NTC Option and VSS “00” and NTC should be Edge
achieved. Rising
High Toggle State Toggle State OFF
Edge
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 Preliminary RT6936
Reset
Reset

STV STV

CPVX CPVX

VOFF VOFF

VON VON

CKVX CKVX

CKVBX CKVBX

Figure 28. CPVx Edge Overlap to STV (ODD) Figure 29. CPVx Edge Overlap to STV (EVEN)

Reset
Reset

STV
STV
CPVX CPVX
VOFF
VOFF

VON
VON

CKVX CKVX

CKVBX CKVBX

Figure 30. Two CPV inside STV (ODD) Figure 31. Two CPV inside STV (EVEN)

Reset Reset

STV
STV
CPVX
CPVX
VOFF
VOFF

VON VON

CKVX
CKVX

CKVBX CKVBX

Figure 32. CPVx Edge Overlap and Inside to STV Figure 33. CPVx Edge Overlap and Inside to STV (ODD)
(EVEN)

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RT6936 Preliminary

Scan Driver Charge Sharing Scan Driver OCP Function

CKVCSx is charge share inputs. The function can The Scan Driver OCP function detects the current of each
decrease power loss. When the function is enabled, charge of the CKVx channel OCP level has 8 steps including
sharing resistors limit the current into the charge share “Function Disable”. When the CKVx level is bigger more
inputs. The larger the value of the charge sharing resistors, than OCP setting level, the level is detected. And detecting
the smaller the peak current into the charge share inputs count becomes more than setting counter in CPV 32 times,
and the gentler the slope of the output charge share IC becomes shut down. The CKVx OCP detecting time is
waveform. fixed to 1.7μs and detecting level is adjustable to 20mA
to 300mA by setting I2C Register 0Ch [4:1].

CPVx

OCP High Level

Current of CKVx
OCP Low Level

1.7µs

Figure 34. Scan Driver OCP Detection of CKVx

Table 4. SCAN DRIVER OCP Setting Step

0Ch[4:1] 0 1 2 3 4 5 6 7
Timing (Min.) 1.7s
Min [mA] Disable 20 40 60 80 100 120 140

0Ch[4:1] 8 9 A B C D E F
Timing (Min.) 1.7s
Min [mA] 160 180 200 220 240 260 280 300

Scan Driver OCP Function should count each CPV1, CKV1_Up

CKVB1_Up OCP_High/Low
CPV2, CPV3 and CPV4 on the basis of STV. If STV start CKV1_Low
again before 32 counts finish, Scan Driver OCP Count CKVB1_Low
CKV2_Up
Block should renew OCP count. OCP level has upper and CKVB2_Up OCP_High/Low
CKV2_Low
lower level two kinds. IC should ignore CPV clock during CKVB2_Low Control
Block
STV pull high, and count again form 1st CPV (rising edge) CKV3_Up
CKVB3_Up OCP_High/Low
after STV falling. CKV3_Low
CKVB3_Low
RT6936 ties up CKV1/CKVB1, CKV2/CKVB2, CKV3/ CKV4_Up
CKVB4_Up OCP_High/Low
CKVB3, CKV4/CKVB4 and counts independently. IC CKV4_Low
recognizes the total event number of CKV1/CKVB1 during CKVB4_Low

counting CPV1. If detected count becomes more than Figure 35. Scan Driver OCP Function Block
setting count in total 32 times, IC becomes shutdown. In
the same way, it counts for each CPV2, CPV3 and CPV4
independently and scan driver OCP detect count by setting
I2C Register 0Ch [6:5].

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 Preliminary RT6936

Power On

Function off No CKV OCP

Option Function Enable
(0Ch [4:1] = 0000)
Yes

CKV OCP OCP Count and Level No

IC Normal Operation
Function Disable  Setting

Yes

IC Normal Operation Shutdown

Figure 36. Scan Driver OCP Function Flow Chart

Table 5. Scan Driver OCP Detect Count In case that ASG Error detect function operates normally,
0Ch [6:5] 0 1 2 3 If ASG carry signals are over setting count times (Table
Detect Count 7.) under setting Detect level (Table 8.) during STV 64
4 8 16 32
(Total : 32 Frame) frame, scan driver should output abnormal CKVx
waveforms. And, abnormal CKVx's VOFF level frame can
ASG Error Detect Function be set by Register (Table 9). (ex. 1:31 setting : normal
CKV 1frame, VOFF level 31 Frame)
For a start, IC counts STV pulse (8 frame) after DLY3 and
shown in the Figure 37. If ASG carry signals are GND Table 7. ASG Error Detect Count
level over setting count times (Table 6.) during STV 32
0Ah[7:4] 0 1 …… 14 15
frame, IC should mask ASG Error detect function.
Detect Count
Therefore, In case of no load, the ASG Error detect function 4 8 …… 60 64
(Total : 64 Frame)
doesn be operated.

STV (32 frame after DLY3)

Table 8. ASG Error Detect Level
STV Counter 0Bh[2:0] 0 1 2 3
Detect Function
ASG Error Level Min [V] VON1/8 VON2/8 VON3/8
Detect Block Disable
Carry
Signal
ASG Error Detect
Function
0Bh[2:0] 4 5 6 7
Masking/Operating
Min [V] VON4/8 VON5/8 VON6/8 VON7/8
Figure 37. ASG Function Detection
Note 7 : Function Disable : ASG Error Detect Function
Table 6. No Load Detect Count Setting for ASG OFF.
Error
0Ah[3:2] 0 1 2 3 Table 9. SCAN DRIVER Output Ratio during ASG Error
Detect Count 0Ah[1:0] 0 1 2 3
4 8 16 32
(Total : 32 Frame)
Normal Frame : Function
1:31 1:63 1:127
VOFF Level Frame Disable

Note 8 : Function Disable : Normal Scan Driver Output

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RT6936 Preliminary

Fault Function
VL VL
During normal operating, each fault pin becomes high-
100k 100k
state. If the one chip becomes the fault-state, the fault FAULT R FAULT
pin becomes low-state. Thus, the fault pin of the other
chip becomes also low-state and shut-down. If the RT6929
becomes the fault-state, the RT6936 becomes shut down.
If the RT6936 becomes the fault-state, the RT6929 Main_Chip Sub_Chip
(From RT6929) (From RT6936)
becomes shut down except for logic power. If the resister
R removes, the fault pin of the other chip becomes high- Figure 38. Fault Function Block
state and normal operation. As show in Figure 38.

Fault and Monitoring Function Table 10. Data Monitoring & Update Period
The monitoring and update is synchronized by STV. The 10h [6:5] 00 01 10 11
update point is next frame of setting frame that is controlled Function
by 2 bit by setting I2C Register 10h [6:5]. As shown in
OFF
Frame 8 Frame 32 Frame 128 Frame
(Include
Table 10. The update data is the average of monitoring Fault)
data during the setting frame and should be transferred in
max 0.5ms.

Min. 1ms (Initial Detection)

STV
100µs A/D A/D
Chip Temp
A/D A/D A/D
VON Voltage
100µs
Figure 39. Data Monitoring Sequence

Update (Data Monitoring +1Frame) Update Update

STV

Data Monitoring Data Monitoring Data Monitoring

Figure 40. Data Monitoring & Update Period

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 Preliminary RT6936
Thermal Considerations Layout Consideration
The junction temperature should never exceed the PCB layout is very important for designing power switching
absolute maximum junction temperature TJ(MAX), listed converter circuits. For best performance of the RT6936,
under Absolute Maximum Ratings, to avoid permanent the following layout guidelines must be followed :
damage to the device. The maximum allowable power  For good regulation, place the power components as
dissipation depends on the thermal resistance of the IC close as possible. The traces should be wider and shorter
package, the PCB layout, the rate of surrounding airflow, especially for the high current output loop.
and the difference between the junction and ambient
 The output sense voltage must be near the sense pin.
temperatures. The maximum power dissipation can be
The sense voltage pin trace must be short and avoid
calculated using the following formula :
the trace near any switching nodes.
PD(MAX) = (TJ(MAX) − TA) / θJA
 Minimize the size of the LXP/CSP and LXN node and
where TJ(MAX) is the maximum junction temperature, TA is keep it wide and shorter. Keep the LX node away from
the ambient temperature, and θJA is the junction-to-ambient the analog ground.
thermal resistance.
 The power ground (PGND) consists of input and output
For continuous operation, the maximum operating junction capacitor grounds.
temperature indicated under Recommended Operating
 Separate power ground (PGND) and analog ground
Conditions is 125°C. The junction-to-ambient thermal
(AGND). Connect the AGND and the PGND islands at a
resistance, θJA, is highly package dependent. For a
single end. Make sure that there are no other
WQFN-40L 6x6, the thermal resistance, θJA, is 27.1°C/W
connections between these separate ground planes.
on a standard JEDEC 51-7 high effective-thermal-
Connect the exposed pad to a strong ground plane for
conductivity four-layer test board. The maximum power
maximum thermal dissipation.
dissipation at TA = 25°C can be calculated as below :
PD(MAX) = (125°C − 25°C) / (27.1°C/W) = 3.69W for a
WQFN-40L 6x6 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 41 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
4.0
Maximum Power Dissipation (W)1

Four-Layer PCB
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0 25 50 75 100 125
Ambient Temperature (°C)
Figure 41. Derating Curve of Maximum Power Dissipation

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RT6936 Preliminary

PGND
VIN

VON
Minimize the size of the
LXP/CSP node and keep it
wide and shorter. Keep the
LXP/CSP node away from
the analog ground.
PGND

SEQ_OUT

PGND
LXP/CSP
GATEP
FAULT

PGND
TRDY

NTC2

VON
NTC
VL
40 39 38 37 36 35 34 33 32 31

BANK_SEL 1 30 CKVB4
SDA 2 29 CKVCS4
Separate power ground (PGND) SCL 3 28 CKV4
and analog ground (AGND).
Connect the AGND and the CPV1 4 27 CKVB3
Connect the exposed
PGND islands at a single end. CPV2 5 PGND 26 CKVCS3 pad to a strong ground
Make sure that there are no
CPV3 6 25 CKV3 plane for maximum
other connections between
thermal dissipation.
these separate ground planes. CPV4 7 24 CKVB2
STV 8 23 CKVCS2
41
A0 9 22 CKV2
AGND 10 21 CKVB1

11 12 13 14 15 16 17 18 19 20
For good regulation, place the
VOFF
VIN
LXN

VSS
VSS_P
CKV_FB1
CKV_FB2

CKV1
CKVCS1
STVP

power components as close as

possible. The traces should be
wider and shorter especially for
the high-current output loop.

Minimize the size of the LXN

node and keep it wide and
shorter. Keep the LXN node
away from the analog ground.

PGND

Figure 42. PCB Layout Guide

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 Preliminary RT6936
Outline Dimension

1 1

2 2

DETAIL A
Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol
Min. Typical Max. Min. Typical Max.
A 0.700 0.750 0.800 0.028 0.030 0.031
A1 0.000 0.020 0.050 0.000 0.001 0.002
A3 0.175 0.203 0.250 0.007 0.008 0.010
b 0.180 0.250 0.300 0.007 0.010 0.012
D 5.950 6.000 6.050 0.234 0.236 0.238
Option1 4.000 4.150 4.750 0.157 0.163 0.187
D2
Option2 3.470 3.520 3.570 0.137 0.139 0.141
E 5.950 6.000 6.050 0.234 0.236 0.238
Option1 4.000 4.150 4.750 0.157 0.163 0.187
E2
Option2 2.570 2.620 2.670 0.101 0.103 0.105
e -- 0.500 -- -- 0.020 --
L 0.350 0.400 0.450 0.014 0.016 0.018

W-Type 40L QFN 6x6 Package

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RT6936

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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