MCP3021

Low-Power 10-Bit A/D Converter with I2C Interface

Features General Description

• 10-bit Resolution Microchip’s MCP3021 is a successive approximation
• ±1 LSB DNL, ±1 LSB INL maximum A/D converter (ADC) with a 10-bit resolution. Available
• 250 µA Max Conversion Current in the SOT-23 package, this device provides one
single-ended input with very low-power consumption.
• 5 nA Typical Standby Current, 1 µA maximum
Based on an advanced CMOS technology, the
• I2C Compatible Serial Interface MCP3021 provides a low maximum conversion current
- 100 kHz I2C Standard mode and standby current of 250 µA and 1 µA, respectively.
- 400 kHz I2C Fast mode Low-current consumption, combined with the small
• Up to 8 Devices on a Single 2-wire Bus SOT-23 package, make this device ideal for bat-
tery-powered and remote data acquisition applications.
• 22.3 ksps in I2C Fast mode
• Single-Ended Analog Input Channel Communication to the MCP3021 is performed using a
2-wire I2C compatible interface. Standard (100 kHz)
• On-Chip Sample and Hold
and Fast (400 kHz) I2C modes are available with the
• On-Chip Conversion Clock device. An on-chip conversion clock enables indepen-
• Single-Supply Specified Operation: 2.7V to 5.5V dent timing for the I2C and conversion clocks. The
• Temperature Range: device is also addressable, allowing up to eight devices
- Extended: -40°C to +125°C on a single 2-wire bus.
• Small SOT-23-5 Package The MCP3021 runs on a single-supply voltage that
operates over a broad range of 2.7V to 5.5V. This
Applications device also provides excellent linearity of ±1 LSB
differential nonlinearity (DNL) and ±1 LSB integral
• Data Logging nonlinearity (INL), maximum.
• Multi-Zone Monitoring
• Handheld Portable Applications Package Type
• Battery-Powered Test Equipment
• Remote or Isolated Data Acquisition 5-Pin SOT-23

VDD 1 5 SCL
MCP3021

VSS 2

AIN 3 4 SDA

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MCP3021
Functional Block Diagram

VDD VSS

DAC

Comparator
–
Sample 10-bit SAR
AIN and +
Hold
Clock

I2C
Control Logic
Interface

SCL SDA

DS20001805C-page 2  2003-2017 Microchip Technology Inc.

 MCP3021
1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

VDD...........................................................................................................................................................................+7.0V
Analog input pin w.r.t. VSS ..................................................................................................................-0.6V to VDD +0.6V
SDA and SCL pins w.r.t. VSS ...............................................................................................................-0.6V to VDD +1.0V
Storage Temperature ............................................................................................................................. -65°C to +150°C
Ambient Temperature with power applied ............................................................................................... -65°C to +125°C
Maximum Junction Temperature ........................................................................................................................... +150°C
ESD protection on all pins (HBM) .......................................................................................................................... ≥ 4 kV

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.

DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k
TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).
Parameter Sym. Min. Typ. Max. Units Conditions
DC Accuracy
Resolution — 10 bits
Integral Nonlinearity INL — ±0.25 ±1 LSB
Differential Nonlinearity DNL — ±0.25 ±1 LSB No missing codes
Offset Error — — ±0.75 ±3 LSB
Gain Error — — -1 ±3 LSB
Dynamic Performance
Total Harmonic Distortion THD — -70 — dB VIN = 0.1V to 4.9V @ 1 kHz
Signal-to-Noise and Distortion SINAD — 60 — dB VIN = 0.1V to 4.9V @ 1 kHz
Spurious Free Dynamic Range SFDR — 74 — dB VIN = 0.1V to 4.9V @ 1 kHz
Analog Input
Input Voltage Range — VSS-0.3 — VDD+0.3 V 2.7V  VDD  5.5V
Leakage Current — -1 — +1 µA
SDA/SCL (open-drain output)
Data Coding Format — Straight Binary —
High-Level Input Voltage VIH 0.7 VDD — — V
Low-Level Input Voltage VIL — — 0.3 VDD V
Low-Level Output Voltage VOL — — 0.4 V IOL = 3 mA, RPU = 1.53 k
Hysteresis of Schmitt Trigger Inputs VHYST — 0.05VDD — V fSCL = 400 kHz only
Note 1: Sample time is the time between conversions after the address byte has been sent to the converter. Refer
to Figure 5-6.
2: This parameter is periodically sampled and not 100% tested.
3: RPU = Pull-up resistor on SDA and SCL.
4: SDA and SCL = VSS to VDD at 400 kHz.
5: tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 in relation to
SCL.

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MCP3021
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k
TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).
Parameter Sym. Min. Typ. Max. Units Conditions
Input Leakage Current ILI -1 — +1 µA VIN = VSS to VDD
Output Leakage Current ILO -1 — +1 µA VOUT = VSS to VDD
Pin Capacitance CIN, — — 10 pF TA = 25°C, f = 1 MHz;
(all inputs/outputs) COUT (Note 2)
Bus Capacitance CB — — 400 pF SDA drive low, 0.4V
Power Requirements
Operating Voltage VDD 2.7 — 5.5 V
Conversion Current IDD — 175 250 µA
Standby Current IDDS — 0.005 1 µA SDA, SCL = VDD
Active Bus Current IDDA — — 120 µA Note 4
Conversion Rate
Conversion Time tCONV — 8.96 — µs Note 5
Analog Input Acquisition Time tACQ — 1.12 — µs Note 5
Sample Rate fSAMP — — 22.3 ksps fSCL = 400 kHz (Note 1)
Note 1: Sample time is the time between conversions after the address byte has been sent to the converter. Refer
to Figure 5-6.
2: This parameter is periodically sampled and not 100% tested.
3: RPU = Pull-up resistor on SDA and SCL.
4: SDA and SCL = VSS to VDD at 400 kHz.
5: tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 in relation to
SCL.

TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND.
Parameter Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature Range TA -40 — +125 °C
Extended Temperature Range TA -40 — +125 °C
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, SOT-23 JA — 256 — °C/W

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 MCP3021
TIMING SPECIFICATIONS
Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TA = -40°C to +85°C.
Parameter Sym. Min. Typ. Max. Units Conditions
I2 C Standard Mode
Clock Frequency fSCL 0 — 100 kHz
Clock High Time THIGH 4000 — — ns
Clock Low Time TLOW 4700 — — ns
SDA and SCL Rise Time TR — — 1000 ns From VIL to VIH (Note 1)
SDA and SCL Fall Time TF — — 300 ns From VIL to VIH (Note 1)
Start Condition Hold Time THD:STA 4000 — — ns
Start Condition Setup Time TSU:STA 4700 — — ns
Data Input Setup Time TSU:DAT 250 — — ns
Stop Condition Setup Time TSU:STO 4000 — — ns
Stop Condition Hold Time THD:STD 4000 — — ns
Output Valid from Clock TAA — — 3500 ns
Bus Free Time TBUF 4700 — — ns Note 2
Input Filter Spike Suppression TSP — — 50 ns SDA and SCL pins (Note 1)
I2C Fast Mode
Clock Frequency FSCL 0 — 400 kHz
Clock High Time THIGH 600 — — ns
Clock Low Time TLOW 1300 — — ns
SDA and SCL Rise Time TR 20 + 0.1CB — 300 ns From VIL to VIH (Note 1)
SDA and SCL Fall Time TF 20 + 0.1CB — 300 ns From VIL to VIH (Note 1)
Start Condition Hold Time THD:STA 600 — — ns
Start Condition Setup time TSU:STA 600 — — ns
Data Input Hold Time THD:DAT 0 — 0.9 ms
Data Input Setup Time TSU:DAT 100 — — ns
Stop Condition Setup Time TSU:STO 600 — — ns
Stop Condition Hold Time THD:STD 600 — — ns
Output Valid from Clock TAA — — 900 ns
Bus Free Time TBUF 1300 — — ns Note 2
Input Filter Spike Suppression TSP — — 50 ns SDA and SCL pins (Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.
2: Time the bus must be free before a new transmission can start.

THIGH VHYS
TF TR

SCL TSU:STA
TLOW THD:DAT TSU:DAT TSU:STO
SDA
THD:STA
IN TSP
TBUF
TAA
SDA
OUT

FIGURE 1-1: Standard and Fast Mode Bus Timing Data.

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MCP3021
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.

0.25
1 0.251
0.20
0.8 0.20
0.8
0.15
0.6 0.15
0.6
Positive INL
0.10
0.4 0.10
0.4 Positive INL

INL (LSB)
0.005
0.2 0.005
INL (LSB)

0.2
0 0
-0.005
-0.2 -0.005
-0.2
-0.10
-0.4 Negative INL -0.10
-0.4
-0.15
-0.6 Negative INL
-0.15
-0.6
-0.20 -0.20
-0.8
-0.8
-0.25 -0.25
-1
-1
0 100 200 300 400
0 100 200 300 400
I2C Bus Rate (kHz)
2
I C Bus Rate (kHz)

FIGURE 2-1: INL vs. Clock Rate. FIGURE 2-4: INL vs. Clock Rate
(VDD = 2.7V).

0.25
1 0.25
1
0.20
0.8 0.20
Positive INL 0.8
0.15
0.6 0.15
0.6
0.10
0.4 0.10
0.4
Positive INL
0.005
0.2 0.005
INL (LSB)

0.2
INL (LSB)

0 0
-0.005
-0.2 -0.005
-0.2
-0.10
-0.4 Negative INL -0.10
-0.4 Negative INL
-0.15
-0.6 -0.15
-0.6
-0.20 -0.20
-0.8
-0.8
-0.25 -0.25
-1
-1
2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5
VDD (V) VDD (V)

FIGURE 2-2: INL vs. VDD - I2C Standard FIGURE 2-5: INL vs. VDD - I2C Fast Mode
Mode (fSCL = 100 kHz). (fSCL = 400 kHz).

0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
INL (LSB)

0.1 0.1
INL (LSB)

0 0
-0.1 -0.1
-0.2 -0.2
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
0 256 512 768 1024 0 256 512 768 1024
Digital Code Digital Code

FIGURE 2-3: INL vs. Code FIGURE 2-6: INL vs. Code
(Representative Part). (Representative Part, VDD = 2.7V).

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 MCP3021
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.

0.25
1 0.25
1
0.20
0.8 0.20
0.8
Positive INL
0.15
0.6 0.15
0.6
Positive INL
0.10
0.4 0.10
0.4
0.005
0.2 0.005
INL (LSB)

0.2

INL (LSB)
0 0
-0.005
-0.2 -0.005
-0.2
-0.10
-0.4 Negative INL -0.10
-0.4
-0.15
-0.6 -0.15
-0.6 Negative INL
-0.20
-0.8 -0.20
-0.8
-0.25
-1 -0.25
-1
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Temperature (°C) Temperature (°C)

FIGURE 2-7: INL vs. Temperature. FIGURE 2-10: INL vs. Temperature
(VDD = 2.7V).

1
0.25 1
0.25
0.20
0.8 0.8
0.20
0.15
0.6 0.15
0.6
0.10
0.4 Positive DNL 0.10
0.4
DNL (LSB)

0.005

DNL (LSB)
0.2 0.005
0.2 Positive DNL
0 0
-0.005
-0.2 -0.005
-0.2
-0.10
-0.4 -0.10
-0.4 Negative DNL
Negative DNL
-0.15
-0.6 -0.15
-0.6
-0.20
-0.8 -0.20
-0.8
-0.25
-1 -0.25
-1
0 100 200 300 400 0 100 200 300 400
I2C Bus Rate (kHz) 2
I C Bus Rate (kHz)

FIGURE 2-8: DNL vs. Clock Rate. FIGURE 2-11: DNL vs. Clock Rate
(VDD = 2.7V).

1
0.25
1
0.25
0.20
0.8
0.20
0.8
0.15
0.6 0.15
0.6
0.10
0.4 Positive DNL
0.10
0.4 Positive DNL
DNL (LSB)

0.005
0.2 0.005
DNL (LSB)

0.2
0 0
-0.005
-0.2 -0.005
-0.2
-0.10
-0.4 Negative DNL -0.10
-0.4
Negative DNL
-0.15
-0.6 -0.15
-0.6
-0.20
-0.8 -0.20
-0.8
-0.25 -0.25
-1
-1
2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5
VDD (V) VDD (V)

FIGURE 2-9: DNL vs. VDD - I2C Standard FIGURE 2-12: DNL vs. VDD - I2C Fast
Mode (fSCL = 100 kHz). Mode (fSCL = 400 kHz).

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MCP3021
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.

0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2

DNL (LSB)
DNL (LSB)

0.1 0.1
0 0
-0.1 -0.1
-0.2 -0.2
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
0 256 512 768 1024 0 256 512 768 1024

Digital Code Digital Code

FIGURE 2-13: DNL vs. Code FIGURE 2-16: DNL vs. Code
(Representative Part). (Representative Part, VDD = 2.7V).

0.25
1 1
0.25
0.20
0.8 0.20
0.8
0.15
0.6 0.15
0.6
0.10 0.10 Positive DNL
0.4 Positive DNL 0.4
0.005 DNL (LSB) 0.005
DNL (LSB)

0.2 0.2
0 0
-0.005
-0.2 -0.005
-0.2
-0.10
-0.4 -0.10
-0.4 Negative DNL
Negative DNL
-0.15
-0.6 -0.15
-0.6
-0.20
-0.8 -0.20
-0.8
-0.25
-1 -0.25
-1
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Temperature (°C) Temperature (°C)

FIGURE 2-14: DNL vs. Temperature. FIGURE 2-17: DNL vs. Temperature
(VDD = 2.7V).

0 0 0.251
fSCL = 100 kHz & 400 kHz
-0.025
-0.1 0.225
0.9
-0.05
-0.2 0.20.8
-0.075
-0.3 0.175
Offset Error (LSB)

0.7
Gain Error (LSB)

-0.1
-0.4 0.15
0.6
Fast Mode
-0.125
-0.5 (fSCL=100 kHz) Standard Mode 0.125
0.5
-0.15 (fSCL=400 kHz)
-0.6 0.10.4
-0.175
-0.7 0.075
0.3
-0.2
-0.8 0.05
0.2
-0.225
-0.9 0.025
0.1
-0.25
-1 0 0
2.5 3 3.5 4 4.5 5 5.5
2.5 3 3.5 4 4.5 5 5.5
VDD (V) VDD (V)

FIGURE 2-15: Gain Error vs. VDD. FIGURE 2-18: Offset Error vs. VDD.

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 MCP3021
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.

1.5
0.375 2
0.50
0.45
1.8
0.2501
0.40
1.6

Offset Error (LSB)

0.35
1.4
Gain Error (LSB)

0.5
0.125
0.30
1.2 VDD = 5V
0 0.25
1
VDD = 2.7V
0.20
0.8
-0.125
-0.5 0.15
0.6
-0.250 0.10
0.4
-1
VDD = 5V 0.05
0.2 VDD = 2.7V
-0.375
-1.5 00
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Temperature (°C) Temperature (°C)

FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs.
Temperature.

84
96 84
96
VDD = 5V
72
84 72
84 VDD = 5V
60
72 60
72

SINAD (dB)
SNR (dB)

48
60 48
VDD = 2.7V 60
VDD = 2.7V
36
48 36
Y 48
24
36 24
36
12
24 12
24

120 120
1 10 1 10
Input Frequency (kHz) Input Frequency (kHz)

FIGURE 2-20: SNR vs. Input Frequency. FIGURE 2-23: SINAD vs. Input Frequency.

-120 84
96

-12
-24 72 VDD = 5V
84

-24
-36 60
72
SINAD (dB)
THD (dB)

-36
-48 VDD = 5V 48
60 VDD = 2.7V
-48 VDD = 2.7V
-60 36
48
-60
-72 24
36
-72
-84 12
24
-84
-96 120
1 10 -40 -30 -20 -10 0
Input Frequency (kHz) Input Signal Level (dB)

FIGURE 2-21: THD vs. Input Frequency. FIGURE 2-24: SINAD vs. Input Signal
Level.

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MCP3021
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.

10
12 10
12
9.95
11.95
9.5
11.5
9.90
11.9
9.85
11.85 VDD = 2.7V
9.0
11 VDD = 5V
ENOB (rms)

ENOB (rms)
9.80
11.8
9.75
11.75 8.5
10.5
9.70
11.7
8.0
10
9.65
11.65
9.60
11.6 7.7
9.5
9.55
11.55
9.50
11.5 7.0
9
2.5 3 3.5 4 4.5 5 5.5 1 10
VDD (V) Input Frequency (kHz)

FIGURE 2-25: ENOB vs. VDD. FIGURE 2-28: ENOB vs. Input Frequency.

96
84 10
VDD = 5 V
72
84 -10

60
72 -30

Amplitude (dB)
VDD = 2.7V
SFDR (dB)

48
60 -50

36
48 -70

24 -90
36
-110
12
24
-130
120
0 500 1000 1500 2000 2500
1 10
Input Frequency (kHz) Frequency (Hz)

FIGURE 2-26: SFDR vs. Input Frequency. FIGURE 2-29: Spectrum Using I2C
Standard Mode (Representative Part, 1 kHz
Input Frequency).

10 250
0
-10
-20 200
-30
Amplitude (dB)

-40
150
IDD (µA)

-50
-60
-70 100
-80
-90
-100 50
-110
-120
-130 0
0 2000 4000 6000 8000 10000 2.5 3 3.5 4 4.5 5 5.5

VDD (V)
Frequency (Hz)

FIGURE 2-27: Spectrum Using I2C Fast FIGURE 2-30: IDD (Conversion) vs. VDD.
Mode (Representative Part, 1 kHz Input
Frequency).

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 MCP3021
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.

200 100
180 90
160 80
140 70
120 60

IDDA (µA)
IDD (µA)

100 VDD = 5V 50 VDD = 5V

80 40
60 30
40 20 VDD = 2.7V
VDD = 2.7V
20 10
0 0
0 100 200 300 400 0 100 200 300 400
I2C Clock Rate (kHz) I2C Clock Rate (kHz)

FIGURE 2-31: IDD (Conversion) vs. Clock FIGURE 2-34: IDDA (Active Bus) vs. Clock
Rate. Rate.

250 100
90
200 80 VDD = 5V
VDD = 5V 70

IDDA (µA)
150 60
IDD (µA)

50
100 40
VDD = 2.7V
30
VDD = 2.7V
50 20
10
0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Temperature (°C) Temperature (°C)

FIGURE 2-32: IDD (Conversion) vs. FIGURE 2-35: IDDA (Active Bus) vs.
Temperature. Temperature.

100 60
90
50
80
70
40
60
IDDA (µA)

IDDS (pA)

50 30
40
30 20

20
10
10
0 0
2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5
VDD (V) VDD (V)

FIGURE 2-33: IDDA (Active Bus) vs. VDD. FIGURE 2-36: IDDS (Standby) vs. VDD.

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MCP3021
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
2.1 Test Circuit
1000

100

10 VDD = 5V
IDDS (nA)

0.1
10 µF 0.1 µF
0.01
2 k 2 k
0.001
VDD
0.0001 AIN SDA
-50 -25 0 25 50 75 100 125 MCP3021
Temperature (°C)
VSS SCL
VIN

FIGURE 2-37: IDDS (Standby) vs.

Temperature.
VCM = 2.5V
2
1.8
Analog Input Leakage (nA)

1.6
FIGURE 2-39: Typical Test Configuration.
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125
Temperature (°C)

FIGURE 2-38: Analog Input Leakage vs.

Temperature.

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 MCP3021
3.0 PIN FUNCTIONS 3.3 Serial Data (SDA)
Table 3-1 lists the function of the pins. SD is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
TABLE 3-1: PIN FUNCTION TABLE terminal, therefore, the SDA bus requires a pull-up
resistor to VDD (typically 10 k for 100 kHz and 2 k
Name Function for 400 kHz SCL clock speeds. Refer to Section 6.2
VDD +2.7V to 5.5V Power Supply “Connecting to the I2C Bus” for more information.
VSS Ground For normal data transfer, SDA is allowed to change only
AIN Analog Input during SCL low. Changes during SCL high are reserved
for indicating the Start and Stop conditions. Refer to
SDA Serial Data In/Out
Section 5.1 “I2C Bus Characteristics” for more infor-
SCL Serial Clock In mation.

3.1 VDD and VSS 3.4 Serial Clock (SCL)

The VDD pin, with respect to VSS, provides power to the SCL is an input pin used to synchronize the data trans-
device as well as a voltage reference for the conversion fer to and from the device on the SDA pin and is an
process. Refer to Section 6.4 “Device Power and open-drain terminal. Therefore, the SCL bus requires a
Layout Considerations” for tips on power and pull-up resistor to VDD (typically, 10 k for 100 kHz and
grounding. 2 k for 400 kHz SCL clock speeds. Refer to
Section 6.2 “Connecting to the I2C Bus” for more
3.2 Analog Input (AIN) information.
AIN is the input pin to the sample and hold circuitry of For normal data transfer, SDA is allowed to change
the Successive Approximation Register (SAR) con- only during SCL low. Changes during SCL high are
verter. Care should be taken in driving this pin. Refer to reserved for indicating the Start and Stop conditions.
Section 6.1 “Driving the Analog Input” for more Refer to Section 6.1 “Driving the Analog Input” for
information. For proper conversions, the voltage on this more information.
pin can vary from VSS to VDD.

 2003-2017 Microchip Technology Inc. DS20001805C-page 13

MCP3021
4.0 DEVICE OVERVIEW 4.2 Conversion Time (tCONV)
The MCP3021 employs a classic SAR architecture. The conversion time is the time required to obtain the
This architecture uses an internal sample and hold digital result once the analog input is disconnected
capacitor to store the analog input while the conversion from the holding capacitor. With the MCP3021, the
is taking place. At the end of the acquisition time, the specified conversion time is typically 8.96 µs. This time
input switch of the converter opens and the device uses is dependent on the internal oscillator and independent
the collected charge on the internal sample and hold of SCL.
capacitor to produce a serial 10-bit digital output code.
The acquisition time and conversion is self-timed using 4.3 Acquisition Time (tACQ)
an internal clock. After each conversion, the results are
The acquisition time is the amount of time the sample
stored in a 10-bit register that can be read at any time.
cap array is acquiring charge.
Communication with the device is accomplished with a
The acquisition time is, typically, 1.12 µs. This time is
2-wire I2C interface. Maximum sample rates of
dependent on the internal oscillator and independent of
22.3 ksps are possible with the MCP3021 in a continu-
SCL.
ous conversion mode and an SCL clock rate of
400 kHz. 4.4 Sample Rate
4.1 Digital Output Code Sample rate is the inverse of the maximum amount of
time that is required from the point of acquisition of the
The digital output code produced by the MCP3021 is a
first conversion to the point of acquisition of the second
function of the input signal and power supply voltage
conversion.
(VDD). As the VDD level is reduced, the LSB size is
reduced accordingly. The theoretical LSB size is shown The sample rate can be measured either by single or
below. continuous conversions. A single conversion includes
a Start bit, Address byte, two data bytes, and a Stop bit.
EQUATION This sample rate is measured from one Start bit to the
next Start bit.
V DD
LSB SIZE = ------------ For continuous conversions (requested by the Master
1024 by issuing an Acknowledge after a conversion), the
maximum sample rate is measured from conversion to
VDD = Supply voltage
conversion, or a total of 18 clocks (two data bytes and
two Acknowledge bits). Refer to Section 5.2 “Device
The output code of the MCP3021 is transmitted serially Addressing” for more information.
with MSB first, the format of the code is straight binary.

Output Code
11 1111 1111 (1023)
11 1111 1110 (1022)

00 0000 0011 (3)

00 0000 0010 (2)
00 0000 0001 (1)
00 0000 0000 (0)
AIN
.5 LSB
VDD-1.5 LSB
1.5 LSB
VDD-2.5 LSB
2.5 LSB

FIGURE 4-1: Transfer Function.

DS20001805C-page 14  2003-2017 Microchip Technology Inc.

 MCP3021
4.5 Differential Nonlinearity (DNL) 4.8 Gain Error
In the ideal ADC transfer function, each code has a uni- Gain error determines the amount of deviation from the
form width. That is, the difference in analog input volt- ideal slope of the ADC transfer function. Before the
age is constant from one code transition point to the gain error is determined, the offset error is measured
next. Differential nonlinearity (DNL) specifies the devi- and subtracted from the conversion result. The gain
ation of any code in the transfer function from an ideal error can then be determined by finding the location of
code width of 1 LSB. The DNL is determined by sub- the last code transition and comparing that location to
tracting the locations of successive code transition the ideal location. The ideal location of the last code
points after compensating for any gain and offset transition is 1.5 LSBs below full-scale or VDD.
errors. A positive DNL implies that a code is longer than
the ideal code width, whereas a negative DNL implies 4.9 Conversion Current (IDD)
that a code is shorter than the ideal width.
Conversion current is the average amount of current
4.6 Integral Nonlinearity (INL) over the time required to perform a 10-bit conversion.

Integral nonlinearity (INL) is a result of cumulative DNL 4.10 Active Bus Current (IDDA)
errors and specifies how much the overall transfer
The average amount of current over the time required
function deviates from a linear response. The method
to monitor the I2C bus. Any current that the device con-
of measurement used in the MCP3021 ADC to deter-
sumes while it is not being addressed is referred to as
mine INL is the end-point method.
Active Bus current.
4.7 Offset Error
4.11 Standby Current (IDDS)
Offset error is defined as a deviation of the code transi-
The average amount of current required while no con-
tion points that are present across all output codes.
version is occurring and no data is being output (i.e.,
This has the effect of shifting the entire A/D transfer
SCL and SDA lines are quiet).
function. The offset error is measured by finding the dif-
ference between the actual location of the first code
4.12 I2C Standard Mode Timing
transition and the desired location of the first transition.
The ideal location of the first code transition is located I2C specification where the frequency of SCL is
at 1/2 LSB above VSS. 100 kHz.

4.13 I2C Fast Mode Timing

I2C specification where the frequency of SCL is
400 kHz.

 2003-2017 Microchip Technology Inc. DS20001805C-page 15

MCP3021
5.0 SERIAL COMMUNICATIONS Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
5.1 I2C Bus Characteristics bytes being transferred between the Start and Stop
conditions is determined by the master device and is
The following bus protocol are defined: unlimited.
• Data transfer may be initiated only when the bus
is not busy. 5.1.5 ACKNOWLEDGE
• During data transfer, the data line must remain Each receiving device, when addressed, is obliged to
stable whenever the clock line is high. Changes in generate an Acknowledge bit after the reception of
the data line while the clock line is high will be each byte. The master device must generate an extra
interpreted as a Start or Stop condition. clock pulse that is associated with this Acknowledge
Accordingly, the following bus conditions are defined bit.
(refer to Figure 5-1). The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
5.1.1 BUS NOT BUSY (A) way that the SDA line is stable low during the high
Both data and clock lines remain high. period of the acknowledge-related clock pulse. Setup
and hold times must be taken into account. During
5.1.2 START DATA TRANSFER (B) reads, a master device must signal an end of data to
the slave by not generating an Acknowledge bit on the
A high-to-low transition of the SDA line while the clock last byte that is clocked out of the slave (NAK). In this
(SCL) is high determines a Start condition. All case, the slave (MCP3021) releases the bus to allow
commands must be preceded by a Start condition. the master device to generate the Stop condition.

5.1.3 STOP DATA TRANSFER (C) The MCP3021 supports a bidirectional 2-wire bus and
data transmission protocol. The device that sends data
A low-to-high transition of the SDA line while the clock onto the bus is the transmitter and the device receiving
(SCL) is high determines a Stop condition. All data is the receiver. The bus has to be controlled by a
operations must be ended with a Stop condition. master device that generates the serial clock (SCL),
controls the bus access and generates the Start and
5.1.4 DATA VALID (D) Stop conditions, whereas the MCP3021 works as a
The state of the data line represents valid data when slave device. Both master and slave devices can oper-
after a Start condition, the data line is stable for the ate as either transmitter or receiver, but the master
duration of the high period of the clock signal. device determines which mode is activated.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per
bit of data.

(A) (B) (D) (D) (C) (A)

SCL

SDA

START ADDRESS OR DATA STOP

CONDITION ACKNOWLEDGE ALLOWED CONDITION
VALID TO CHANGE

FIGURE 5-1: Data Transfer Sequence on the Serial Bus.

DS20001805C-page 16  2003-2017 Microchip Technology Inc.

 MCP3021
5.2 Device Addressing 5.3 Executing a Conversion
The address byte is the first byte received following the This section describes the details of communicating
Start condition from the master device. The first part of with the MCP3021 device. Initiating the sample and
the control byte consists of a 4-bit device code, which hold acquisition, reading the conversion data, and
is set to 1001 for the MCP3021. The device code is fol- executing multiple conversions are discussed.
lowed by three address bits: A2, A1, and A0. The
default address bits are 101. Contact the Microchip 5.3.1 INITIATING THE SAMPLE AND
factory for additional address bit options.The address HOLD
bits allow up to eight MCP3021 devices on the same
The acquisition and conversion of the input signal
bus and are used to determine which device is
begins with the falling edge of the R/W bit of the
accessed.
address byte. At this point, the internal clock initiates
The eighth bit of the slave address determines if the the sample, hold and conversion cycle, all of which are
master device wants to read conversion data or write to internal to the ADC.
the MCP3021. When set to a 1, a read operation is
selected. When set to a 0, a write operation is selected.
There are no writable registers on the MCP3021, there- tACQ + tCONV is
fore, this bit must be set to a 1 to initiate a conversion. initiated here

The MCP3021 is a slave device that is compatible with Address Byte

the 2-wire I2C serial interface protocol. A hardware
connection diagram is shown in Figure 6-2. Communi-
cation is initiated by the microcontroller (master SCL 1 2 3 4 5 6 7 8 9
device), which sends a Start bit followed by the address
byte.

ACK
On completion of the conversion(s) performed by the SDA 1 0 0 1 A2 A1 A0 R/W
MCP3021, the microcontroller must send a Stop bit to
Start
end the communication. bit
Device bits Address bits
The last bit in the device address byte is the R/W bit.
When this bit is a logic 1, a conversion is executed. Set-
FIGURE 5-3: Initiating the Conversion,
ting this bit to logic 0 also results in an Acknowledge
Address Byte.
(ACK) from the MCP3021, with the device then releas-
ing the bus. This can be used for device polling. Refer
to Section 6.3 “Device Polling” for more information.
tACQ + tCONV is
initiated here
START READ/WRITE
Lower Data Byte (n)
SLAVE ADDRESS R/W A
17 18 19 20 21 22 23 24 25 26
SCL

1 0 0 1 1 0 1
ACK

ACK

SDA D6 D5 D4 D3 D2 D1 D0 X X

Device code Address bits(1) FIGURE 5-4: Initiating the Conversion,

Continuous Conversions.
Note 1: Contact Microchip for additional address bits.

FIGURE 5-2: Device Addressing.

 2003-2017 Microchip Technology Inc. DS20001805C-page 17

MCP3021
The input signal is initially sampled with the first falling 5.3.2 READING THE CONVERSION DATA
edge of the clock following the transmission of a
logic-high R/W bit. Additionally, with the rising edge of After the MCP3021 acknowledges the address byte,
the SCL, the ADC transmits an Acknowledge bit (ACK the device transmits four 0 bits followed by the upper
= 0). The master must release the data bus during this four data bits of the conversion. The master device
clock pulse to allow the MCP3021 to pull the line low acknowledges this byte with an ACK = low. With the
(refer to Figure 5-3). following six clock pulses, the MCP3021 transmits the
lower six data bits from the conversion. The last two
For consecutive samples, sampling begins on the last bits are “don’t cares”, and do not contain valid data. The
bit of the lower data byte. Refer to Figure 5-6 for the master sends an ACK = high, indicating to the
timing diagram. MCP3021 that no more data is requested. The master
can send a Stop bit to end the transmission.

tACQ + tCONV is
initiated here
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCL
S
T S
A Address Byte Upper Data Byte Lower Data Byte T
R O
T P
A
S 1 0 0 1 A A A R
/ C D D D D A
C D D D D D D N
P
SDA 2 1 0 W K 0 0 0 0 9 8 7 6 K 5 4 3 2 1 0 X X A
K

Device bits Address bits

FIGURE 5-5: Executing a Conversion.

5.3.3 CONSECUTIVE CONVERSIONS

For consecutive samples, sampling begins on the fall-
ing edge of the last bit of the lower data byte. See
Figure 5-6 for timing.

tACQ + tCONV is tACQ + tCONV is

initiated here initiated here

fSAMP = 22.3 ksps (fCLK = 400 kHz)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCL
S
T
A
Address Byte Upper Data Byte (n) Lower Data Byte (n)
R
T
R A D D D A
C D D D D D D
A
SDA S 1 0 0 1 A2 A1 A0 / C
K 0 0 0 0 D
9 8 7 6 K 5 4 3 2 1 0 X X
C 0
K
W

Device bits Address bits

FIGURE 5-6: Continuous Conversion.

DS20001805C-page 18  2003-2017 Microchip Technology Inc.

 MCP3021
6.0 APPLICATION INFORMATION The analog input model is shown in Figure 6-1. In this
diagram, the source impedance (RSS) adds to the inter-
6.1 Driving the Analog Input nal sampling switch (RS) impedance, directly affecting
the time required to charge the capacitor (CSAMPLE).
The MCP3021 has a single-ended analog input (AIN). Consequently, a larger source impedance increases
For proper conversion results, the voltage at the AIN pin the offset error, gain error and integral linearity errors of
must be kept between VSS and VDD. If the converter the conversion. Ideally, the impedance of the signal
has no offset error, gain error, INL or DNL errors and source should be near zero. This is achievable with an
the voltage level of AIN is equal to or less than operational amplifier such as the MCP6022, which has
VSS + 1/2 LSB, the resultant code is 000h. Addition- a closed-loop output impedance of tens of ohms.
ally, if the voltage at AIN is equal to or greater than
VDD - 1.5 LSB, the output code is 1FFh.

VDD
Sampling
Switch
VT = 0.6V
RSS AIN SS RS = 1 k

CSAMPLE
VA CPIN ILEAKAGE = DAC capacitance
VT = 0.6V
7 pF ±1 nA = 20 pF

VSS
Legend
VA = signal source
RSS = source impedance
AIN = analog input pad
CPIN = analog input pin capacitance
VT = threshold voltage
ILEAKAGE = leakage current at the pin
due to various junctions
SS = sampling switch
RS = sampling switch resistor
CSAMPLE = sample/hold capacitance

FIGURE 6-1: Analog Input Model, AIN.

6.2 Connecting to the I2C Bus The number of devices connected to the bus is only
limited by the maximum bus capacitance of 400 pF. A
The I2C bus is an open collector bus, requiring pull-up possible configuration using multiple devices is shown
resistors connected to the SDA and SCL lines. This in Figure 6-3.
configuration is shown in Figure 6-2.

SDA SCL
VDD
PIC16F876
Microcontroller
Microcontroller

RPU RPU MCP3021 24LC01

SDA EEPROM
PIC®

AIN
SCL Analog MCP3021
Input 10-bit ADC
Signal
TC74
RPU is typically: 10 k for fSCL = 100 kHz Temperature
Sensor
2 k for fSCL = 400 kHz

FIGURE 6-2: Pull-up Resistors on I2C

Bus. FIGURE 6-3: Multiple Devices on I2C Bus.

 2003-2017 Microchip Technology Inc. DS20001805C-page 19

MCP3021
6.3 Device Polling 6.4.2 LAYOUT CONSIDERATIONS
In some instances, it may be necessary to test for When laying out a printed circuit board for use with
MCP3021 presence on the I2C bus without performing analog components, care should be taken to reduce
a conversion as described in Figure 6-4 where the R/W noise wherever possible. A bypass capacitor from VDD
bit in the address byte is set to a zero. The MCP3021 to ground must be used always with this device and
acknowledges by pulling SDA low during the ACK clock placed as close as possible to the device pin. A bypass
and then releases the bus back to the I2C master. A capacitor value of 0.1 µF is recommended.
Stop or repeated Start bit can be issued from the mas- Digital and analog traces should be separated as much
ter and I2C communication can continue. as possible on the board, with no traces running
underneath the device or the bypass capacitor. Extra
Address Byte precautions should be taken to keep traces with high-
frequency signals (such as clock lines) as far as
SCL 1 2 3 4 5 6 7 8 9 possible from analog traces.
The MCP3021 must be connected entirely to the ana-
log ground place as well as the analog power trace.
ACK

1 0 0 1 A2 A1 A0 0
SDA
The pull-up resistors can be placed close to the
Start Start
bit microcontroller and tied to the digital power or VCC.
Device bits Address bits R/W bit
Use of an analog ground plane is recommended in
MCP3021 response
order to keep the ground potential the same for all
FIGURE 6-4: Device Polling. devices on the board. Providing VDD connections to
devices in a Star configuration can also reduce noise
6.4 Device Power and Layout by eliminating current return paths and associated
errors (Figure 6-6). For more information on layout tips
Considerations when using the MCP3021 or other ADC devices, refer
to the Microchip Technology Application Note, “AN688
6.4.1 POWERING THE MCP3021
Layout Tips for 12-Bit A/D Converter Application”
VDD supplies the power to the device and the reference (DS00688).
voltage. A bypass capacitor value of 0.1 µF is recom-
mended. Adding a 10 µF capacitor in parallel is recom- VDD
mended to attenuate higher frequency noise that is Connection
present in some systems.

VDD

Device 4
VDD Device 1

10 µF 0.1 µF

VDD RPU RPU

SCL Device 3
AIN To
MCP3021
SDA Microcontroller
Device 2

FIGURE 6-5: Powering the MCP3021. FIGURE 6-6: VDD traces arranged in a
Star configuration in order to reduce errors
Note: When power-down of the MCP3021 is caused by current return paths.
needed during applications (after
power-up), it is highly recommended to
bring down the VDD to VSS level. This can
guarantee a Full Reset of the device for
the next power-up cycle.

DS20001805C-page 20  2003-2017 Microchip Technology Inc.

 MCP3021
6.4.3 USING A REFERENCE FOR
SUPPLY
The MCP3021 uses VDD as power and also as a refer-
ence. In some applications, it may be necessary to use
a stable reference to achieve the required accuracy.
Figure 6-7 shows an example using the MCP1541 as a
4.096V 2% reference.
VDD

VCC
0.1 µF 1 µF
MCP1541
CL
4.096V
Reference VDD RPU

Microcontroller
AIN SCL
MCP3021

To
SDA

FIGURE 6-7: Stable Power and

Reference Configuration.

 2003-2017 Microchip Technology Inc. DS20001805C-page 21

MCP3021
7.0 PACKAGING INFORMATION
7.1 Package Marking Information

5-Pin SOT-23

3 2 1

1 2 3 4

4 5

Part Number Address Option SOT-23

MCP3021A0T-E/OT 000 GP
MCP3021A1T-E/OT 001 GS
MCP3021A2T-E/OT 010 GK
MCP3021A3T-E/OT 011 GL
MCP3021A4T-E/OT 100 GM
MCP3021A5T-E/OT 101 GJ *
MCP3021A6T-E/OT 110 GQ
MCP3021A7T-E/OT 111 GR
* Default option. Contact Microchip Factory for other address
options.

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

DS20001805C-page 22  2003-2017 Microchip Technology Inc.

 MCP3021
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)

Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging

E1

p
B
p1 D

n 1

A A2

 A1
L


Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 5 5
Pitch p .038 0.95
Outside lead pitch (basic) p1 .075 1.90
Overall Height A .035 .046 .057 0.90 1.18 1.45
Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30
Standoff § A1 .000 .003 .006 0.00 0.08 0.15
Overall Width E .102 .110 .118 2.60 2.80 3.00
Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75
Overall Length D .110 .116 .122 2.80 2.95 3.10
Foot Length L .014 .018 .022 0.35 0.45 0.55
Foot Angle  0 5 10 0 5 10
Lead Thickness c .004 .006 .008 0.09 0.15 0.20
Lead Width B .014 .017 .020 0.35 0.43 0.50
Mold Draft Angle Top  0 5 10 0 5 10
Mold Draft Angle Bottom  0 5 10 0 5 10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-178
Drawing No. C04-091

 2003-2017 Microchip Technology Inc. DS20001805C-page 23

MCP3021
NOTES:

DS20001805C-page 24  2003-2017 Microchip Technology Inc.

 MCP3021
APPENDIX A: REVISION HISTORY

Revision C (January 2017)

The following is the list of modifications:
• Added a note to Section 6.4.1 “Powering the
MCP3021”.
• Updated Figure 6-5.
• Fixed Section 7.1 “Package Marking Informa-
tion” format to reflect the correct package mark-
ing as “1 2 3 4” instead of “1 10 10 10”.

Revision B (January 2013)

• Added a note to each package outline drawing.

Revision A (June 2003)

• Original Release of this Document.

 2003-2017 Microchip Technology Inc. DS20021805C-page 25

MCP3021
NOTES:

DS20021805C-page 26  2003-2017 Microchip Technology Inc.

 MCP3021
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. XX X /XX Examples:

a) MCP3021A0T-E/OT: Extended, A0 Address,
Device Address Temperature Package Tape and Reel
Options Range
b) MCP3021A1T-E/OT: Extended, A1 Address,
Tape and Reel
Device: MCP3021T: 10-Bit 2-Wire Serial A/D Converter c) MCP3021A2T-E/OT: Extended, A2 Address,
(Tape and Reel) Tape and Reel
d) MCP3021A3T-E/OT: Extended, A3 Address,
Tape and Reel
Temperature Range: E = -40C to +125C
e) MCP3021A4T-E/OT: Extended, A4 Address,
Tape and Reel
Address Options: XX A2 A1 A0 f) MCP3021A5T-E/OT: Extended, A5 Address,
A0 = 0 0 0 Tape and Reel
A1 = 0 0 1 g) MCP3021A6T-E/OT: Extended, A6 Address,
Tape and Reel
A2 = 0 1 0
h) MCP3021A7T-IE/OT: Extended, A7 Address,
A3 = 0 1 1 Tape and Reel
A4 = 1 0 0
A5 * = 1 0 1
A6 = 1 1 0
A7 = 1 1 1
* Default option. Contact Microchip factory for other
address options

Package: OT = SOT-23, 5-lead (Tape and Reel)

 2003-2017 Microchip Technology Inc. DS20001805C-page 27

MCP3021
NOTES:

DS20001805C-page 28  2003-2017 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
ensure that your application meets with your specifications. CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
MICROCHIP MAKES NO REPRESENTATIONS OR KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries.
arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company,
devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A.
suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
intellectual property rights unless otherwise stated. CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
Microchip received ISO/TS-16949:2009 certification for its worldwide the U.S.A.
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California Silicon Storage Technology is a registered trademark of Microchip
and India. The Company’s quality system processes and procedures Technology Inc. in other countries.
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and GestIC is a registered trademark of Microchip Technology
analog products. In addition, Microchip’s quality system for the design Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
and manufacture of development systems is ISO 9001:2000 certified.
Inc., in other countries.
All other trademarks mentioned herein are property of their

QUALITY MANAGEMENT SYSTEM respective companies.

© 2003-2017, Microchip Technology Incorporated, All Rights
CERTIFIED BY DNV Reserved.
ISBN: 978-1-5224-1290-8
== ISO/TS 16949 ==

 2003-2017 Microchip Technology Inc. DS20001805C-page 29

 Worldwide Sales and Service
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