B.Tech “apt 2025 ARCHITECTURE A ANIZATION ¢ COMPUTER ORG! N), AISDS, AI&ML, csp) c$), CSE(S), CSE ) BS, CSIT, CE(SE), CSE( " | (Bommen to GSE, CSBS, . Pimers Howes a i sists of Part A Part Be aes en aah ree ich caries 25 anaes, In Part Ay Answer all questions (i) Pare is compulsory ion fe it. Bach question carries 10 marks and ma one question from each unit ns ii) Part B, Answer any one qt OO Qaseat questions, Max. NaN PART-A. (25 Marks) Paget fa) Whatisacomputer? —s al . 4 iy Explain functionalities of CPU. feat et 1 @ (©) Whatare differant addressing modes? Wi Poa as (@)__ Discuss about any two types of instruction formats. ua ‘0 8a és (e) Give an example of decimal representation. tt Poste ; @® Explain about BCD adder. it Page ae i (@) Whats magnetic tape? tue Pane 4 (h) Describe parallel priority interrupt. AV, Page No, 1350 as @ What sre conditions for incoherence? + (Unit, Page No, 12 03 Q@) Whatare cisc characteristics? (Unit-V, Page No. 158,09) 3. @) PART-B (50 Marks ) ‘2 (a) Explain about computer design and architecture. (Unit-, Page No. 3,04 (0) What are computer registers? Explain, (Unit, Page No. 25, 0 ¢ a OR 3. (a) Discuss about shift microoperations in detail, (nit, Page No.20,02)] 4. (a (©) List and explain about memory-reference instructions. (Unit, Page No. 35,032 4. (@). What are shif instructions? Explain with suitable examples. (Unitll, Page No. 73,081 ¢ (©) Define control memory. Explain. (Units, Page No.48,0) 5. - OR 5. (a) Explain about microinstruction format in detail, (Unit-tl, Page No. 51,8 ¢ (b) What are RISC instructions? Explain, : Page Ne. 158.00} 5 6. _{@) Discuss about complements in data representation, (Unit A, Page No. 86,08) (0) Explain decimal arthmetic.operations with examples, (Unit.I, Page No. 113 051 ( Ree 7. (@) , Describe fixed-point representation in detail ait) % on . No. 88. (b) Discuss about division algorithms with examples, vf H reset 8 (6) Explain hardware organization and match logic of associative nit Page N™ memory. 508] 8 (6) What are various modes of transfer? Explain, Nee fee a watalt . nit AV, ; OR 9. Discuss about direct mapping and sat asso : 8 10. Explain the following: sssociative mapping, (univ, Page Ho. 48. (a). Interprocessor arbitration 73,088 + (0) , Four-segment instruction pipeline, (Unit-V, Page me 54,08 : (Unit-v, Page No- ‘V1. Explain the following: Bee {a) Interprocess communicatior ° © (b) Array processors: "and synchronization ‘WARN SPECTRUM @LL-IN-ONE JOURNAL. FOR’ ENG INEERING STUDENTS *Qp.2 COMPUTER ORGANIZATION AND ARCHITECTURE [JNTU-HYDERABAD] Code No: 153AG Sgr eae Jawaharlal Nehru Technological University Hyderabad R 1 8 B.Tech Il Year | Semester Examinations Solution: August/September - 2022 COMPUTER ORGANIZATION AND ARCHITECTURE (Commonto CSE, CSBS, CSIT, CSE(SE), CSE(CS), CSE(AIML), CSE(OS), CSE(N)) Time: 3 Hours Max. Marks: 75 nee ce Solutions 1. @_ Whatis the difference between Computer Organization and Computer + Architecture? " (Units, Page No. 6, 07) (©) "Write a short note on instruction code format. *. (Unit, Page No, 23, 024) 2. (@).» Explain the format of Register reference instructions and their functionalitics. (Unit4, Page No. 34, 031) (6) Draw and explain the flowchart for interrupt cycle. (Unit, Page No. 41, 038) 3. (a) Define the following terms: (Control memory (ii) Address sequencing. (Units, Page No. 49, 03) (8) Explain about the microinstruction format with neat sketch. (Unit, Page No. 51, 05) 4. (a) Explain about various addressing modes. (Unit-ll, Page No. 66, 020) () Briefly explain about General purpose registers and Flag registers. (Uaitl, Page No. 61, 014) 5. ‘(a). Explain the flow chart for addition operation with sign-magnitude data. (Unit-lll, Page No. 97, 027) (b) Perform (-25) + (-10) in binary with negative numbers in 2's complement. (Unitdll, Page No. 99, 0.28) 6 (a). Explain the Booth’s algorithm for signed multiplication. (Unit, Page No. 100, 031) *(b) Draw the flowchart for floating point division. (Unit-IIl, Page No. 111, 045) 7. (a) ' Explain the block diagram of 1/0 interface. (Unit-1V, Page No. 126, 05) (b). Write a short note on Cache memory. (Unit-1V, Page No. 147, 032) 8. (@)_Explain about instruction pipelining with an example, (Unit-V, Page No. 164, 09) (®) Discuss about the serial arbitration technique, (Unit-V; Page Np. 179, 026)Code No : 153AG Zz Jawaharlal Nehru Technological University Hyderabad B.Tech Il Year | Semostor Examinations . Em March + 2022 ¥ COMPUTER ORGANIZATION AND ARCHITECTURE (Common to CSE, CSBS, CSIT, CSE(SE), CSE(CS), CSE(AIML), CSE(DS), CSE(N)) Time: 3 Hours Max. Nia "Answer any five questions All questions carry equal marks os Solutiy 1. (@)< Explain in detail’computer design and computer architecture. + (Unit, Page No.3 (b) Explain in detail life cycle of instruction. (Unit-, Page No. 31, 2.» Explain the following, (a) Register transfer. (b) Input-Output and interrupt. : (Units, Page No. 44,1 3. __ Explain in detail various types of addressing modes with examples. (Unit-tl, Page No. 66,¢ 4) (a) Explain in detail about data transfer instructions. (Unit-Il, Page No. 71,0 (6) Discuss the various types of instruction formats. (Unit. Page No. 63,0 5. (@_Explain floating point representation of decimal numbers. (Unit.I1, Page No. 91,0 (b) Explain the decimal addition operation with a neat diagram. (Unit-II1, Page No. 116.0 Explain the subtraction op¢ration with signed 2’s complement data. (Unit-Ill, Page No. 95.0 @ (b) Explain in brief fixed-point data representation. (ait-ill, Page No. 88.0 7. (a)_ Explain the working process of DMA. (units, Page No. 136. (&) Compare cache and main' memory. | unit, Page No. 183: a 1! {Unit.V, Page No- 181.0 8. (a) Explain in brief inter-processor communication. (b) Discuss the characteristics of multi-processors.: -HYDERABAD] QP. COMPUTER ORGANIZATION AND ARCHITECTURE: [JNTU-HYDEI eee eee ee Code No : 153AG R 1 ; Jawaharlal Nehru Technological University Hyderabad Rn B.Tech Il Year |, Semester Examinations September - 2021 COMPUTER ORGANIZATION AND ARCHITECTURE (Computer Science and Engineering ) : Time: 3 Hours Max, Marks: 75 Answer any five questions All questions carry equal marks Solutions 1. @)_-Draw the block diagram of a digital computer and explain the purpose of cach pait, (Unit-t, Page No. 2, 02) (©), Design a 4-bit combinational circuit decrementer using four full-adder circuits, . (Unit, Page No. 13, 017) What are the common fields found in instruction format? Explain various instruction formats based on types of CPU organization, (Unit-l, Page No. 66, 019) 3. Perform the arithmetic operation (+41) + (-13) and (41) ~ (-13) in binary using signed 2's complement representation for negative numbers. (Unitll, Page No. 98, 028) 4 @ _ Draw the block diagram of a typical DMA controller and explain, (Unit1V, Page No. 136,.040) (©) Explain Daisy-Chain priority interrupt in detail (Unit-1V, Page No. 134, 016) 5 @_, Construct a diagram for a 4 * 4 omega switching network. Show the switch setting required to connect input 3 to output. (Uni |. Page No. 173, 022) ©),. Give a brief note on mutual exclusion with a semaphore. (nit Page No. 182, 030) 6. @) “Differentiate between computer organization and computer architecture. (Unit, Page No. 6, 07) (©) Explain the Stored Program organization in detail. Unit, Page No. 24, 025) 7. Explain the microprogram sequencer for a control ‘memory with a neat diagram: (Unitdl, Page No. 58, 012) 8. Derive an algorithm in flowchart form for adding and subtracting two fixed-point 2’s complement ~ binary numbers when negative numbers are in the signed.2" representation, (Unitttl, Page No. 96, 023)Exam'Question Papers witn somone 53AG 8 R Ci} Jawaharlal Nehru Technological University Hyderabad B.Tech Il Year | Semester Examinations March ~ 2021 COMPUTER ORGANIZATION AND ARCHITECTURE (Computer Science and Engineering ) Qi Time: 3 Hours Max. My 7 ‘Answer any five questions - All questions carry equal marks ret oluto| 1. © (a) Discuss the functional units of a digital computer. Unit, Page Ka (6) | Demonstrate construction of a common bus system with multiplexers. (Units, Page uo 2. -(@) Design a 4-bit combinational circuit decrementer using four full-adder circuits. : : (Wnit-, Page No.1 (0) What is the difference between a direct and an indirect address instruction? How many references to memory are needed for cach type of instruction to | bring an operand into a processor register? (Units, Page No. 23 EL (a) Discuss the need of memory stack and stack limits. (Unit-ll, Page No. 6 (b) Explain the general register organization of the processor. (Unit, Page No.8 4. Explain addition and subtraction of floating-point numbers with an example and 5 necessary flowchart. . . * (Unit-lll, Page No. 113, 5. * (a) Atwo way set associative cache has lines of 16 bytes and a total size of 8 K bytes. The 64 Mbytes main memory is byte addressable. Show the format of main memory address. (Unit-AV, Page No. 146, (b) How does SDRAM differ from ordinary DRAM? (Unit-V, Page No. 18 6. (@_ Explain the major differences between the central computer and peripheral. How to resolve these differences? (Unit-V, Page Mo. 124" (b) Discuss the Strobe control method of Asynchronous data transfer. (Unit, Page No.2 7. © /(@) Whats parallel processing? Explain Flynn’s classification of computer. (Unit V, Page No.6 (b) Illustrate vector operations and vector processing. z (unit.v, Page No. 1514 8 (a) Discuss about RISC Pipeline. (Unitv, Page No- 168 (b) Whats cache coherence problem? Discuss solutions for it. tuniev, pose Ho. 16|> (R23) MODEL | 1 4 PAPER — B.Tech, II Year | Somostor Examination COMPUTER ORGANIZATION AND ARCHITECTURE. (Common to CSE, CBE(AI&HML)CE(SE), CBE(CS), CSE(D8), CSE(N), CSD, CSBS, AIDS and AI&ML) Time: 3 How ie rs s Max. Marks: 60 - PART-A_ (10% 1 = 10 Marks) Solutions 1. (a) Dofine digital computer. (Unit 4, Page No. 45, 01) (b) List the two instructions for Interrupt Enable Flip-flop (IEN). (Unit-, Page No.45, 09) (€) List the major operations performed by sequencer on next address generator. M4 (Unit-lI, Page No. 79, 03) (4) Define contro! memory, (Unit-ll, Page No. 79, 06) (e) Write about decimal number system. : (Unit-ll, Page No. 120, Q1) (f) Find 9's complement (25.639),,. {Unit-Il!, Page No. 120, 05) IV. Page No. 155, 02) (9) What do you mean by FIFO Buffer? (Uni (h) What is the purpose of designing data communication processor? : (Unit1V, Page No. 155, 04) (i) _ List two advantages of pipeline processing? (Unit-V, Page No. 185, 02) (j) | Write a short note on cache coherence. (Unit-V, Page No. 185, 07) . PART-B (5 10=50 Marks) 2. (a) List and explain the functional units of a computer. . “ (Unit, Page No. 2, 02) (b) Give the block diagram for registers and explain. Also, discuss about memory transfer operations. (Unit-1, Page No. 7, 010) OR (Unit-l, Page No. 20, 021) 3. (a) Discuss about shift microoperations in detail. . (Unit-, Page No. 31, 030) (6) Draw and explain about the instruction cycle state diagram. 4. (a) Describe how mapping from instruction code to microinstruction is done. Also, explain.about subroutines. (b) Discuss the decoding of microoperation fields. OR (Unit-I, Page No. 43, 04) (Unit-ll, Page No. 57, 011) 5. Discuss in detail about all the microinstruction formats. Also explain various microinstruction fields. (us 6 (a) Convert (19.625), equivalents. (b) Explain floating-point representation of decimal numbers. oR addition operation with sign magnitude 1, Page No. 51, 06) into its binary, octal and hexadecimal (Unit-ll, Page No. 84, 05) (Unit-IIl, Page No. 91, 016) 7. (a) Explain the flow chart for * data. (b) Explain the decimal addi SPECTRUM ALL-IN-ONE JOURNAL FOR EN Page No. 97, 027) No. 116, 050) ition operation with a neat diagral10. 1. Tay Explain the major differences between the central computer and peripheral. How to resolve these differences? (0) What are various modes of transfer? Explain. oR (a) Show the memory hierarchy and give the brief explanation. (b): With the help of a neat diagram explain the match logic for: - ‘one word of associative memory. (a) Differentiate between RISC and CISC characteristics. (0) What is pipelining? Explain pipeline processing with an example. OR (a) Give the timing diagram of instruction pipeline. (b) Write short notes on vector processing. COMPUTER ORGANIZATION AND ARCHITECTURE LNTU-HYp, ER q (Unit i May (Unit.tv, p, No, i} 13, y nit-V, Page Nast oN (Unit AV, Pag hy 4 i (Unit-V, Page No, " (Unit, Page, (Unit-V, Pago No.1, (nit-V, Page No, 167,Médel Questicii Papers with Solutions ue eee oe ape amnanennnmemaniininneinnea cn dainicailscatcesta MODEL B.Tech. II Year | Somoster Examination FAPER COMPUTER ORGANIZATION AND ARCHITECTURE (Common to CSE, CSE(AI&ML)CE(SE), CSE(CS), CSE(DS), CSE(N), CSD, CSBS, AIZDS and AILML) Time: 3 Hours - Max. Marks: 60 ) (b) © (@) (e) o () (hy @ o (b) (b) (b) (b) (b) PART-A (10x 1=10 Marks) Write short notes on three state buffers. Write about timing signals. Wo, 45, 010) What do you mean by subroutines? No. 79, 01) What are the three basic fields present in an instruction? 1, Page No. 79, 05) What is 10's complement? (Unit-I11, Page No. 120, 02) What do'you mean by overflow? it II, Page No. 120, 08) What do you mean by associative memory? {Unit4V, Page No. 155,05} - Define Hit Ratio. . (Unit-IV, Page No. 155, 07) What do you mean by super computer? (Unit-V, Page No. 185, 03) Write in brief about RISC. (Unit-v, Page No. 185, 05) PART-B (5 10=50 Marks ) Explain the components of the computer system. brief about Arithmetic Microoperations. OR (Unit, Page No. 5, 05) Discuss (Unit-l;Page No. 10, 013) Define instruction code and operation code. With the help of examples, explain direct and indirect addressing. List and explain about memory-reference instructions. Explain about Stack Organization in detail Illustrate the use of different addressing modes with numerical example. (Units, Page No. 23, 024) (Unit, Page No. 35,032) (Wnit-tl, Page No. 62, 015) (Unit-I, Page No. 69, 022) OR (Unit-ll, Page No. 58, 013) Describe briefly the general register organization. (Unit-ll, Page No. 74, 027) Discuss in brief about program control instructions. Explain how a binary number can be converted to an octal and a hexadecimal number. Perform arithmetic on the following numbers using their binary equivalents. () 544 -5+4 (Unit-tll, Page No. 82, 02) diy 5-4 . (iv) -5-4. (Unit-ll, Page No. 89, 013) oR , ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS TSPECTRGCOMPUTER ORG (a) Explain Booth's multiplication algorithm with example. MP.4 (b), Explain about BCD adder. (a) Explain the block diagram of VO interface. 8. (©) What is dalsy-chaining? Explain with neat skétch. OR 9. (@)_ Drawand explain the block diagram of RAM and ROM chips. (bo) Write a short note on cache memory. 10: (a)) Explain the array processors. * () Discuss the characteristics of multi-processors. OR 1. ji ; , 41. (@) Construct a diagram for a 4 * 4-omega switching network. Show the switch setting required to connect input 3 to output. (b). What is a system bus? What are the different signal line: associated with a system bus? Explain i ANIZATION AND ARCHITECTURE lUNTU., (Un “ YOR, (Unt1V, Page y i , WnitV, Page y. "Pago, 14 (Unit-tv, Pago Na (Unit, Page no, i nit, Pago Noy (Unit-V, Pago no, my (Unit-V, Page No, My (Unit, Page No. 144(2 B.Tech. II Year | Semester Examination COMPUTER ORGANIZATION AND AR‘ CSE(AISML)CE(SE), CSE(CS), CSE(DS), CSE(N), PAPERIOD CHITECTURE CSD, CSBS, Al&DS and AI&ML) | (common to CSE, Ffime: 3 Hours ‘ ‘Max. Marks: 60 PART-A (10x 1=10 Marks) Solutions (Unit, Page No. 45, 05) (a) Define instruction cede. (6) List the phases of an instruction cycle. (c) Define stack organization. i (a) Write about one-address instruction. (e) What do you mean by floating point representation? (0 Define fast multiplication circuit: (@) List two advantages of handshaking? (h) What do you mean by Direct Mapping technique? (i). Define speedup ratio. (What do you mean by snooping protocol. PART-B (5 * 10 =50 Marks) are register transfer logic languages? Explain few RTL with their actual functioning ‘on? Discuss in detail various types of mentation of (a), What statements for branching (b) What is a logic microoperati logic microoperations. Also give the hardware impler logic microoperations. : OR (@)_List various registers in a computer along with their purpose. lowchart for interrupt cycle. (b) Draw and explain the fl plain about the microprogrammed (a) Define control memory. Ex} control organization. (b) With the help of a block diagram, explain how do we select the address of control memory. oR (a) With the help of a block diagram explain the computer hardware configuration. (b) With the help of a diagram, explain the organization of microprogram sequencer for a control memo! ‘SPECTROM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS, (Units, Page No. 45, 07) (Unit-tl, Page No. 79, 04) (Unit-I1, Page No. 79, 08) (Unitll, Page No. 120, 03) rage No. 120, 06) (Uni (Unit-1V, Page No.'155, 1) {Unit1V, Page No. 155, 08) (Unit-V, Page No. 185, 01) (Unit-V, Page No. 185, 08) (Unit, Page No. 7, 03) (Unit-1, Page No. 16, 019) (Unit-, Page No. 25, 026) (Unit, Page No. 41, 038) (Unit-ll, Page No. 48, 01) (Unit-tl, Page No. 49, 03) (Unit-tl, Page No. 50, 05) {Unit-tl, Page No. 58, 012)AND ARCHITECTURE [yyy MP. COMPUTER. ORGANIZATION ne ~ 6 (a) Discuss about complements in dal = ‘puter arithmetic addition and subtraction an EF tl raved using signed magnitude data? Also provide its: , ita implementation. st, hardware imp! asi 4 i ng Booth's by-step multiplication process using B Trvailt ote Sieh ne felowing binary number are multiplied (7)* (43). (Unit, Page yy ql 4 i floating-point . flowchart to explain how two \EEE 754 f dy Sy ees ean be added, subtracted and multiplied. Assume single precision numbers. Give example for each. nit-tll, Page ‘1 8) (a)” Discuss the Strobe control method of Asynchronous data * aa transfer. (Unit-tV, Page Na, (b) Explain the working process of DMA. (Unit, Page ha, OR i 9. (a) Discuss in detail the two most common auxiliary memory devices used in computer systems. (Unit-1V, Page No, tq (0), Distinguish between the virtual memory and cache memory. Write the merits and demerits of virtual memory. (Unit1V, Page No.1 10. (a) Discuss about the serial arbitration technique. “(Unit-V, Page No.1 {) Explain in brief inter-processor communication. (Unit-v, Page No 1 OR : 11." What is cache coherence problem? Discuss about different cache coherence approaches. (Unit-V, Page No. 1~— a iment Computers, Register Transfer . guage and Micro Operations, Basic omputer Organization and Design Digital Computers: Introd Organization, Compt luction, Block Diagram of Digital Computer, Definition of Computer Seen om ter Design and Computer Architecture. any i ‘guage and Micro operations: Register Transfer Language, Register Transfer, Bus and Memory Transfers, Ari d + Arithmetic Mier :! Operations, Aritmetie logic St Un” OPetatens bese Mire Operon, SAH Mice Basic Computer 0: i oa es er rosnization and Design: Instruction Codes, Computer Registers Computer ‘ontrol, Instruction Cycle, Memory Reference Instructions, Input — Output ond Interrupt. GBIESTIVES |) Basic Block Diagram of Digital Computer Definitions of Computer Organization, Computer Design and Computer Architecture Various Register Transfer Symbols and RTL Statements Different Arithmetic, Logic and Shift Microoperations Format of Instruction and Operation Code Direct and Indirect Addressing ifferent Types of Computer Registers and Computer Instructions n Cycle Yarious Phases of Instru Configuration of Input — Output Flowchart of Interrupt Cycle. LLVKLKK LAS «@ fast electronic data processing device, which takes the input in the form of to its various memory elements and finally produces the result. ueture and behavior of the computer. The two basic computer d Harvard architecture. The term “register transfer" refers to a consequence in which, after the execution of a given microinstruction, the data is transferred to certain register(s). However, a mierooperation is defined os an operation which is performed on the information stored in the registers. The shift micro-operations are specifically employed for shifting the contents of a register to left or right position. Thus, the corithmetic, logic anc shift circuits can be combined Into che composite circuit with the help of « multiplexer to get the arithmetic logic shift unit. Instruction cofle Is a s that directs the computer to perform operations. It is divided Into two parts wherein each part has its own interpretation. The process of executing a program by allowing each instruction through @ cycle in a sequential manner Is known as Instruction cycle. emory-reference instructions are those Instructions whose execution requires the access of memory. f is an asynchronous event that halts the normal program execution and Moreover, an Interrup' diverts the program flow temporarily to an interrupted routine. ) Harvard Architecture _ Acomputer with a Harvard architecture of five different blocks. They are, A 1. Program memory unit 2. Data memory unit e 3. Input/Output unit 4, Data processing unit 5. Program control unit. All the instructions are stored in memory unit called a program memory unit. Th > is stored ina separate memory unit called dat unit. ‘The input-output unit, data processing ual program control unit have the same functionality * in Von Neumann architecture. Ina Harvard architecture, instructions 22° are stored in separate memories. Both of these me" may have varied word lengths, memory adit Jn addition, it also contains Accumulator (AC) and Multiplier Quotient (MQ) registers. These structures, timings and implementation technolo#™ Generally, the size of the data memory is $0” ‘ompared to that of the program (or instruction) meram memory Isa read o inet Mullonty Be tend roman ence Feeney in memory In a rend.write meme Whereas, ine de read OF Wrllen to the manutd Because the ory, od ‘rhe data and Program mem, nists Ory are co) pe central processing unit through pro, nected to | the hardws a Sant edn ra data and ear a ee eee eer are iy and the menvory through Are passed across | arithmet structions in order to perform the basic ane tereone,In 8 Ttarvard sven ePonaing | the tenet opel and inp ote (UO) crease Tt and anette a CHG | ee The thee internal setons that are eneally can 00 tthe same time, Tenautite lata from/to the biel leprae eur memo pitecture is Very fetes computer with a Register Bectio Itisacollection ofa bus (orany ; red to.a con ‘communication mechanism) and re iputer ene cru ths Gon etn Proemting Un (GPU i he baln of Wy, mer that I expat tr controling bb ing and executing most of the commands from a0 Neumann a Hr n-Neumann architecture, tht ae special ones ‘of memory units used, by iene following figure represents Harvard iene a ‘order to transfer the data with ectre- rvar speed. These registers are not considered as Ani the part of main memory, but they store the data or information temporarily and then pass it based ‘on the directions given by the control unit. (b) ALU Section: As the name suggest, arithmetic ‘and logic unit is responsible for performing many arithmetic related operations. When user supplies data for either addition, subtraction, multiplication or division ete, the processor initiates the arithmetic Gnd logic unit for further manipulations, For ‘example, fa usr intends to perform multiplication between two numbers. The processor initially fetches the required data Le., operands, operators te, and initiates the arithmetic and logic unit. AS seals the unit considers this data and accordingly performs the required computation By switching, PeroMMalues, Input and output of a special and eae ey fast circuitry are referred as registers and. Inge Out pees f+] Dain procesig] it (aris ‘Logs unt ‘Sanue] [Cont Controb adds | bas Instrtion bus jain the components of the computer 06. system. = Model Papert, 22(0) returns back the output . OR (Control Unit Seetion: The control wot though ooks quite simple, but forms the major ‘component, Explain functionalities of CPU. wee the entire computer. Its main function isto [RRELORY: Topies CPU) govern the activities of other functional devices. aie: ELBE CED, ato. ate) Tass done by tassmiting he a ‘ pi signals to various other unit e ‘The generic organization ofthe computer contains ais ovis es ofthese units and ; tee main components. They are inhibi em thir peavion inte ee i. CPU timing, Hence not granting full independence : tavother functional units which may Tead to 2, Memory subsystem degradation of system's performance. 3, YO subsystem. | 2. Memory Subsystem ; The generic computer organization is depictedin Combining two oF Ore memory ti, he tbe following figure. enhancing, ae camel of a memory “4 . sl M . i i ne ‘example, the 8*2 chips can be combined t© form an 8x44 memory: 18 such a system, the — a of the first chip are a pected 0 bits 3 and 2 OF HE whereas the data pins ‘second chip are connectey ee the data bus. Hence; BO chips. wil i anARCHITECT UNE LINTUHyp, Uy) i v ND Al COMPUTER ORGANIZATION At ere aT | be £ jon beween the computer and external, jevices. After the sary forthe a Pr yO devicesare newest Sead wane compute ‘petractons ae Te at a peated wi Be sored om the OUEDUE CANCE ater. They are used forthe trans the cut gene 20 Sion, ye oe ge semen the het Tcalion and computer Srchitecmeme Mf i from one somone the thes zat ita 7 Gi. What Is the difference bet 5 oN Me OR ‘ tor organization and computer architecture. “ye z pifferentiate betwoon computer org aan “ ys . n f coe differences between computer organization and computer architecture are as follows, tm A ‘ = meter Orgnniration Computer Archivectare 2 seed to connect the component the hardware | 1. | Computer architecture deals with the struq ranizati¢ ils eae behavior of the computer. components and their interconnection. Fi fl ‘Tr describes the functionality of the computer. 2. | It describes the design of the computer, Sd It includes instruction sets, instruction formal) data types, addressing modes. Fr 4, | It deals with the high-level design issues, + gt 5. | It coordinates between hardware and software 8 the system. Fs It defines the logical aspects of a system, ; While designing a system, computer achiters|| > is considered first. aa a i ansfer Language) Q8._ What is a microoperation? Write about register transfer language. Answer : Microoperation ; A microoperation is defined as an operation which is performed on the information stored in the regists| Registers are temporary storage devices. Microoperation is an elementary operation. Moreover, microoperatis| € or transfer binary information of a register. A digital system can be described by mentioning its internal hardware organization such 2s, (2) The registers available in a digital system and function of each register. | (©) ° A series of microoperations executed on the information av; (©) Acontrol that initiates a series of microoperations, Register Transfer Language such as shift, count, clear and load replac ailable in the registers. wala " . _ hich is described in a symbolic format instead of le guage”, ardware lo, “Transfers CUS such as gates that perform information The term language implies programmi symbols, programming language that specifies a particular computational poees™™ > Aregister transfer language is an a ‘This a system that indicates a sequ PI ‘ , am information among registers in a ropri ae aati ied ‘001 for explaining digital Computer's internal organi™™ microoperations in a symbolic form to carry out transfet ae syoR _prmerentate werween computer organization” rn and computer architecture are as follows, ‘and computer architecture, 5 tecture deals with th Seaton deals with the hardware | T- | Computer archi snag behavior of the computer. | 6" tr wiersoneton io es eects se compu |2.| 1 deco te devin of he comput as i inte istration vt, istruton fal Mtinchodes circuit design control signals, memory s I % oo eee - lypes. data types, addressing modes. g i goth os Tedeals with the low-level design issues. 1 deals with the high-level design issues, 0 5s OO MD hanes the componcats connection of «sys-| 5.| It coordinates between hardware and soften gi i aoe: the system, defines the physical aspects of a system, It defines the logical aspects of a system. While designing a system, computer architec ‘While designing a system, computer organization hitecture fi {EUREGISTER TRANSFER LANGUAGE AND micRO OPERATIONS 12:4 Mepistor Transfer Language 8. What is a microoperation? Write about register transfer language. Answer Microoperation ‘Armicrooperation is defined as an operation which is performed on the information stored in the T8385) i. Gi the lock diagram Registers are temporary storage devices. Microoperation is an elementary operation. Moreover, microoperia such as shift, count, clear and load replace or transfer binary information of a register. (aa. No, daca ‘A digital system can be described by mentioning its internal hardware organization such as, — (2) The registers available ina digital system and function of each register. bere (8) A series of microoperations executed on the information available in t information available in the registers. ‘cs Tater (©) Acontrol that initiates a series of microoperations. 4 s hi Register Transfer Language feat oat ase ae har Microopenaions canbe explained in terms of words but itis lengthy procedure, therefore symbol ae welt) A Stang get ‘explain information transfer between registers and other digital componen sh bit egisters and other digi nents, feat . ‘A microoperation transfer among registers which is describs . mat instead of RAE) Wag Raw te a8 eh ‘bed in a symbolic 1 th ‘The mictooperations applied to the hardware logic circuits such as gates form informat Wie circuits such as gates that perform infor a among registers, This is known as “Register Transter™ ‘The term language implies ‘oa plies programming language that specifies « particular computational proces & -Aregister transfer language isan appropriate tol fo ‘© Wis a system that indicates a sequence of micro information among registers in digital synteny & Symbolic form to carry out ta WARNING: KerexiPhotocopying of Metehe woe CRMGTAT Sa Ro Tana alto UABIE Tas RL0 logter nguages? Explain few RTL atatomente torn” wan thelr actual functioning. snehing anwer! Model Paper, a2(a) einer Transfer Logle Language (REL) The term “regiater transfer" yeriee In Which, after the exceutio, everotnatuetion, the data In trenena fegier(s) Here, InngUNge specify a wy {hing which certain predefined aymbots foaming nicto-instruetion, Hence, rey language refers 0 a standard logie font symbolic requences (mero. ‘given digital circultry, tefers to a, n of a given d to certain fandard logic are arranged ister transfer i ing which few ‘nstructions) are written in RTL Statements for Branching Few RTL statements for branching are represented below, 1, BROX: to the posi This statement causes branch or jump n*X’ ifan overflow occurs, 2, BRN X: This statement causes branch to the position *X? ifthe result is negative, RZ X: Thisstatement causes branch ‘X"ifresult = 0 4 BRP X: This statement causes branch to the location *X" if the result is positive, BRER, Ry s statement causes branch to the location *X*, if the content of register RI is equal to the content of register R2. palnaF Wanstor) aus wad Womloey Lestat! MeL Selts Q10. Give the block diagram for registers and oxplain. Also, discuss about memory transfor oporations. htothe position Answer Modo! perl, Q2(b) Register Transfer {many digital system hardware, the storage and ata transfers are predominant, For this purpose, registers ‘hat perform temporary data storage with the ability to ‘hitiotae the data bits are employed. The following diagram shows how the registers are rendered on. piece f paper, RI Figure (1): Abstra 76 View of a Register 543 21 0 R2 15: 0 R3 Figura (3): Showing the Range of Bits 3 16 15 0 RAH) [| RAC) Figure (4h: Divided into Two Hatves As shown in the above figures, capital letters, followed by numbers are used to designate registers. For ‘example in many systems, accumulator is designated by capital letter A. Bits of an n-bit register are numbered from 0 (right most) to n-1 (left most). Figure (1) shows 4 simple abstract view of a register. In figure (2) the individual bit positions of an 8-bit register can be identified, Figure (3) describes the range of values of 16-bit register. In figure (4) higher order bits (16-31) of register R4 is designated by H (for high byte) and the lower order bits (0-15) of register R4 is designated by L (for low byte), Memory Transfer Operations Memory read and memory write are the two ‘memory transfer operations. 1, | Memory Read Aread operation can be performed by transferring data from memory word M to its surroundings. A address register AR provides address to the memory unit. The data in the address register AR is sent to another register known as data register DR. Read Operation DR MAR] This read operation reads the data from the memory address specified in registerAR into data register DR. 2, Memory Write ‘A write operation is performed to store newly arrived information into the memory. ‘The data present in the data register DR is \ransferred to selected address of memory word M by performing write operation. Write Operation MIAR] © RL ‘This write operation writes the data in register RI to address selected by the addfess register AR into the memory word M,ON 8 . 5 : COMPUTER ORGANIZATION AND ARCHITECTURE (JNTU-Hy Q11. Tabulate various for transfers. With the help of an oxan, register transfer is implemented. i Answer : 7 Register Transfer Symbols In general, the CPU of a computer system is setup with number of general purpose registers. Here, every register in it has the property o store words which can be aecessed independently. Also, the other comp’ of the system can havo access to contents of any register. : Microoperations are specified as operations that are executed on data stored in register. This is carrey ‘upon the information stored in multiple registers. The ‘generated output is usually stored in destination rep, in other registers. i ‘A sequence of microoperations are performed to execute ont complete operation. For example, to suby two numbers the following sequence of microoperations has to be performed, 1... Load first number in register A. 2. Load second number in register B. " 3.) © Perform subtract microoperation. 4. Store the result in the destination register. 'As deseribed above it is possible to specify the sequence ‘of microoperations in words, but it invol Tengthy descriptive explanation. Hence, it is preferred to,use symbolic notations to describe the microoperatia “The following table lists the basic symbols used for register transfers. 2 f Symbol Description i Example Letter or letters | Designates a register PC, MAR, RI with numerals Parentheses () | Designates a part of aregister RI(O~ 15) : Bits 0~15 of RI ; RI(H) : Most significant half of register RI Arrow — Designates transfer of information RIC R2 : Comma, Separates two microoperations that are] RI <~ R2,R2<—RI performed simultaneously _| "As shown in the above table, symbol ‘«~’ is used to describe the transfer of information from one register another. Ri © R2 Destination__/4 Ree ssane register register “The above statement specifies the replacement of the contents of register RI by the contents of register R2 “This operation does not change the contents ofthe source register R2- : “The term register transfer signifies the availabilty of hardware logic cireuits which supports the transfer o! source register output to the input of destination register In addition to this, it iso specifies the ability of destination. register to support parallel load. A register transfer language aso allows to specify control conditions in the statement. Inorder to specify control conditions, ituses control variable along witha colon at the left most side of the statement as shown below. . : a CRI @ R2 Control_7 variable Here, Cis used as'a control variable. It is basically a boolean variable having a Value 1 or 0.A boolean variable js also called a control function. This statement indicates that the operation 1s performied only when C= 1, otherwise transfer operation is not performed. This is just an implementation of ifthen statement in the high-level langues thei R Ry + TABLE to Took is @ CRIMINAL act. Anyone found guilty, WARNING: Xerox/Photocopying of thisUNIT-1_ 5 Register Transfer Implementation ‘The figure below shows the bl seis tt : Jock i register trdnsfer from register Rl to register RO CLK (ek) Reger [| Te i eee Toad i= = input Control circuit = 7 Figure (i): Block Diagram of Register Transfer In the above figure, register R2 is connected to register RI ic, the outputs of R2 are given as inputs to- Ri. Let 7’ be the length of the register i, Ri ta that a rogiser olde. The control treat bas b control variable *C’ with which the load input associated with the register RI gets enabled. Further, the clock for the control variable must be synchronized with the same clock as applied to the register. ‘The timing diagram for the register transfer is shown in figure (ii. PL ax (eck) “Tanai ue ter Transfer Figure (ii: Timing Diagram of Res “As shown in the figure, both register (R1) and control variable (C) are synchronized with the same clock pulse ~ CLK. Hence, when the register transfer is implemented, at the same time, the control variable Cis also enabled. In the timing diagram itis shown thatattime *, Cis enabled which isrepresented by the rising edge of aclock pulse (i.e 1).And attime r+ 1, the load input is activated and the inputs of R} dre transferred into the register R2 simultancously. Now at timer the control variable C may go back to its origina! ata 0 Otherwive, if isactive then the register transfer will ‘occur with every clock pulse transition. Q12. Describe the ‘transfer of information u: common bus. ising OR Demonstrate constructio! bus system with multiplexers. i Macch-24(R18), 0116) the registers play @ tcontainadata in of acommon Answer : Ina digital computer system, critical roe iri data transfer. Every register m’™ 9 A common bus can be specified as a set of common lines, dedicating each line to each bit of a register. These are now responsible for sequential transfer ‘of binary information. Along the same lines, the identification of source register and destination register for a specific task is carried out by control signals. ‘The implementation of common bus is done in two ways, 1. Using Multiplexers Reger} per #f foo) (Elelels) Be, Figure (1): Common Bus System Using Multiploxors Figure (1) illustrates the implementation of common bus system. It comprises four registers, Register 0, Register 1, Register 2, Register 3, which are connected to multiplexers (mux 0, mux 1, mux 2, mux 3). Each and every register contains four bits from 0 to 3 and each of them is routed to common bus through multiplexers. ‘The implementation has four multiplexers that contains four input lines (A,B,C,Pp» A,B,C,» A,B,C,D,, 3210), two select lines (S,S,), and one output line."These four ‘multiplexers operate by selecting four bits of the source register such that four input lines belonging to mux 0 are connected to bit 0 outputs belonging to four source registers. This connection is performed in such a way that bit 0 of register 0 is given as input to bit 0 of mux 0, bit O of register 1 is given as input to bit 1 of mux 0, bit 0 of register? is given asinputto bit2 of mux 0, bit0 of register 3 is given as input to bit 3 of mux 0. In a way similar to this, the connections for mux’ can be connected to bit 1 outputs and inputs for mux 2 with bit 2, and the inputs belonging to mux 3 are linked to bit 3 outputs of register 0 through 3. However, only input connections for mux 3 are displays inorder to avoid the complexity. In addition to this, the multiplexer also has two more inputs i.e. two selection signals (S, and S,). The purpose of these lines is to select four bits of any one register and put them on the four-line common bus via i 4 ‘toanother. Cen fers information eer serge then, | outlines, When both the selec signals S, S,=00 then ; lent ines ae setup be 1 TErof wires, | input Oofall four multiplexers ‘get selected and enforced itcan result inthe requirement of eX PUTO cre | on the outputs 50 8 9 Wane them on common us. ons ey oe ae ems in com of muliple-reister | Now, Ne ommon bus receives the source register 0 Y leading to a complex cic ion between the | conten ‘When §, S,=01, the contents of register! gets aaa, fae tach eae transferred to the common bus. is carried out by a comm« IE JOURNAL FOR ENGINEERING ‘STUDENTS SPECTRUM ALL-IN-O!OMPUTER ORGANIZATION AND ARCHITECTURE [JNTU-HYDERABAD) buffer let ws assum ing tri c struct common bus SYStEM USING Li-stang Normally, the common bus system comprises 11 smultipliewer. and » - fre common bus and K number of agate to each maitiplexen. Where, m = Number of bits in each register. KC = Total number of registers. Aad cack multiplexer size becomes K «1. By connecting the inputs of all destination ‘Tegitery te bus ines an activating the load control input of spenitic destation register, the data transfer from a Sus to any destmnatice register ean be performed. The data wanster betucen register RI and R2 using a bus em be specifed as BUS « RILR2 — BUS. Kr signifies that the content of register RI is leaded er tus and the content of bus is loaded into the fepster R2 fs most of the data transfers, direct method of representing daa ransters herween register is adopted, Sm easy as Bas et within the gustem. Example: 22 2 Using Tristate Bas Baffers of common bus system can roc only by multiplevers but the three state serves as a best tool for this. Atri- Seite gate cans be specified as 2 distal circuit consisting Gree ontper gates HIGH. LOW. and high impedence. ong ect the onteus states HIGH. LOW corresponds so logic | and logic 0 respectively, where as output state Righ-impederce acts as omtput circuit representing that onipit is connected. As the burserves a common connection between multiple registers and other units, the data transfer through itrequires large sinking and large current source and he wistate that gives high sinking and sourcing ‘capacities is referred as tri-state buffer. Figure (2) shows the logic symbok fer tri-state buffer. Figure (Ze Logic Symbol for Tristate Butfer A teistate butfer has two inputs, a normal data pat seit 2 contsoh inget. The control input decides the Ste of the ontzas. Yihen the control input = 1 then the cota gets generated ix.,y™ A. Whereas, when control ign ~ G the output reaches high impedence state. f control signals fj 1 bus and four output control s . tote carter For such system, 2:4 decoder is required ion in figure (3). The decoder has 4 outputs whieh as show 5 behaves as 4 control signals. 2a Corea, ‘hain feeb —_—>———— Figure (3: Common Bus Line with Three-state Buffer When the enable input of the decoder indicates 1, then any one of the four tri-state buffer will be active, This activation of tri-state buffers depends on the binary. values of the decoder’s select input When the enable input of the decoder indicates 0, then all the four outputs of the decoder becomes 0°s. ‘This puts the bus into high-impedance state as all the tri-state buffers gets disabled. 1.2.3 Arithmetic Microopera Q13. Discuss in brief about Arithmetic Microoperations. Answer : Model Papert, 02(b) Arithmetic microperations are those that perform ‘arithmetic operations on the data contained in registers, The various arithmetic micro operations are as follows, Add: The micro-operation of the form R. < R, ~ 8 specifies an add micro-operation, this GPeration adds the contents of register Rio the somtents of register R.. Finally, it uansfone tt result obtained to register & . (ii) Subtract: The ‘micro- i R, from register RF obtained to register. ii) Increment: The micro operat t Peration of « _R,* Ispevifiesaninerementmicns any tion adds tothe contents oh fv) ‘The micro-operation of the ga", 1 Lepeiiesadccement microns "operation subtracts fom he conten ot (%) 1'sComplement: The: . 8, « Ry spevites an one's coma operation complement the conten SER 2's Complement: The micro-open se eER, form R, <= Ry + 1 specifies 26 OM OF the This operation complements the ¢"Plement, register R, and adds | to Ro Rents gUNIT-1 G14. With the help of block diagrams, about Half Adder, Full Adder and banal Adder. Answel 1. Half-Adder Consider the following operations, 0+0 =00 o+1=01 1+0=01 1+1=10 ‘These operations are executed using a logic circuit called half adder. The half adder takes two binary digits as inputs and generates two binary digits as outputs (ie comand carry). The following table shows the truth table for the half adder, From the operation of the half-adder as stated in the above table, expressions can be derived for the sum and the output carry as functions of the inputs. It can be observed that, the output carry (C,_) is 1 when both A and B are 1. Therefore, C,_ can be expressed as the AND of the input variables. C_.=AB Now, observe that the sum output is 1 ifthe input variables 4 and B are different. The sum can therefore be expressed as the exclusive-OR of the input variables, sum -A@B=AB + AB. yD —senaen oS Coq AB 3 Figure (1): Half-Adder 2 Full-Adder The full adder is the second ‘category of the Address. It operates by taking two inputs 4, B and input carry and produces an output of sum and output carry. A logic symbol for a full-adder is shown in the figure (2; L—sum, | ase cary je Symbol for Full-Adder Output 4 [slic] cw | Ss 0 fofof o jo o joJi}tio fa o frfo] oft o situ 1 jo 1 jofo]} o.f4 1 fof-t 1 ]o or fifo}or fo sfoor~fa Lt Asif Like a half-adder, the expressions for the sim and output carry of a full-adder are derived as follows, Sum =(4@B)@C,, AB +(A® BIC, C= ABHAGBIC, Figure (3k Full-Adder Parallel Adder A single full adder is an adder which is effective of adding two one-bit number and an input carry. The addition of binary number with multiple bits can only be performed with the use of full adders. This is called a parallel‘adder. When one binary number is added to. another, each column generates a sum bit and a carry bit (Gor 1) to the next column to the left, as illustrated here with 2-bit numbers. ear ttt i rektcokimn fun +01 100 Inths case, thecarry bit from secon cols becomes sum bi Inorder to add two binary numbers, a full- adder is required for each bit in the numbers. So for 4-bit numbers, four adders are used. The carrry output ‘generated from each adder is connected as input in the form of carry input to the next higher-order adder. SPECTRUM €ALL-I IN-ONE JOURNAL FOR ENGINEERING STUD!12 COMPUTER ORGANIZATION AND ARCHITECTURE LINTU-HYDERABAp, RC 3,¢, a 5 ih Awe, sey | ra §, 5, ‘bit Binary Addor Itean be observed that, there is no carry in the least significant bit position due to which the half adder jy employed as least significant position or carry input of full adder is made 0. Q15. With the help of block diagrams, explain the 4-bit binary subtractor. Answer : Subtraction is a special case of addition. To subtract two signed numbers, take the 2’s complement of the ‘subtrahend and add it with the minuend, Discard any final carry bit. To getthe 2's complement of a number, first find ou 1's complement and then add I to the Least Significary Bit (LSB). The following example illustrates the subtraction of two numbers, B-3=8+(-3)=5 00001000. Stinuad (+4) Decarg 2 EEVITOL Pecompmentofsuteaend (3) es Tooano tot Diereme (3) AMG ARG ABQ OAR fq [ew Addition/Subtraction of Logie Unit By using a combination of exclusive-OR ga ten eatatea | can be posmed 4s shown below. The circuit in figure (1) cénsists of to inputs A (ay. a, a, an cava ean 24, ,) a8 wells mode input M which is espns for sntling the operations. Ihe value of Mor ge ee circuit performs an add operation. And if itis equal to 1 then a subtract operation is performed. Every XOR gate i the circuit as an input of # and an input $f associated with 1 A1= 0 s applied to the NOR gate then ee obtained is B © 0 B and input carry C, is 0. The result is forwarded to al the full adders andthe gee Me SU addition of A and B. Altematively, if M™= 1 is applied, then the result obtained is 8 ® 1 = B with tne oe C, = 1. Hence, all the inputs of H are complemented and the input carry is add to it. The cieeniy sbtraction operation by adding 4 to the 2's complement of 8, The resll obtained is iterpreted ve te 6) Unsigned Numbers: When the condition A 2 B then the result obtained is (A ~B), When 4 = 2's complement of (B ~ A) is obtained. a Signed Numbers: If there is no overflow, then the result obiained is (4 ~ B), I~ lows, then the Gi) CK By. fr z | Cc (16. Give the Impl 13: tatlon of a 4-bit bh Answer: » ‘The purpose of the binary incrementer unit isto carryout incre byadding one othe number stored inthe regis a {sineremented by the clock pulse tra Incrementer. ‘ment microooperation. This operation is done hile the count enable signal is active, ; the content of the register : Misition, Icontinues, till the count enable signal is des tivated, Implementing the increment ner peberation using a binary counter is n egister-specific technique, This dependency can be eliminated ty using a combinational circuit consisting of casended halfeadders, A 4-bit binary increment cr implemented using a combinational e circuit adds a 4-bit binary number ora nibble By B, and B, indicate t ircuit of half-adders is shown below. The i hy he bits in the nibble from LSB (i.c., B,) to MSB (ie, J.) respectively. The first haliondder taker 122 nd logics! asiinputs, adds them, stores the sum in'S,and carry in ©. The next half-adder takes the curry fee the previous half-adder as one input and B, as another, Kalso, adds the tWo inputs, stores the Sum in S, and carry in C. The brocess continues tll all the 4-bits are processed. C, aives the camry and S, i the sum Which i Reviernted after incrementing the 4-bit numiber. » i 1 B, a v , a eae tae . fF £. s ‘| c nt Ss c Hh s & 8, 8, 8, ss * Fiaure: Abit Binary Ineromontar Using Four Half-Adders a Example ; : i Feder 4-bit register which has a bitary value (1001),, The complete process of incrementing by using the 4-bit binary icrementer is as. follows, . L By= and logie = 1 is another input + G1, =0 : y 2 =O and C= 1 (carry generated in previous adder) i + C=0,5,=0 3 B,=Oand 4, Therefore, after incrementing the binat C,will be 1 only when the binary number 1111 is j Foran -bit binary incrementer, n half-adders Sameas that ofa 4-bit binary incrementer. Thus, G17. Design a 4-bit combinational.circuit decrementer u Answer ‘it Binary Decrementer Decrement microoperation is used to decrement 1 from a number ng 1111 to the number as shown below. Let A be the number stored i 4~1 Decrement = atin The diagrammatic representation of 4-bit bin (enum a) Mae 20 ca) oe. ay stored in a re in the register, sister, This can be done by A +2’s complement of 1 t ary decrement is shown below, B, 1 Boa | y | FA, Hf t reNA ANIZATIO! ZI, B,=0.B,~ 1 and B= gy - fies By : ‘Suppose A = 5. Its binary equivalent Da gum in S, and the earry in C,. Here, y," takes B, and logic-1 as input, adds them and fall adder. The other input is By. Here, p sy carry is 1s cary forwarded as input 1 HE C. Here, §, is 0and C8 1. Gis now yey) are added. Their sum is now saved in S, and cay” "2-4 guit-adder are added: The De full-adder in addition-to B,. The two inputs ys oe adder, 5, and C,areo ‘at srl and carry in C,, Here, S, is 1 and C, is 1. Similarly, final bodtivalric rooming all the four th the final value obtained is 0100, whose decimal equivalent is 4, Hetcg that the value $ is decremented to 4. Q18, Draw and explain 4-bit arithmetic circu | Answer: ' - An arithmetic circuit can implement distinct arithmetic, operations. It uses the paralle! a component, By controlling the data inputs of the adder, the arithmetic operations such as adgiyg, °S register transfer, iicrement and decrement can be generated using a single arithmetic circuit, Be The below figure shows a 4-bit arithmetic circuit. Input Cary : SC 14 vi it with the help of a function table, Logics15 ‘The arithmetic circuit consists of, 4 full adders" 4 multiplexers ‘Two 4-bit inputs Mand N ‘Two selection inputs S, and, 4-bit output 0 iq input carry) [C,, can be either 0 oF 1} Cong (OUtPUt carry) Tand Jare the inputs of the full adder. ‘The four input lines from Mare connected to the inputs of the full adder. From 4-bit input N, each of the 4 inputs go directly to the multiplexer’s data inputs, The complements of inpuls from N are also connected to the data input of the multiplexer. The remaining two data inputs of multiplexer are connected to logic-0 and logic-1. Logic) is a fixed voltage value. An inverter is used to generate the logic-I signal. The two selection inputs §, and S, control the four multiplexers, To the least significant position ( stages of a full adder are connecte: Pee ee sae (C,) of a full adder the input éarry C,, is connected. First and succeeding ‘d through other carries ie, C,, C,, Cy and Cy. ‘The output of the binary adder is computed. using the following arithmetic expression: L=M+J*C, Where, M - 4-bit binary number at the J inputs J -4bit binary number at the J inputs C,,~ The input carry having a value 0 of 1. By controlling the values of C,, and the J in eight arithmetic microoperations. They are additio increment, decrement and transfer. The transfer microoperations. a . Addition % — WhenS,S,=00and C,,=0, value of Nis appl is carried out. Output, L = M+N. % When S,S, = 00 and C,, = 1, a value of N is applied to J in __ microoperation is carried out. Output, L= M+ N+ 1 iputs of the binary adder, the 4-bit arithmetic circuit can generate mn (with and without carry), subtraction (with and without borrow), operation is generated twice: So, there are only seven distinct lied to the J inputs ofa full adder and an addition microoperation puts of a full adder and an addition with carry Selection Input Carry input | Input of full Output S, Sy C, addeS |LeM+s+c, 0 0 oO N_ L z pf te [u=M+ne1 (li) Subtraction 1oiWhen S; $,=01 and C,,=0, acomplement of Wis applied to the J inputs ofa full adder and a subtract with borrow microoperation is carried out. 9 Output, L= M+ N= M+ 1’s complement of N =M-N-1 When 5, 5, = 01 and C,,= 1, 2’s complement of W is applied to the J inputs of a full adder, and a subtract microoperation is carried out. Output, L = M+ N = | = M+ 2's complement of N. Selection Input Carryinput | Input of ‘Output G, adder, J | L=M+J+C,, L=M+WN L=M+N41Fe ON | ND ARCHITECTURE [JNTU-Hyp, 16 COMPUTER ORGANIZATION Al ay cm) paste 10 and C,,= 0, a zero is inserted into J inputs of a full adder by ignoring the input Vale ofy er! in O% Output, L= M+ J+ C= M040 L=M When SS) 11 and C= 1, insert all 1's into J inputs of a full adder by Ignoring the input Values op y So anh Output, L = ME I+, g = M+2’s complement of J+ C,, =M+JS +140, =M-J4C, . M146, J=tj “ =M-1+1 => Lem. Selection Input Carry input Input of Output S, S, c adder, J L=M+J+C, 1 0 0 0 L=M 1 1 1 1 _L=M (iv) Decrement and Increment When, $,5, = 10 and if, = 1, ignore the values LeM+I+C,= M4046, =M+0+1 = M+ 1 (increment) When, 5,5, = 1 andifc, L=M+J+C, = M+ 2's complement’of J+ C,, oM+ JT +146, = IEC, M-14+6,(" J=1) M-1+0 =M-r L=M-1 decrement) Of and replace al the J inputs ofa full adder with 0s 0+ Fenore the values of and replace ail the J inputs of a full adder with 1's ‘Selection Input] Carry input | TnpatoF s, 5, Cy [> adder, 3 1 0 1 0 a 1 © 1 Logic Microoperations: ate. whit is‘@'logic microoperation? Discuss in detall various. Laas O1P28 of logic microo Also give the hardware implementation of logle mlcrooperatione erations. a Model Paperan,a2te) Logie Microoperations ir ions for bit strings present in a register are specified by the log The binary operations es ee st ings Press a ares Pe Y the logic indy contents of a register are considered as dis Binary Comidera sateen, 3 x:de AOB SEG cto rages CET e" @® -Exclusive-OR (XOR) operatorConsider © numeric example, 40101 and B= 0011 fenume that Contents of register B Contents Contents of reg eT '¥ of register Ib after XOR operation When x= 1 Special Symbols Inorder to differentiate’boolean functions from Jogic microoperations having similar functionalities, the logic microoperations use special symbols wn fs 8 Is as she the following table, own in Boolean Function Logic Microoperation | OR @ Vv E,=(a+b) BE, (avby Gi) AND dj) A E,= (ab) E, (arb) Complement Complement E = Rea Example X+Y: RIC R3 + RA, R2<— RS v RO Inthe above example, ‘+’ symbol between R3 and R4 denotes an ‘arithmetic addition’ operation. Whereas in boolean function X + ¥, it denotes an ‘OR’ operation. Here, ‘v’ symbol between RS and R6 denotes an ‘OR’ operation. R3 + R4 denotes an ADD operation between binary contents of two registers R3 and R4. RSV RG denotes an OR operation between binary contents of two registers RS and R6. ‘Types of Logic Microoperations There are 16 logic microoperations. They are as follows, 1, Clear Microoperation Boolean function : F = 0. ‘Truth Table Set to all 1 PF e allt Boolean function : F= 1 ‘Truth Table qransfer x : Fx Boolean function : F ‘Transfer y : Boolean funct Complemen Boolean function : F = x! 17 Complement Boolean function : F = y" ‘Truth Table y fy] ofa 1}o of1 rio18 FOR Microoperation Roolean function :F ‘Truth Table AND Microoperation :F Boolean function FX Y ‘Truth Table ©, Exclusive-OR Microoperation (XOR) : F— x ey Boolean function : F = x ® y Truth Table 40. NOR Microoperation : Fe xvy Boolean function : F = (x+y) ae T OR AA cluslve-NOR Mlcrooperation (x 10N AND ARC Oe enna PAR 10 FO xBY hy Hoolean function + F = (x @ yy ‘Truth Table 13: Logic Microoperation : F —xv¥ (ty) ‘Truth Table Boolean functio 14, Logic Microoperation : F— ¥vy Boolean function : F = (x' + y) ‘Truth Table y 0 1 0 L oon al 1 0 1 15. Logic Microoperation : Fx Ay Boolean function : F = xy’ ‘Truth Table ‘Truth Table x y [a+y [Featy'] [x F=xy' po fof o 1 0 0 ; 0 1 1 0 0 0 pi jo 1 0 1 1 oj 1 0 1 ° Jj 16, Logic Microoperation : F XA y Boolean function : F = x' y ‘Truth Tab wa” aeUNIT-1_* Hardware Implementation of Logle Microoperations This circuit consists of 16 gates and 16 * 1 multiplexer which generates all the 16 basic logic mmicrooperations by performing logic at a respective gate as shown in figure, AL cach gate corresponding microoperation is performetl and its result is generated E,, The circuit consists of 4 selection vatiables namely'S., $., 5. §., These selection inpuis, select data inpyts and passes ite value to the output, 19 1} o};1yo TPoprys Ty} rjoto 1 tj}ott Transfer Y_ tyro Transfer X rfijfifi | _Set all to 1’s ft Fanetion Sette 5 Q20. What are the applications of logic microoperations? Answer : Applications of logic microoperations are, + Inaregister, individual bits or a portion of a word can be manipulated. Bit values can be changed in a register. Group of bits can be deleted from register. New bit values can be.inserted in a register. Manipulation of bits present in register RX and RY can be carried out using the following operations, @ Sete It considers only 1’s in register ¥ and’ sets the corresponding bits in the register X to 1 wherever I’s are encountered in register Y. e-set Operation Ignore performing operations on bits of register X whose corresponding bits in register ¥ are 0°s. Example Register Register ¥ i bY (Geter) Geto) wana « Conesponing sister 1s HS Hy {oo ° 1 1 ietangesy Figure: Logic Diagram of Hardware Associated with i ®. . distorts i 1 1 Wockange since < isvahe wi) - responding bt 5.15, 15,]5, ‘Operation oloboto Clear Gi) Selective-complement Operation olo ‘s elt OR Itconsiders only 1's in register ¥ and complements olotite nore the corresponding bits in the register 1" wherever I’s are encountered i Y. - atte ND ed in register Y, i Example of 1folo NAND = > 5 Regitr X 1fofa X-OR tate olitilo X-NOR Ae oft 1 pew | Complementy : Bey plement 4 (Complement operation) 1fololo E= 3x | Complement X : : . 9 (Complemeet operation)cl (i) Clear Operation Oe ap 20 Topers eee Yand clears the Anexchisive-OR (KOR) oe es ool : 0 bits in Mask Operation ; v It considers only 0°s in,register Y and clears the corresponding bits in register X to 0. . Mictooner s in rey asa clear operation. Whenever two. one aton vy ster Xt0 of registers X and Y are similay 4 wesP onda -] either Os or 1s then its value win fe assigtt® bits a Tex > | register X. ined aah (After) [is tae | ° 9 (Cleared to 0) 1 0 Example ; Register Y Register X en (rask) (After) 9 Mask Operation) ° 0 (Mask Operation) 1 The selective-clear and mask operations are similar only the difference is that, here it considers 0°s inregister y. () Insert Operation In a group of bits, a new value can be inserted by performing mask operation and then OR operation is performed on the result with the required value. Register x’ Before) Register ¥ Register X (leary (Aner) Letthe bit via a tb Hobe With the 2 (Mask Operation) ° © (Mask Operation) 1 inserted in register Ythen thése resulting masked register X. Registerx (After OR) Q21. Discuss about shift mi detail. Answer : (Model Paper icrooperations in | Q3(a) | AprivMay-23(R19), The shift micro-operations are specifi employed for shifting the contents of a register t OF Fight position. They are used for performing serial ansfer of data. During the shifting operation of bis, the binary information from serial input is given tothe first flip-flop in the register and the last ip-flop in the Fegister produces the information to the serial output, aya) cally 0 leh ‘The operations that are performed here is shift left operation and shift right operation. In former one, the Operation of serial input transfers bit to the right most Position where as in latter one, the operation of serial input transfers bit to the left most position, ‘The shift operations are categorized into three types, 1. Logical Shift ‘The serial input in logical shift operation is taken as zero. Due to the shift operation, an empty pestion is created in the register which is filled with zero ba is transferred through serial input. This is Harm E in the following figures. There are two logical 7 microoperations i.e., Logical Shift Left (LshL) an Logical Shift Right (LshR). aia, The following operations illustrates logical shi Ry —Lshh R, R,—LshR R, 3 icrooperations e tions are two microoperation Tie above operstiong ate tilace and Ry21 Cee as ; art Ny aoe . Figure (1: Logical Shit Right —p.pa] . Bal B, | B, Je Sera wT ; Figure (2k: Logical shift aft Example of Logical Shit “The above figure shows a register that holds ‘n’ bits. The left most bit in the register stores B,_ which is the sign bit. The bits B,_,and B, specify the most significant and least significant bits of the number respectively. In the arithmetic shift-right operation, the sign bit must remain the same and the bits along with the sign bit must be shifted from left to right. Hence, the bit B,_, does not change and is passed to B,_,- The received bit in B,_ is again passed to B,_, and so on till B, receives a bit from B,. As a result, the bit in B, is removed. Example Sieabit Figure (4): After Logical Shift-Right Example of Logical Shift-Left i fo fofrfafa 7 PS * pat This bit removed 0% Figure (5): Before Logical Shift-Left of of rf] rf of 1] 0 . Figure (6): After Logical Shift-Left 2. Arithmetic Shift ‘Anarithmetic shift is defined as a microoperation “which isresponsible for shifting a signed binary number towards-a right or left position. Hence, the arithmetic ‘shift can either be (i) An arithmetic shift-right (07) (i) ‘An arithmetic shift-left. ‘An atithmetic shift-right is equivalent to the jon of the binary number by 2 whereas the arithmetic the multiplication of the binary per is divided or multiplied di shift-left is equivalent to number by 2. When the numa by 2, there'should be no change in the sign of that umber. Thus, in case of arithmetic shift operations, the sign bit of the number remains the same. A register ‘with thé left most bit contains the sign bit and the other bits contain the number. Ifa zero appears inthe sign bit hen the number is positive, else it is negative. The negative numbers are represented in a 2's ‘complement format. @ Arithmetic Shift-Right Sign bit Most significant & 1 CELE! t Least sinicant (Decimal 28) epee ty “This bi removed Figure (8): Before Arithmetic Shift Right 1] 0 @oimiig fof of.o fo] 1} t + Sabi remains same : Figure (9): After Arithmetic Shift Right Gi) Arithmetic Shift-Left ‘The sion bit changes 25 per the received bit [Pe |. S This bit is removed Figure (10}: Arithmetic ShiftLeft During the arithmetic shift-left operation, a zero is placed in the B, position and the remaining bits in the register are shifted towards the left. Hence, the value at B,_, bit gets lost and a new value which is received fromB,_, bit is stored in B,__,. Depending upon the new value, the sign bit changes after the left shift operation. ‘The sign reversal is performed when an overflow occurs after the multiplication of number by 2. Afier an arithmetic shift left operation, an overflow occurs if the value of B,_, # B,_., before the shift operation. In order to identify an arithmetic shift-left overflow, a flip-flop V, is required such that, SV Bt Bae When V, holds a zero value, no overflow occurs and when V, holds 1, an overflow occurs and the sign bit is changed. Both the shifting operation and the V, transfer in the overflow flip-flop must be synchronized with the same clock pulse i., they must be performed atthe same time. NE JOURNAL FOR ENGINEERING ‘STUDENTS =SspecrRan auLin-o22 se rf t : a RACE abhi Ot eed Figure (11): Before an Arithmetic Shift-Left Sign bit otc f omit [To] oo. fe] ]e “Figure (12) After an Arithmetic Shift-Left ‘Symbolic Representation Re—AshLR ReAshRR 3. Circular Shift or Rotate ‘The circular shift or rotate is also called as rotate microoperation. During the shifting of bits in shift microooperation, the bits which are shifted out of register 80 off track (lost). However, this bit is maintained by circular shift. It operates by shifting each bit out of one end of register and giving back into the other end of the register. The two types of rotate microoperations are Rotate Left (RL or CshL) and Rotate Right (RR or CshR). B.-|B, <— [5/5 Figure (13): Rotate Left a Na Figure (14%: Rotate Right Symbolic Representation Re CshLR RE CARR ireular Shift-Left Example of 7 1 eee Figure (15): Before Circular Shift-Left cy Figure (16): After Circular Shift-Left “Example of Cireular Shift-Right para . Figure (171: Before Circular Shift-Right WARNING: Kerox|Photocopying of ths COMPUTER ORGANIZATION AND ARCHITECTURE [JNTU-HY! DERABAD, Example ‘22. Write about th plenenas Answer A bidirectional shift register along with a Parl load is used for shifting the information, The informatie, canbe parallely sent into the register and then a shift shift-left operation can be performed. This system two clock pulses, one for storing the informatio Feuires the isterand the other for initiating the shift microoperations case of a processor unit containing several registers, shia operation must be performed using a combinational cre, Here, the information ofa register is applied onto a commen, bus and the result generated is given to the combinations, ifted value. This value is again stored shifterto produce a in the register. Hence, for shifting and ste the register, only a single clock pulse transi “a AAA ing the value in % a 1 8, Figure: Representation of a 4-bit Combinational Circuit Sitter ‘The above figure represents, a 4-bit combinational circuit shifter along with the multiplexers. This circuit consists of four data inputs (4,—A,) and four data outputs (Hy ~ H,). It also contains 4 selection input(s) and two serial inputs for performing a shift-right (J,) and shift-left operation (J,). If = 0 then input data is shifted towards right and if S= 1, then it is shifted towards left. Selection Input Output s nH, | H, | 4, | 1, 0 A | Ag sf Aprfeay 1 A | a | aA | Table: Function Table The above function table defines which input is connected to which output after the shift microoperation has been performed. Suppose, ifa combinational shifter contains m data inputs and m data outputs then for shifting the data ‘m’ multiplexers are required. Inorder to handle the two serial inputs another multiplexer is used to provide three possible kinds of shift microoperations. agian cemrnnseerr 1.2.6 “Arithe ic Logic 23. With the help of a diagram explain one stage of arithmetic logic shift unit. Answer : , ‘The arithmetic, logic and shift circuits can be ‘combined into one composite circuit with the help of a multiplexer to get the arithmetic logic shift unit. The following figure shows one stage of an arithmetic logi¢ shift unit. te LEGAL proceedings.