DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs

October 1988
Revised March 2000

DM74LS47
BCD to 7-Segment Decoder/Driver with
Open-Collector Outputs
General Description Features
The DM74LS47 accepts four lines of BCD (8421) input ■ Open-collector outputs
data, generates their complements internally and decodes ■ Drive indicator segments directly
the data with seven AND/OR gates having open-collector
■ Cascadable zero-suppression capability
outputs to drive indicator segments directly. Each segment
output is guaranteed to sink 24 mA in the ON (LOW) state ■ Lamp test input
and withstand 15V in the OFF (HIGH) state with a maxi-
mum leakage current of 250 µA. Auxiliary inputs provided
blanking, lamp test and cascadable zero-suppression func-
tions.

Ordering Code:
Order Number Package Number Package Description
DM74LS47M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS47N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol Connection Diagram

VCC = Pin 16
GND = Pin 8

Pin Descriptions
Pin Names Description
A0–A3 BCD Inputs
RBI Ripple Blanking Input (Active LOW)
LT Lamp Test Input (Active LOW)
BI/RBO Blanking Input (Active LOW) or
Ripple Blanking Output (Active LOW)
a –g Segment Outputs (Active LOW) (Note 1)
Note 1: OC—Open Collector

© 2000 Fairchild Semiconductor Corporation DS009817 www.fairchildsemi.com

DM74LS47
Truth Table
Decimal
Inputs Outputs
or Note
Function LT RBI A3 A2 A1 A0 BI/RBO a b c d e f g
0 H H L L L L H L L L L L L H (Note 2)
1 H X L L L H H H L L H H H H (Note 2)
2 H X L L H L H L L H L L H L
3 H X L L H H H L L L L H H L

4 H X L H L L H H L L H H L L
5 H X L H L H H L H L L H L L
6 H X L H H L H H H L L L L L
7 H X L H H H H L L L H H H H
8 H X H L L L H L L L L L L L

9 H X H L L H H L L L H H L L
10 H X H L H L H H H H L L H L
11 H X H L H H H H H L L H H L
12 H X H H L L H H L H H H L L
13 H X H H L H H L H H L H L L

14 H X H H H L H H H H L L L L
15 H X H H H H H H H H H H H H
BI X X X X X X L H H H H H H H (Note 3)
RBI H L L L L L L H H H H H H H (Note 4)
LT L X X X X X H L L L L L L L (Note 5)
Note 2: BI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held at a HIGH
level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking or a decimal 0 is not
desired. X = input may be HIGH or LOW.
Note 3: When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a HIGH level regardless of the state of any other input
condition.
Note 4: When ripple-blanking input (RBI) and inputs A0, A1, A2 and A3 are LOW level, with the lamp test input at HIGH level, all segment outputs go to a
HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition).
Note 5: When the blanking input/ripple-blanking output (BI/RBO) is OPEN or held at a HIGH level, and a LOW level is applied to lamp test input, all segment
outputs go to a LOW level.

Functional Description
The DM74LS47 decodes the input data in the pattern indi- intermediate decoder from an OR gate whose inputs are
cated in the Truth Table and the segment identification BI/RBO of the next highest and lowest order decoders. BI/
illustration. If the input data is decimal zero, a LOW signal RBO also serves as an unconditional blanking input. The
applied to the RBI blanks the display and causes a multi- internal NAND gate that generates the RBO signal has a
digit display. For example, by grounding the RBI of the resistive pull-up, as opposed to a totem pole, and thus BI/
highest order decoder and connecting its BI/RBO to RBI of RBO can be forced LOW by external means, using wired-
the next lowest order decoder, etc., leading zeros will be collector logic. A LOW signal thus applied to BI/RBO turns
suppressed. Similarly, by grounding RBI of the lowest order off all segment outputs. This blanking feature can be used
decoder and connecting its BI/RBO to RBI of the next high- to control display intensity by varying the duty cycle of the
est order decoder, etc., trailing zeros will be suppressed. blanking signal. A LOW signal applied to LT turns on all
Leading and trailing zeros can be suppressed simulta- segment outputs, provided that BI/RBO is not forced LOW.
neously by using external gates, i.e.: by driving RBI of a

www.fairchildsemi.com 2
 SN54/74LS74A
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir-
cuitry to produce high speed D-type flip-flops. Each flip-flop has individual
clear and set inputs, and also complementary Q and Q outputs. DUAL D-TYPE POSITIVE
Information at input D is transferred to the Q output on the positive-going EDGE-TRIGGERED FLIP-FLOP
edge of the clock pulse. Clock triggering occurs at a voltage level of the clock
pulse and is not directly related to the transition time of the positive-going LOW POWER SCHOTTKY
pulse. When the clock input is at either the HIGH or the LOW level, the D input
signal has no effect.

J SUFFIX
LOGIC DIAGRAM (Each Flip-Flop) CERAMIC
CASE 632-08
14
1
SET (SD)
4 (10)
Q
5 (9)
CLEAR (CD)
1 (13) N SUFFIX
PLASTIC
CLOCK 14 CASE 646-06
3 (11)
Q 1
6 (8)
D
2 (12)
D SUFFIX
SOIC
14
1 CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ Ceramic
MODE SELECT — TRUTH TABLE SN74LSXXN Plastic
SN74LSXXD SOIC
INPUTS OUTPUTS
OPERATING MODE
SD SD D Q Q
Set L H X H L
LOGIC SYMBOL
Reset (Clear) H L X L H
*Undetermined L L X H H 4 10
Load “1” (Set) H H h H L
Load “0” (Reset) H H l L H
2 D SD Q 5 12 D SD Q 9
* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then 3 11
CP CP
we cannot guarantee to meet the minimum level for VOH.
H, h = HIGH Voltage Level 6 8
L, I = LOW Voltage Level
CD Q CD Q
X = Don’t Care
i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time 1 13
i, h (q) = prior to the HIGH to LOW clock transition.
VCC = PIN 14
GND = PIN 7

FAST AND LS TTL DATA

5-72
 SN54/74LS75
4-BIT D LATCH SN54/74LS77
The TTL/MSI SN54/ 74LS75 and SN54/ 74LS77 are latches used as tem-
porary storage for binary information between processing units and input /out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH. 4-BIT D LATCH
The SN54 / 74LS75 features complementary Q and Q output from a 4-bit
LOW POWER SCHOTTKY
latch and is available in the 16-pin packages. For higher component density
applications the SN54/ 74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.

CONNECTION DIAGRAMS DIP (TOP VIEW)

Q0 Q1 Q1 E0–1 GND Q2 Q2 Q3 J SUFFIX

CERAMIC
16 15 14 13 12 11 10 9
CASE 620-09
16
1

SN54 / 74LS75
N SUFFIX
PLASTIC
16 CASE 648-08
1 2 3 4 5 6 7 8
Q0 D0 D1 E2–3 VCC D2 D3 Q3 1

Q0 Q1 E0–1 GND NC Q2 Q3
D SUFFIX
14 13 12 11 10 9 8
SOIC
16
1 CASE 751B-03

SN54 / 74LS77

J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
D0 D1 E2–3 VCC D2 D3 NC 1

PIN NAMES LOADING (Note a)

HIGH LOW
N SUFFIX
D1–D4 Data Inputs 0.5 U.L. 0.25 U.L.
PLASTIC
E0–1 Enable Input Latches 0, 1 2.0 U.L. 1.0 U.L.
14 CASE 646-06
E2–3 Enable Input Latches 2, 3 2.0 U.L. 1.0 U.L.
Q1–Q4 Latch Outputs (Note b) 10 U.L. 5 (2.5) U.L. 1
Q1–Q4 Complimentary Latch Outputs (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 Unit Load (U.L.) = 40 µA HIGH. D SUFFIX
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) SOIC
Temperature Ranges. 14
1 CASE 751A-02

TRUTH TABLE
(Each latch)
ORDERING INFORMATION
tn tn + 1 NOTES:
tn = bit time before enable SN54LSXXJ Ceramic
D Q negative-going transition SN74LSXXN Plastic
H H tn+1 = bit time after enable SN74LSXXD SOIC
negative-going transition
L L

FAST AND LS TTL DATA

5-75
 SN54/74LS75

LOGIC SYMBOLS

SN54/74LS75 SN54/74LS77
2 3 6 7 1 2 5 6

D0 D1 D2 D3 D0 D1 D2 D3
13 E0–1 12 E0–1 VCC = PIN 4
VCC = PIN 5
E2–3 E2–3 GND = PIN 11
4 GND = PIN 12 3
NC = PIN 7, 10
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q0 Q1 Q2 Q3

16 1 15 14 10 11 9 8 14 13 9 8

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input LOW Voltage for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

D Input 20 µA VCC = MAX, VIN = 2.7 V

E Input 80
IIH Input HIGH Current
D Input 0.1 mA VCC = MAX, VIN = 7.0 V
E Input 0.4

D Input – 0.4
IIL Input LOW Current mA VCC = MAX, VIN = 0.4 V
E Input –1.6
IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX
ICC Power Supply Current 12 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tPLH 15 27
Propagation Delay, Data to Q ns
tPHL 9.0 17

tPLH 12 20
Propagation Delay, Data to Q ns
tPHL 7.0 15 VCC = 5.0 V
tPLH 15 27 CL = 15 pF
Propagation Delay, Enable to Q ns
tPHL 14 25

tPLH 16 30
Propagation Delay, Enable to Q ns
tPHL 7.0 15

FAST AND LS TTL DATA

5-76
 DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
September 1986
Revised July 2001

DM7476
Dual Master-Slave J-K Flip-Flops with
Clear, Preset, and Complementary Outputs
General Description negative transition of the clock, the data from the master is
transferred to the slave. The logic state of J and K inputs
This device contains two independent positive pulse trig- must not be allowed to change while the clock is HIGH.
gered J-K flip-flops with complementary outputs. The J and The data is transferred to the outputs on the falling edge of
K data is processed by the flip-flop after a complete clock the clock pulse. A LOW logic level on the preset or clear
pulse. While the clock is LOW the slave is isolated from the inputs will set or reset the outputs regardless of the logic
master. On the positive transition of the clock, the data levels of the other inputs.
from the J and K inputs is transferred to the master. While
the clock is HIGH the J and K inputs are disabled. On the

Ordering Code:
Order Number Package Number Package Description
DM7476N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Connection Diagram Function Table

Inputs Outputs
PR CLR CLK J K Q Q
L H X X X H L
H L X X X L H
L L X X X H H
(Note 1) (Note 1)
H H L L Q0 Q0
H H H L H L
H H L H L H
H H H H Toggle
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
= Positive pulse data. The J and K inputs must be held constant while
the clock is HIGH. Data is transferred to the outputs on the falling
edge of the clock pulse.
Q0 = The output logic level before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each complete active HIGH level clock pulse.
Note 1: This configuration is nonstable; that is, it will not persist when the
preset and/or clear inputs return to their inactive (HIGH) level.

© 2001 Fairchild Semiconductor Corporation DS006528 www.fairchildsemi.com

 SN54/74LS138
1-OF-8 DECODER/
DEMULTIPLEXER
The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder /
Demultiplexer. This device is ideally suited for high speed bipolar memory
chip select address decoding. The multiple input enables allow parallel ex-
pansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 1-OF-8 DECODER /
decoder using four LS138s and one inverter. The LS138 is fabricated with the DEMULTIPLEXER
Schottky barrier diode process for high speed and is completely compatible
with all Motorola TTL families. LOW POWER SCHOTTKY
• Demultiplexing Capability
• Multiple Input Enable for Easy Expansion
• Typical Power Dissipation of 32 mW
• Active Low Mutually Exclusive Outputs
• Input Clamp Diodes Limit High Speed Termination Effects J SUFFIX
CERAMIC
CONNECTION DIAGRAM DIP (TOP VIEW) CASE 620-09
16
VCC O0 O1 O2 O3 O4 O5 O6 1
16 15 14 13 12 11 10 9

NOTE:
The Flatpak version N SUFFIX
has the same pinouts PLASTIC
(Connection Diagram) as CASE 648-08
the Dual In-Line Package. 16
1
1 2 3 4 5 6 7 8
A0 A1 A2 E1 E2 E3 O7 GND
D SUFFIX
PIN NAMES LOADING (Note a)
SOIC
HIGH LOW 16
1 CASE 751B-03
A0 – A2 Address Inputs 0.5 U.L. 0.25 U.L.
E1, E2 Enable (Active LOW) Inputs 0.5 U.L. 0.25 U.L.
E3 Enable (Active HIGH) Input 0.5 U.L. 0.25 U.L. ORDERING INFORMATION
O0 – O7 Active LOW Outputs (Note b) 10 U.L. 5 (2.5) U.L.
SN54LSXXXJ Ceramic
NOTES:
SN74LSXXXN Plastic
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
SN74LSXXXD SOIC
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.

LOGIC DIAGRAM
LOGIC SYMBOL
A2 A1 A0 E1 E2 E3
3 2 1 4 5 6 VCC = PIN 16 1 2 3 456
GND = PIN 8
12 3
= PIN NUMBERS

A0 A1 A2 E

O0 O1 O2 O3 O4 O5 O6 O7

15 14 13 12 11 10 9 7

VCC = PIN 16
GND = PIN 8
7 9 10 11 12 13 14 15
O7 O6 O5 O4 O3 O2 O1 O0

FAST AND LS TTL DATA

5-1
 SN54/74LS138

FUNCTIONAL DESCRIPTION
The LS138 is a high speed 1-of-8 Decoder/Demultiplexer pansion of the device to a 1-of-32 (5 lines to 32 lines) decoder
fabricated with the low power Schottky barrier diode process. with just four LS138s and one inverter. (See Figure a.)
The decoder accepts three binary weighted inputs (A0, A1, A2) The LS138 can be used as an 8-output demultiplexer by
and when enabled provides eight mutually exclusive active using one of the active LOW Enable inputs as the data input
LOW Outputs (O0 – O7). The LS138 features three Enable in- and the other Enable inputs as strobes. The Enable inputs
puts, two active LOW (E1, E2) and one active HIGH (E3). All which are not used must be permanently tied to their appropri-
outputs will be HIGH unless E1 and E2 are LOW and E3 is ate active HIGH or active LOW state.
HIGH. This multiple enable function allows easy parallel ex-

TRUTH TABLE
INPUTS OUTPUTS
E1 E2 E3 A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7
H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H H L L H L H H H H H H
L L H L H L H H L H H H H H
L L H H H L H H H L H H H H
L L H L L H H H H H L H H H
L L H H L H H H H H H L H H
L L H L H H H H H H H H L H
L L H H H H H H H H H H H L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care

A0
A1
A2
LS04
A3

A4
H

123 123 123 123

A0 A1 A2 E A0 A1 A2 E A0 A1 A2 E A0 A1 A2 E

LS138 LS138 LS138 LS138

O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7

O0 O31

Figure a

FAST AND LS TTL DATA

5-2
 SN54/74LS151
8-INPUT MULTIPLEXER
The TTL / MSI SN54 / 74LS151 is a high speed 8-input Digital Multiplexer.
It provides, in one package, the ability to select one bit of data from up to eight
sources. The LS151 can be used as a universal function generator to
generate any logic function of four variables. Both assertion and negation
outputs are provided. 8-INPUT MULTIPLEXER
• Schottky Process for High Speed
LOW POWER SCHOTTKY
• Multifunction Capability
• On-Chip Select Logic Decoding
• Fully Buffered Complementary Outputs
• Input Clamp Diodes Limit High Speed Termination Effects

J SUFFIX
CERAMIC
CASE 620-09
CONNECTION DIAGRAM DIP (TOP VIEW) 16
1
VCC I4 I5 I6 I7 S0 S1 S2
16 15 14 13 12 11 10 9

N SUFFIX
PLASTIC
16 CASE 648-08
1

1 2 3 4 5 6 7 8
I3 I2 I1 I0 Z Z E GND
D SUFFIX
SOIC
16
1 CASE 751B-03

ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
PIN NAMES LOADING (Note a) SN74LSXXXD SOIC
HIGH LOW
S0 – S2 Select Inputs 0.5 U.L. 0.25 U.L.
E Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. LOGIC SYMBOL
I0 – I7 Multiplexer Inputs 0.5 U.L. 0.25 U.L.
Z Multiplexer Output (Note b) 10 U.L. 5 (2.5) U.L.
Z Complementary Multiplexer Output 10 U.L. 5 (2.5) U.L. 7 4 3 2 1 15 14 13 12
(Note b)
NOTES: E I0 I1 I2 I3 I4 I5 I6 I7
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. 11 S0
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) 10 S1
Temperature Ranges. 9 S2
Z Z

6 5

VCC = PIN 16
GND = PIN 8

FAST AND LS TTL DATA

5-1
 SN54/74LS151

LOGIC DIAGRAM
I0 I1 I2 I3 I4 I5 I6 I7
9 4 3 2 1 15 14 13 12
S2
10
S1
11
S0
7
E

VCC = PIN 16
GND = PIN 8 6 5
= PIN NUMBERS
Z Z

FUNCTIONAL DESCRIPTION
The LS151 is a logical implementation of a single pole, Z = E ⋅ (I0 ⋅ S0 ⋅ S1 ⋅ S2 + ⋅ I1 ⋅ S0 ⋅ S1 ⋅ S2 + I2 ⋅ S0 ⋅ S1 ⋅ S2
8-position switch with the switch position controlled by the + I3 ⋅ S0 ⋅ S1 ⋅ S2 + I4 ⋅ S0 ⋅ S1 ⋅ S2 + I5 ⋅ S0 ⋅ S1 ⋅ S2 + I6 ⋅ S0
state of three Select inputs, S0, S1, S2. Both assertion and ⋅ S1 ⋅ S2 + I7 ⋅ S0 ⋅ S1 ⋅ S2).
negation outputs are provided. The Enable input (E) is active The LS151 provides the ability, in one package, to select
LOW. When it is not activated, the negation output is HIGH from eight sources of data or control information. By proper
and the assertion output is LOW regardless of all other inputs. manipulation of the inputs, the LS151 can provide any logic
The logic function provided at the output is: function of four variables and its negation.

TRUTH TABLE
E S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 Z Z
H X X X X X X X X X X X H L
L L L L L X X X X X X X H L
L L L L H X X X X X X X L H
L L L H X L X X X X X X H L
L L L H X H X X X X X X L H
L L H L X X L X X X X X H L
L L H L X X H X X X X X L H
L L H H X X X L X X X X H L
L L H H X X X H X X X X L H
L H L L X X X X L X X X H L
L H L L X X X X H X X X L H
L H L H X X X X X L X X H L
L H L H X X X X X H X X L H
L H H L X X X X X X L X H L
L H H L X X X X X X H X L H
L H H H X X X X X X X L H L
L H H H X X X X X X X H L H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care

FAST AND LS TTL DATA

5-2
DUAL 4-INPUT MULTIPLEXER SN54/74LS153
The LSTTL / MSI SN54 / 74LS153 is a very high speed Dual 4-Input
Multiplexer with common select inputs and individual enable inputs for each
section. It can select two bits of data from four sources. The two buffered
outputs present data in the true (non-inverted) form. In addition to multiplexer
operation, the LS153 can generate any two functions of three variables. The
LS153 is fabricated with the Schottky barrier diode process for high speed and
is completely compatible with all Motorola TTL families.
DUAL 4-INPUT MULTIPLEXER
• Multifunction Capability
• Non-Inverting Outputs LOW POWER SCHOTTKY
• Separate Enable for Each Multiplexer
• Input Clamp Diodes Limit High Speed Termination Effects

CONNECTION DIAGRAM DIP (TOP VIEW)

        J SUFFIX
       CERAMIC
CASE 620-09
16
NOTE:
1
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
N SUFFIX
      PLASTIC
        16 CASE 648-08
1
PIN NAMES LOADING (Note a)
HIGH LOW
S0 Common Select Input 0.5 U.L. 0.25 U.L. D SUFFIX
E Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. SOIC
16
I0, I1 Multiplexer Inputs 0.5 U.L. 0.25 U.L. 1 CASE 751B-03
Z Multiplexer Output (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. ORDERING INFORMATION
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges. SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
LOGIC DIAGRAM SN74LSXXXD SOIC

           

           
LOGIC SYMBOL

         

         

 
 
 

  
    
 
  
 

FAST AND LS TTL DATA

5-257
 SN54/74LS153

FUNCTIONAL DESCRIPTION
The LS153 is a Dual 4-input Multiplexer fabricated with Low Za = Ea ⋅ (I0a ⋅ S1 ⋅ S0 + I1a ⋅ S1 ⋅ S0 + I2a ⋅ S1 ⋅ S0 +
Power, Schottky barrier diode process for high speed. It can I3a ⋅ S1 ⋅ S0)
select two bits of data from up to four sources under the control
of the common Select Inputs (S0, S1). The two 4-input multi- Zb = Eb ⋅ (I0b ⋅ S1 ⋅ S0 + I1b ⋅ S1 ⋅ S0 + I2b ⋅ S1 ⋅ S0 +
plexer circuits have individual active LOW Enables (Ea, E b) I3b ⋅ S1 ⋅ S0)
which can be used to strobe the outputs independently. When
the Enables (Ea, Eb) are HIGH, the corresponding outputs (Za, The LS153 can be used to move data from a group of regis-
Zb) are forced LOW. ters to a common output bus. The particular register from
The LS153 is the logic implementation of a 2-pole, 4-posi- which the data came would be determined by the state of the
tion switch, where the position of the switch is determined by Select Inputs. A less obvious application is a function genera-
the logic levels supplied to the two Select Inputs. The logic tor. The LS153 can generate two functions of three variables.
equations for the outputs are shown below. This is useful for implementing highly irregular random logic.

TRUTH TABLE
SELECT INPUTS INPUTS (a or b) OUTPUT
S0 S1 E I0 I1 I2 I3 Z
X X H X X X X L
L L L L X X X L
L L L H X X X H
H L L X L X X L
H L L X H X X H
L H L X X L X L
L H L X X H X H
H H L X X X L L
H H L X X X H H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

FAST AND LS TTL DATA

5-258
QUAD 2-INPUT MULTIPLEXER SN54/74LS157
The LSTTL / MSI SN54 / 74LS157 is a high speed Quad 2-Input Multiplexer.
Four bits of data from two sources can be selected using the common Select
and Enable inputs. The four buffered outputs present the selected data in the
true (non-inverted) form. The LS157 can also be used to generate any four
of the 16 different functions of two variables. The LS157 is fabricated with the
Schottky barrier diode process for high speed and is completely compatible
with all Motorola TTL families. QUAD 2-INPUT MULTIPLEXER
• Schottky Process for High Speed
• Multifunction Capability LOW POWER SCHOTTKY
• Non-Inverting Outputs
• Input Clamp Diodes Limit High Speed Termination Effects
• Special Circuitry Ensures Glitch Free Multiplexing
• ESD > 3500 Volts

CONNECTION DIAGRAM DIP (TOP VIEW) J SUFFIX

CERAMIC
       
CASE 620-09
       16
1
NOTE:
The Flatpak version has
the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
N SUFFIX
PLASTIC
16 CASE 648-08
     
        1

PIN NAMES LOADING (Note a)

HIGH LOW D SUFFIX
S Common Select Input 1.0 U.L. 0.5 U.L. SOIC
16
E Enable (Active LOW) Input 1.0 U.L. 0.5 U.L. 1 CASE 751B-03
I0a – I0d Data Inputs from Source 0 0.5 U.L. 0.25 U.L.
I1a – I1d Data Inputs from Source 1 0.5 U.L. 0.25 U.L.
Za – Zd Multiplexer Outputs (Note b) 10 U.L. 5 (2.5) U.L. ORDERING INFORMATION
NOTES:
SN54LSXXXJ Ceramic
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
SN74LSXXXN Plastic
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges. SN74LSXXXD SOIC

LOGIC DIAGRAM
          LOGIC SYMBOL
         

        

        

 

   

 

     

   
    
   

FAST AND LS TTL DATA

5-268
 SN54/74LS157

FUNCTIONAL DESCRIPTION
The LS157 is a Quad 2-Input Multiplexer fabricated with the Za = E ⋅ (I1a ⋅ S + I0a ⋅ S) Zb = E ⋅ (I1b ⋅ S + I0b ⋅ S)
Schottky barrier diode process for high speed. It selects four Zc = E ⋅ (I1c ⋅ S + I0c ⋅ S) Zd = E ⋅ (I1d ⋅ S + I0d ⋅ S)
bits of data from two sources under the control of a common
Select Input (S). The Enable Input (E) is active LOW. When E A common use of the LS157 is the moving of data from two
is HIGH, all of the outputs (Z) are forced LOW regardless of all groups of registers to four common output busses. The partic-
other inputs. ular register from which the data comes is determined by the
The LS157 is the logic implementation of a 4-pole, state of the Select Input. A less obvious use is as a function
2-position switch where the position of the switch is deter- generator. The LS157 can generate any four of the 16 different
mined by the logic levels supplied to the Select Input. The logic functions of two variables with one variable common. This is
equations for the outputs are: useful for implementing highly irregular logic.

TRUTH TABLE
SELECT
ENABLE INPUT INPUTS OUTPUT
E S I0 I1 Z
H X X X L
L H X L L
L H X H H
L L L X L
L L H X H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

FAST AND LS TTL DATA

5-269
 DM74LS194A 4-Bit Bidirectional Universal Shift Register
August 1986
Revised March 2000

DM74LS194A
4-Bit Bidirectional Universal Shift Register
General Description Features
This bidirectional shift register is designed to incorporate ■ Parallel inputs and outputs
virtually all of the features a system designer may want in a ■ Four operating modes:
shift register; they feature parallel inputs, parallel outputs,
Synchronous parallel load
right-shift and left-shift serial inputs, operating-mode-con-
trol inputs, and a direct overriding clear line. The register Right shift
has four distinct modes of operation, namely: Left shift
Parallel (broadside) load Do nothing
Shift right (in the direction QA toward QD) ■ Positive edge-triggered clocking
Shift left (in the direction QD toward QA) ■ Direct overriding clear
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs,
S0 and S1, HIGH. The data is loaded into the associated
flip-flops and appear at the outputs after the positive transi-
tion of the clock input. During loading, serial data flow is
inhibited.
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is HIGH and S1 is LOW.
Serial data for this mode is entered at the shift-right data
input. When S0 is LOW and S1 is HIGH, data shifts left
synchronously and new data is entered at the shift-left
serial input.
Clocking of the flip-flop is inhibited when both mode control
inputs are LOW.

Ordering Code:
Order Number Package Number Package Description
DM74LS194AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS194AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

© 2000 Fairchild Semiconductor Corporation DS006407 www.fairchildsemi.com

DM74LS194A
Function Table
Inputs Outputs
Mode Serial Parallel
Clear Clock QA QB QC QD
S1 S0 Left Right A B C D
L X X X X X X X X X L L L L
H X X L X X X X X X QA0 QB0 QC0 QD0
H H H ↑ X X a b c d a b c d
H L H ↑ X H X X X X H QAn QBn QCn
H L H ↑ X L X X X X L QAn QBn QCn
H H L ↑ H X X X X X QBn QCn QDn H
H H L ↑ L X X X X X QBn QCn QDn L
H L L X X X X X X X QA0 QB0 QC0 QD0

H = HIGH Level (steady state)

L = LOW Level (steady state)
X = Don’t Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
a, b, c, d = The level of steady state input at inputs A, B, C or D, respectively.
QA0, QB0, QC0, Q D0 = The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established.
QAn, QBn, QCn, Q Dn = The level of QA, QB, QC, respectively, before the most-recent ↑ transition of the clock.

Logic Diagram

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