TB62217AFG

TOSHIBA BiCD Process Integrated Circuit Silicon Monolithic

TB62217AFG
PWM drive Stepping Motor Driver / Brush DC Motor Driver Selectable, DC-DC Converter
and Reset function IC

The TB62217FG is a dual stepping motor driver driven by PWM

chopper micro step, with 3- channel step-down DC-DC converters and
an external-IC reset function.
To drive a two-phase bipolar-type stepping motor, a 16-bit latch and
a 16-bit shift register are built into the IC. The IC is suitable for
driving stepping motors with low-torque ripple in a highly efficient
manner. In addition, a signal axis can be switched to serve as a PWM
driver for two DC motors.
By equipping the stepping motor driver with Selectable Mixed
Decay Mode for switching the attenuation ratio during chopping, and
also equipping it with a DC-DC converter, it is possible for the IC to
supply external voltage.
With a built-in timer that starts running when the IC is supplied Weight: 0.45 g (typ.)
with power, the IC can be used in resetting (initializing) external
devices.

Features
• The following motor combinations can be used.

Stepper DC Large DC (L) DC Small DC (S)

(1) Dual motors ⎯ ⎯

(2) Single motor Single motor ⎯
(3) Single motor ⎯ Dual motors
(4) ⎯ Single motor Dual motors
(5) ⎯ Dual motors ⎯
(6) ⎯ ⎯ Quadruple motors

Note Hereafter, DC Large will be referred to as DC (L) and DC Small will be referred to as DC (S).

Recommended maximum
current
Stationary current

The large current standard is achieved by shorting a small current H-Bridge across two ICs. In addition, if the
thermal setting is designed to be within the prescribed thermal range, the initial torque current can be used as the
normal operating current.

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• It is possible to supply external voltage by incorporating three step-down 1.5 V to 5.0 V variable DC-DC
converters.
• A Reset function has been added making it possible to deliver an external reset signal.
• The DMOS motor driver output of this monolithic BiCD IC is capable of achieving a low ON resistance of Ron =
0.6 Ω ( Tj = 25°C, 0.6A: typ.)
• With two sets of internal 16-bit shift register and latch, the IC can drive stepping motors using a 4-bit micro
step.
• Equipped protection circuits: DC-DC converter over current/increased voltage protection, motor over current
protection and total IC over temperature protection.
In addition, equipped with Power On Reset circuit for initializing the IC when the power is turned on and off.
• Package: 64-pin Pb-free QFP package with a heat sink (THQFP64-P-1010-0.50)
• Motor maximum output pressure: 50 V
• On-chip Mixed Decay Mode enables specification of four-stage attenuation ratio.
• Chopping frequency can be set by external oscillator. High-speed chopping is possible at 100 kHz or higher.

Note: When using the IC, exercise great care in regard to thermal conditions.

This device is easy damaged by high static voltage (ESD).

For this reason, please handle with care.

Please Insert an SBD (Schottky Barrier Diode : Recommended "TSB CRS04” ) between "ODB" pin and "D-GND"
pin ,
if using C channel.

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 TB62217AFG

* Pin Layout (4-channel DC Motor Mode , example)

Dch Cch
Driver Driver

Ach Bch
Driver Driver

T-HQFP64-1010-P-0.50
Combinations enclosed in the blue dashed lines are used when in DC (L) mode (A- and B-axis drivers in a pair, and
C- and D-axis drivers in a pair).

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 TB62217AFG
Cautions on connection to the IC pins

Note1 Connect all NC pins (pins left unused) to the lowest potential level (usually to GND).
Note2 Connect any unused Vref pins (28pin,29pin) to GND.
Note3 Unused DATA, CLOCK, and STROBE input pins are pulled down internally, so connect them to GND.
Please ensure that noise is not introduced into the external circuit
Note4 Connect any unused RS pins to VM.
Note5 Connect the feedback pins (FBA, FBB, and FBC) to GND if the corresponding DC-DC converter is
not used.
Note6 Always connect the TEST pin to the lowest potential level (usually to GND).

Note7: TEST pin

The TB62217FG has a test mode function for inspection at the factory. The test mode reduces the “initial
and normal protection mask time” and “ORT output time” to 1/1024 of the respective ratings so as to make the
inspection easier.
To maintain normal operation, therefore, be sure to connect pin 32 to a ground so that it will not be used.

Conditions to use the test mode

32 pin: TEST
Input level 32

High standard operation

100kΩ
Low TEST Mode

Note 8 If the IC is inserted in an incorrect orientation, it will be damaged because a high voltage is applied
to low-voltage blocks. To avoid such damage, always confirm the position of pin 1 and the position
and dimensions of each lead when installing the IC.

Note 9 The IC has no on-chip over voltage protection circuit. Avoid applying a voltage higher than any
rated voltage (such as maximum ratings) to the IC.
Note 10 Solder the heat sink provided on the bottom surface of the IC to a ground-level pattern arranged
for heat release so as to ensure stable operation and efficient heat release.
Note11 Once set up, since the IC is not affected by a logical input from a “Don’t care” pin even if a voltage is
applied to the pin, as long as the applied voltage is not higher than its rating, no problem (such as
a malfunction) will occur.

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 TB62217AFG
Pin Descriptions (initial setup mode)
SLEEP = Low supports a write mode for the initial setup or extended setup mode data.
(1) Pin description (SETUP mode, that is, initial setup or extended setup mode)
(2) Pin description (dual axis stepping motor mode)
(3) Pin description (single axis stepping motor and single axis DC (L) mode)
(4) Pin description (single axis stepping motor and dual axis DC (S) mode)
(5) Pin description (dual axis DC (S) and single axis DC (L) mode)
(6) Pin description (dual axis DC (L) mode)
(7) Pin description (quadruple axis DC (S) mode)

Pin Name Assignment Table

+ + + + + + +

− − − − − − −

17 (ODC) ODC ODC ODC ODC ODC ODC

18 (FBC) FBC FBC FBC FBC FBC FBC

19 (ODB) ODB ODB ODB ODB ODB ODB

20 (FBB) FBB FBB FBB FBB FBB FBB

21 CC CC CC CC CC CC CC

22 OSC_D OSC_D OSC_D OSC_D OSC_D OSC_D OSC_D

23 NC NC NC NC NC NC NC

30 NC NC NC NC NC NC NC

25 VDIN1 VDIN1 VDIN1 VDIN1 VDIN1 VDIN1 VDIN1

26 VDIN2 VDIN2 VDIN2 VDIN2 VDIN2 VDIN2 VDIN2

27 VM VM VM VM VM VM VM

28 (VREF AB) VREF AB VREF AB VREF AB VREF LAB VREF LAB VREF SAB

29 (VREF CD) VREF CD VREF LCD VREF SCD VREF SCD VREF LCD VREF SCD

30 (FBA) FBA FBA FBA FBA FBA FBA

31 (ODA) ODA ODA ODA ODA ODA ODA

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32 TEST TEST TEST TEST TEST TEST TEST Connect to GND

33 DGND1 DGND1 DGND1 DGND1 DGND1 DGND1 DGND1

34 MGND MGND MGND MGND MGND MGND MGND

35 (OUT C−) OUT C− OUT LCD− OUT SC− OUT SC− OUT LCD− OUT SC−

36 (RS C1) RS C1 RS C1 RS C1 RS C1 RS C1 RS C1

37 (RS C2) RS C2 RS C2 RS C2 RS C2 RS C2 RS C2

38 (OUT C+) OUT C+ DOUT LC( OUT SC( OUT SC( OUT LCD( OUT SC(

39 MGND MGND MGND MGND MGND MGND MGND

40 NC NC NC NC NC NC NC

41 NC NC NC NC NC NC NC

42 MGND MGND MGND MGND MGND MGND MGND

43 (OUT D() OUT D( OUT LCD( OUT SD( OUT SD+ OUT LCD+ OUT SD+

44 (RSD1) RSD1 RSD1 RSD1 RSD1 RSD1 RSD1

45 (RSD2) RSD2 RSD2 RSD2 RSD2 RSD2 RSD2

46 OUT D- OUT D- OUT LCD- OUT SD- OUT SD- OUT LCD- OUT SD-

47 MGND MGND MGND MGND MGND MGND MGND

48 C_SELECT C_SELECT C_SELECT C_SELECT C_SELECT C_SELECT C_SELECT

49 - - - ENABLE SD ENABLE SD - ENABLE SD

50 - STROBE CD ENABLE LCD ENABLE SC ENABLE SC ENABLE LCD ENABLE SC

51 TH_OUT TH_OUT TH_OUT TH_OUT TH_OUT TH_OUT TH_OUT

52 LOGIC OUT LOGIC OUT LOGIC OUT LOGIC OUT LOGIC OUT LOGIC OUT LOGIC OUT

53 - - - - - - ENABLE SB

54 STROBE AB STROBE AB STROBE AB STROBE AB ENABLE LAB ENABLE LAB ENABLE SA

55 NC NC NC NC NC NC NC

56 LGND LGND LGND LGND LGND LGND LGND AGND (LGND)

57 LGND LGND LGND LGND LGND LGND LGND AGND (LGND)

58 NC NC NC NC NC NC NC

59 ORT ORT ORT ORT ORT ORT ORT

60 OSC_M OSC_M OSC_M OSC_M OSC_M OSC_M OSC_M

61 - DATA CD - PHASE SD PHASE SD - PHASE SA

-: Don’t care

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 TB62217AFG

Note:H-bridge combination (connection method) for each type of motor driver

VM VM

RRS

RRS
RS pin RS pin

A-phase B-phase

Load Load

PGND PGND

Stepping Motor single motor

VM
RRS

RS pin RS pin

Mutually
connected Load
outside the IC

PGND PGND

DC (L) Single motor

The white circle indicates an IC pin.

Note1: When driving a DC motor in DC (L) mode, avoid an impedance difference outside the IC.

Note2: If the impedance of wiring to mutually connected output transistors is unbalanced, the current that flows
through the transistor also becomes unbalanced and may exceed the maximum rating of the transistor, thus
damaging the transistor.

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 TB62217AFG

VM

RRS
RS pin

Note

Load

PGND

DC (S) Single motor

The white circle indicates an IC pin.

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1. Overall Block Diagram

OSCD FBA ODA FBB ODB FBC ODC CSELECT CC

DC/DC DC/DC
converter DC/DC
selector VM-VDD
DC/DC cnv A converter DC/DC
DC/DC cnv B converter regulator
DC/DC cnv C

VSD unit POR unit

(CC)

Extended
*
setup unit

* These items are provided only

Init setup unit
SLEEP 16-bit latch on the A- and B-axis inputs.
DATA
selector Logic
Current control
out
data logic circuit
Chopping reference circuit
DATA 16-bit
shift register Current OSC_M
Chopping
CLK control
waveform
16-bit latch
generating circuit
STROBE

Current setting circuit

Waveform
4-bit sine D/A shaping circuit
Vref Torque control
(Angle control)

TH_OUT

Current feedback circuit

RS COMP Output control unit
RS VRS
circuit
unit
Thermal
detect
VM

ISD TSD
Outputs unit unit circuit
(H-bridge)

RESET
POR circuit
ORT unit (VM)
Select

Out X Protection circuits

High-voltage wiring (VM)

Stepping DC DC
Logic DATA motor motor
motor
Analog DATA
IC pin

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 TB62217AFG
2-1. Input Equivalent Circuits
(1) Logic Input Pin

21 CC
* 64: PHASE SB
63: PHASE SD
62: PHASE SC
61: PHASE SA
* IN 54: ENABLE SA
100 kΩ 150 Ω To the internal logic 53: ENABLE SB
50: ENABLE SC
49: ENABLE SD
1: SLEEP
56 57 LGND GND

(2) Vref Input Pin

21 CC

28 : Vref AB 2
29 : Vref CD
To the DA circuit

56 57 GND

(3) DC/DC Feed Back Pin (FBx)

150 Ω
30 : FBA
20 : FBB
1.5 V

18 : FBC
2.01 V
1.05 V

57

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 TB62217AFG
2-2. Stepping Motor Logic Unit
(with the same functions for both an A-/B-axis pair and a C-/D-axis pair)
Function
This circuit receives step current setting data entered from the DATA pin and transfers it to the subsequent
stage. It is enabled when the SLEEP pin is high. (If the SLEEP pin is low, the IC enters the initial setup or
extended setup mode.)

Step current setting data logic circuit and setup logic

16-bit shift register

STROBE

CLK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Current
control
16-bit latch

Sleep = H

Phase
Torque Decay Current Phase Decay Current
× 1 bit
× 2 bits × 2 bits × 4 bits × 1 bit × 2 bits × 4 bits
A unit
B unit side B unit side B unit side A unit side A unit side
side

Current DA B-phase DA A-phase

B unit side A unit side
feedback circuit information circuit information
mixed mixed
circuit decay decay
(TRQ setting) timing timing
Output control circuit Output control circuit

Once ORT is released, driving the SLEEP pin high puts the IC in a write mode for stepping motor current
control data. Driving the SLEEP pin from high to low and back to high clears any latched motor control data
(to all low).

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 TB62217AFG
2-3. Initial Setup Logic Unit (available only for the A- / B-axis pair)
Function
This circuit is used to set up driver functions (initial setup) according to signals entered from the DATA pin.
The functions that can be set up include motor re-configuration, digital tBLANK, DC-DC converter ON/OFF
setting, and DC motor mode Vref (gain) setting.

Note: Do not use the TEST mode. Keep all the corresponding bits and any unused pins at a low level.

Logic circuit and setup logic

16-bit shift register

STROBE AB

CLK AB

DATA AB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

L
Initial
setup
16-bit latch

Sleep = L

DC
Motor tBLANK tBLANK DCDC Vref TEST No use
select AB CD select gain (3 bit) (1 bit)
(3 bit) (2 bit) (2 bit) (3 bit) (2 bit)

Note: The setting entered in initial setup mode is in effect if the DATA signal is low when the STROBE signal is
supplied. The initial setup mode data is cleared at POR (power-on reset).

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 TB62217AFG
2-4. Extended Setup Logic Unit (available only for the A- and B-axis pair)
Function
This circuit sets up the monitor functions of the driver IC internal circuits according to a signal entered from
the DATA pin.

Extended setup logic

16-bit shift register

STROBE AB

CLK AB

DATA AB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Extended
setup H
16-bit latch

Sleep = L

Shut down Shut down Reset Pre No use ISD

select mask mask TSD Reserved (1 bit) time
(4 bit) (4 bit) (3 bit) (2 bit) (1 bit)

Note: The internal-signal monitoring setting (entered in extended setup mode) is in effect if the DATA signal is high
when the STROBE signal is supplied. Data for the extended setup mode is cleared at POR (power-on reset).

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 TB62217AFG
3. Current Feedback Circuit and Current Setting Circuit for Motor Driver
Function
The current setting circuit is used to set the reference voltage of the output current using the step current
setting data entered from the serial input pin.
The current feedback circuit is used to deliver a signal to the output control circuit when the output current
reaches the set current. This is done by comparing the reference voltage delivered from the current setting
circuit with the potential difference generated when current flows through the current sense resistor (RRS)
connected between RS and VM.
The chopping waveform generator, to which a capacitor is connected, generates the OSC M (OSC-CLK) as a
chopping frequency reference.
If the Osc_M pin becomes open, the open condition detection function works, thus shutting down the IC. If the
pin is shorted to GND when the IC starts operating, the detection function also works and the IC does not
operate.

Torque From the Current DSC Open Short

OSC_D
0.1 logic unit 0~3 Detect Unit

Vref 15 OSCM
100% Chopping reference
14
85% waveform generator circuit

COSCM
13
70%
12 Step
50%
11 current
10 selector
Torque 9 circuit
control circuit 8
7
6 Mixed
5 decay
4 timing
3 4-bit Waveform shaper circuit
circuit
2 DA
1 circuit Chopping reference generator circuit
0
Output stop signal (ALL OFF)
Current setting circuit

VRS circuit 1
(detects
RS COMP
voltage Output
circuit
difference NF (set current reached signal) control unit
RS between
RS and VM)
RRS

Current feedback circuit

VM

Note: The RE COMP circuit compares the set current with the output current and generates a signal when the
output current reaches the set current.

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 TB62217AFG
4. Output Control Circuit, Current Feedback Circuit, and Current Setting Circuit for
Motor Driver

Chopping reference
Step current setting data logic circuit
generator circuit

Phase Decay Mixed

Output control
circuit mode decay
timing
circuit
Current NT
feedback set current
circuit reached signal Charge start OSC counter

Mixed decay
timing OSC counter (2)

Current U1
Output stop
setting signal Output
U2
circuit driver
L1
circuit
Output control signal L2

Output reset signal

Output circuit ISD circuit

VM
POR circuit
VM-VCC (VM)
regulator Reset signal
CC monitoring
selector
circuit
circuit
CC TSD circuit

VSD circuit

Th_out
Protection circuits

Latched-data
clear signal

VSD : DC-DC output voltage monitor

Logic
VMR : VM power monitor
ISD : Over current protection circuit
TSD : Over-temperature protection circuit

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 TB62217AFG
5. Output Equivalent Circuit for Motor Driver

To VM
RSA RRS A
Output driver
circuit

U1 U2
U1
From U2
OUT A
output L1
control L2
circuit L1 L2 OUT A

Phase A
VM

RSB RRS B
Output driver
circuit

U1 U1 U2
U2 OUT B
From
L1
output M
L2 OUT B
control
circuit L1 L2

Phase B
MGND

The motor output H switch block consists of the upper P-channel DEMOS FET and lower N-channel DEMOS
FET.
Each output DEMOS FET is connected to an over current sense circuit (ISD detection circuit) in parallel.

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 TB62217AFG
6. DC-DC Converter Circuit
When an open detection circuit is available, Osc_D pin is set to open, the IC shuts down. If the pin is shorted to
GND at startup, the IC fails to start operating. (It does not detect in a default.) In the DC-DC converter
operating mode, channel B starts operating before channel A or C.
VDIN OSC_D

(120 pF)
COSC_D
Maximum Rating
CR control circuit

A ch DC-DC converter A
control circuit

LDA
(330 µH) To output

ODA

C_DC_A
(100 µF)

RDCA2 RDCA1
FBA
VSD

DGND
B ch DC-DC converter B
control circuit

LDB
(330 µH) To output

ODB SBD
RDCB2 RDCB1
C_DC_B
(100 µF)

FBB
VSD

C ch DC-DC converter C
control circuit

LDC
(330 µH) To output

ODC
C_DC_C

RDCC2 RDCC1
(100 µF)

FBC
VSD

DGND

Please Insert a SBD( Schottky Barrier Diode : Recommended "TSB CRS04) between
"ODB" Pin to "D-GND" pin.
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 TB62217AFG
7. Reset Circuit (ORT)
This circuit has an open-drain output. If the output is
DC/DC conv
pulled up with a resistor to the supply voltage, its
3.3 V
level becomes low (internally on) at reset and high
(internally Hi-Z) during normal operation (at a

1 kΩ
non-reset). ORT

8. DC-DC Converter Select Circuit (C_SELECT)

*: Each internal circuit resistance varies by ±30%.

CC
To internal 5 V
200 kΩ

supply voltage

150 Ω C_SELECT

200 kΩ is
added if the
voltage is 2.5 V

9. Set Temperature Detection Output Pin (TH-OUT)

It is not necessary to connect a pull-up resistor when choosing ANALOG output mode ( terminal :OPEN)

10. Internal Logic Signal Select Output Pin (LOGIC OUT)

Both the TH-OUT and LOGIC OUT circuits have the same open-drain circuit as the ORT circuit.
If their output pins are pulled up with a resistor to the supply voltage, their levels become low (internally on) at
reset and high (internally Hi-Z) during normal operation (at non-reset).

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 TB62217AFG
16-Bit Serial Input Signals
Three different pieces of data can be entered and set up by combining the CLK, DATA, STROBE and SLEEP pin
inputs.

(1) Extended setup mode (for setting up protection circuits)

(2) Initial setup mode (for setting up motor drive modes)
(3) Stepping motor drive mode (normal drive mode)

Setup Mode Specifications (Initial setup and extended setup modes)

SLEEP

STROBE

CLK

DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Note: The internal-signal monitoring setting (entered in extended setup mode) is in effect if the DATA signal is high
when the STROBE signal is supplied. If the DATA signal is low, initial setup is in effect (initial setup mode).

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 TB62217AFG
(1) Extended Setup Mode Function
(write enabled only when SLEEP = L and Setup Select = H)
• In the extended setup mode, the protection circuits are set up and a monitor setup (output of a Lo_out
pin) of a shutdown signal etc. is performed.

Default
Data Bit Name Function Setting Value
0 SD SELECT 0 0
These 4 bits select what shut-down signal
1 SD SELECT 1 to produce. 0
Selecting a signal at shut-down
See the next item for explanations about
2 SD SELECT 2 0
the 4-bit data combinations.
3 SD SELECT 3 0
4 Unused ⎯ ⎯ 0
5 DCDC VSD SD MASK 0: Normal operation. 0
See the corresponding item below for
6 Motor ISD SD MASK Shut-down signal mask 0
explanations about the 3-bit data
7 TSD SD MASK combinations. 0
8 RESET MASK C 0: Normal operation. 0
1: If the DC-DC converter concerned is shut
9 RESET MASK B down: 0
(1) The RESET signal is not generated.
Disabling the RESET signal at the
(2) All DC-DC converters other than the
shut-down of the corresponding
DC-DC converter of interest operate
DC-DC converter.
10 RESET MASK A normally. 0
(3) The DC-DC converter concerned
returns to normal when the SLEEP
signal changes from low to high.
11 PRE TSD 0 12 11 (← bit) 0
Generating a low signal at the 0 0: TSD-20°C
Th_out pin at a temperature of the 0 1: TSD-30°C
12 PRE TSD 1 TSD temperature − X. 1 0: TSD-40°C 0
1 1: Analog
13 Unused Unused ⎯ 0
OSCM/D Specifying whether to cause 0: OFF (watchdog disabled)
14 0
Watch Dog Setting OSC_M and OSC_D to run. 1: ON (watchdog enabled)
15 Unused Unused ⎯ 0

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 TB62217AFG
[Shut-down signal output (SD select)]
These 4 bits are used to select what shut-down signal to generate. Alternatively, they are used to indicate
vendor or version code.

The shut-down select signals are released when the SLEEP signal changes form low to high.

Data Function
Data (3) Data (2) Data (1) Data (0) Bit
Generate the shut-down signal when the channel A DC-DC
L L L L
converter is shut down with DC-DC VSD_H or DC-DC VSD_L.
Generate the shut-down signal when the channel B DC-DC
L L L H
converter is shut down with DC-DC VSD_H or DC-DC VSD_L.
Generate the shut down signal when the channel C DC-DC
L L H L
converter is shut down with DC-DC VSD_H or DC-DC VSD_L.
L L H H Unused
Generate the shut-down signal when the DC-DC converter is shut
L H L L
down with “DC-DC VSD_H”.
Generate the shut-down signal when the DC-DC converter is shut
L H L H
down with “DC-DC VSD_L”.
Generate the shut-down signal when the DC-DC converter is shut
L H H L
down with “Motor ISD”.
Generate the shut-down signal when the DC-DC converter is shut
L H L H
down with “TSD”.
Revision (0)
H L L L
Deliver bit 0 of the version code.
Revision (1)
H L L H
Deliver bit 1 of the version code.
Revision (2)
H L H L
Deliver bit 2 of the version code.
Vender code:
H L H H
Always deliver “detected” in the TB62217FG.
H H L L Unused
H H L H Unused
H H H L Unused
H H H H Unused

*: Data (3 to 0) = “0000” to “0111” are used to indicate a signal filtered in the internal dead-zone time circuit.

[Shut-down mask]
These 3 bits are used to disable the shut-down function concerned. (One bit corresponds to one function.
When a bit is high, the corresponding function is disabled. Their default value is “LLLL”.)

Data (7): If this bit is high, “TSD” is disabled.

Data (6): If this bit is high, “Motor ISD” is disabled.
Data (5): If this bit is high, “DC-DC VSD” is disabled.

*: Data (4): Unused.

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 TB62217AFG
[RESET output mask]
These 3 bits are used as a signal to specify whether to produce the RESET when the respective DC-DC
converters are shut down.

No low signal is produced as the RESET even if Data (X) = H and one DC-DC channel = H. The default value
of these bits is “L, L, L”.
(When a DC-DC converter is shut down, the RESET is driven low, and all DC-DC channels are turned off.)

If the DC-DC converter concerned is shut down:

(1) No RESET (ORT) is produced.

(2) All DC-DC converters other than that concerned operate normally (rather than being shut down)
(3) Changing the SLEEP signal from low to high restarts the DC-DC converter.

Data (10): DC-DC converter channel A

Data (9): DC-DC converter channel B
Data (8): DC-DC converter channel C

[PRE TSD]
A low signal is generated at the TH_OUT pin if the current temperature is X degrees lower than the TSD
temperature. In analog output mode, a very low voltage proportional to the temperature is generated.
(The analog output mode is dedicated for test use; its specification is not guaranteed and therefore it may
not be able to be used in usual operation.)

Data (12, 11) = 0, 0: TH_OUT is generated (low level) at the TSD temperature − 20°C.
Data (12, 11) = 0, 1: TH_OUT is generated (low level) at the TSD temperature − 30°C.
Data (12, 11) = 1, 0: TH_OUT is generated (low level) at the TSD temperature − 30°C.
Data (12, 11) = 1, 1: Analog output mode.

[Revision and vender]

The revision and vendor codes are specific to an individual version of product.

For example: Revision (0, 1, 2) = (L, L, L) and Vendor = (H) for Toshiba #1.0
Revision (0, 1, 2) = (H, L, L) and Vendor = (H) for Toshiba #1.1
Revision (0, 1, 2) = (L, H, L) and Vendor = (H) for Toshiba #1.2
Revision (0, 1, 2) = (H, H, L) and Vendor = (H) for Toshiba #1.3
Revision (0, 1, 2) = (L, L, H) and Vendor = (H) for Toshiba #2.0

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 TB62217AFG
[OSC_M/OSC_D open-state detection circuit]
The OSC_M/OSC_D open-state detection circuit tries to detect when a capacitor comes off the OSC_M or
OSC_D for some reason by monitoring to see if the frequency gets out of the rated frequency range. When it
detects such an event, it shuts down the IC.

The open-state detection circuit is initially off when the power is turned on.
(To cause it to run, a serial signal must be supplied to make the corresponding bit high.)

The frequency range settings are stated below.

(1) Shut down if the current frequency does not fall in the range: OSC_M frequency/64 > OSC_D frequency
> OSC_M frequency/2

(2) Shut down if the current frequency does not fall in the range: OSC_D frequency × 32 > OSC_M
frequency > OSC_D frequency × 2

Example 1: If the OSC_M frequency is 800 kHz

The IC is shut down when OSC_D frequency > 400 kHz or OSC_D frequency < 12.5 kHz.

2: If the OSC_D frequency is 100 kHz

The IC is shut down when OSC_M frequency > 3200 kHz or OSC_M frequency < 200 kHz.

23 2004-11-12
 TB62217AFG
(2) Initial Setup Mode Select (write enabled only when SLEEP = L and Setup Select = L)
Default
Data Bit Name Function Setting Value
0 Motor Select0 D2 D1 D0 0
0 0 0: Stepper × 2
1 Motor Select1 Motor pairing setting 0 0 1: Stepper × 1 + DCL × 1 0
(See the corresponding pin 0 1 0: Stepper × 1 + DCS × 2
assignment table.) 0 1 1: DCL × 1 + DCS × 2
2 Motor Select2 1 0 0: DCL × 2 0
1 0 1: DCS × 4
3 TBlank AB 0 D4 D3
Channels A and B 0 0: (1 ÷ fChop) ÷ 8 × 5
Noise rejection dead band time 0 1: (1 ÷ fChop) ÷ 8 × 2 0 0
4 TBlank AB 1 setting (See Note below.) 1 0: (1 ÷ fChop) ÷ 8 × 3
1 1: (1 ÷ fChop) ÷ 8 × 4
5 TBlank CD 0 D6 D5
Channels C and D 0 0: (1 ÷ fChop) ÷ 8 × 5
Noise rejection dead band time 0 1: (1 ÷ fChop) ÷ 8 × 2 0 0
6 TBlank CD 1 setting (See Note below.) 1 0: (1 ÷ fChop) ÷ 8 × 3
1 1: (1 ÷ fChop) ÷ 8 × 4
DC-DC converter channel A 0: ON
7 DC/DC A SW (Note)
operation 1: OFF
DC-DC converter channel B 0: ON
8 DC/DC B SW (Note)
operation 1: OFF
DC-DC converter channel C 0: ON
9 DC/DC C SW (Note)
operation 1: OFF
Channels A and B
(A- and B-axis) DC Internal Vref attenuation ratio 0: 1/10
10 0
motor Vref (gain) setting for constant current in DC 1: 1/20
motor mode
Channels C and D
(C- and D-axis) DC Internal Vref attenuation ratio 0: 1/10
11 0
motor Vref (gain) setting for constant current in DC 1: 1/20
motor mode
12 Test IC internal test mode setting Always keep this bit low. 0
13 Test IC internal test mode setting Always keep this bit low. 0
14 Test IC internal test mode setting Always keep this bit low. 0
This bit is not in use.
15 Unused ⎯ 0
Always keep it low.

Note: The initial setting for DATA bits 7, 8, and 9 is determined according to the value of C_SELECT when the VM
power is turned on.

24 2004-11-12
 TB62217AFG
tBLANK (noise rejection dead band time)
The TB62217FG incorporates two different dead band times (blanking times) for different motors to be driven so
as to prevent malfunction because of switching noise.

(1) Analog tBLANK (for stepping motor mode)

The noise rejection dead band time (analog tBLANK), defined by the motor's AC characteristics, is fixed
within the IC. It is used mainly to avoid misjudging Irr (diode recovery time) when a stepping motor is
driven with constant current.
It is fixed within the IC; it cannot be altered.

(2) Digital tBLANK (for DC motor mode)

Unlike the analog tBLANK, this tBLANK time, specified when the initial setup mode is selected, is
generated digitally from an external chopping period. It is used mainly to avoid misjudging the varistor
recovery current that occurs when a DC motor is driven by PWM in the DC motor drive mode.
If the Motor Select signal selects the stepping motor mode, the digital tBLANK is nullified (0 µs), thus
enabling only the analog tBLANK time provided within the IC.
Because the digital tBLANK is generated in reference to the OSC_M, it can be changed by altering the
OSC_M. (Note that altering the OSC_M also changes other items (motor chopping frequency, dead band time
at the time of starting).)

Digital tBLANK time

In the initial setup mode, the tBLANK time can be set to 4 different levels for A-B and C-D pairs as follows:

(1) Immediately after the PHASE has changed

If the PHASE changes, the following time is needed for synchronization with an OSC_M edge and
internal synchronization.

tBLANK time = time need for synchronization between OSC_M and PHASE + set tBLANK time =
internal processing time (OSC_M × 1) + synchronization time (below OSC_M × 1) + set time

(2) Charging in constant-current operation (limiter operation)

tBLANK time = set tBLANK time

The set tBLANK time is as follows:

tBLANK AB (0, 1) & tBLANK CD (0, 1) =:

0 0: OSC_M period × 5
0 1: OSC_M period × 2
1 0: OSC_M period × 3
1 1: OSC_M period × 4

Caution: For #2.0 and after, tBLANK (0, 0) = OSC_M period × 5.

25 2004-11-12
 TB62217AFG
Digital tBLANK Timing in DC Motor Drive Mode

Digital
Digital Digital
Digital tBLANK
tBLANK
tBLANK tBLANK
Phase Digital
tBLANK

Iout

Charge

Iout = 0

Charge start timing in constant-current control

Phase switching point Phase switching point

The digital tBLANK time begins immediately after the external PHASE signal is switched or at the charge start
timing of the constant-current chopper.
The digital tBLANK is effective only in the DC motor drive mode.
The decay mode for DC motor driving is “Fast Decay”.

26 2004-11-12
 TB62217AFG
(3) Data for Normal Stepping Motor Operation
The TB62217FG signals for normal stepping motor operation can be entered in much the same manner as
the drive data of the Toshiba TB62202AF.

Data Bit Name Function Setting

0 Torque A0/B0 A1/B1 A0/B0

0 0 : 50%
Current range setting 0 1 : 70%
1 Torque A1/B1 1 0 : 85%
1 1 : 100%
2 Decay Mode B0 B1 B0
0 0 : 12.5% Decay Mode
Channel B current attenuation ratio setting
0 1 : 37.5% Decay Mode
3 Decay Mode B1 (Mixed Decay Mode)
1 0 : 75% Decay Mode
1 1 : Fast Decay Mode(100%)
4 Current B0
Channel B current setting
5 Current B1 4-bit current data
(Using 4 data bits can divide each step See Setting Table (3).
6 Current B2 into 16.)
(“0000”: All-output OFF mode)
7 Current B3
1: OUT B+ is high.
8 Phase B Channel B current phase information
0: OUT B− is high.
9 Decay Mode A0 A1 A0
0 0 : 12.5% Decay Mode
Channel A current attenuation ratio setting
0 1 : 37.5% Decay Mode
10 Decay Mode A1 (Mixed Decay Mode)
1 0 : 75% Decay Mode
1 1 : Fast Decay Mode(100%)
11 Current A0
Channel A current setting
12 Current A1 4-bit current data
(Using 4 data bits can divide each step See Setting Table (4).
13 Current A2 into 16.)
(“0000”: All-output OFF mode)
14 Current A3
1: OUT A+ is high.
15 Phase A Channel A phase information
0: OUT A− is high.

SLEEP

STROBE

CLK

DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

The initial setup latch, extended setup latch, or normal motor latch is selected as a write latch according to the logical level of the
SLEEP signal and the polarity of the DATA signal at an STROBE signal edge.
If the SLEEP signal is low, the setup latch is selected when the STROBE changes from low to high (initial setup if DATA = low and
extended setup if DATA = high). If the SLEEP is high, the normal motor latch is selected. Don't care the level of the SLEEP during
data transfer.
The stepping motor latches (for both A-B and C-D pairs) are initialized when the SLEEP signal changes from high to low or from
low to high.
All registers are initialized at POR.
The pins used to write during SLEEP include the DATA AB, CLOCK AB, and STROBE AB pins.

27 2004-11-12
 TB62217AFG
Setting Table (1) D0 and D1
Torque setting

The peak torque current can be switched using 2-bit data. (Switching is the same for both the A-B and C-D
pairs.)
Setting
Data Bit Name Function Torque 1 Torque 0
Torque (typ.)
0 0 50%

0 Torque0 0 1 70%
Sets current range
1 Torque1
1 0 85%
1 1 100%

Setting Table (2) D2, D3, D9, and D10

Decay mode x1 and x0 settings

A value of 37.5% is recommended for a typical condition. Data of (0, 0) specifies a 12.5% decay mode.
Setting
Data Bit Name Function Decay Mode 1 Decay Mode 0
Decay mode
0 0 Mixed Decay Mode: 12.5%
2
3 Decay Mode A1/A0 0 1 Mixed Decay Mode: 37.5%
Sets mixed decay
9 Decay Mode B1/B0 1 0 Mixed Decay Mode: 75%
10
1 1 Fast Decay Mode (100%)

Setting Table (3) D4, D5, D6, and D7

Current B setting
Set angle
Data Bit Step Current B3 Current B2 Current B1 Current B0 Current (%)
(degrees)
4 16 1 1 1 1 90 100
5
6 15 1 1 1 1 84 100
7
14 1 1 1 0 79 98
13 1 1 0 1 73 96
12 1 1 0 0 68 92
11 1 0 1 1 61 88
10 1 0 1 0 56 83
9 1 0 0 1 51 77
8 1 0 0 0 45 71
7 0 1 1 1 39 63
6 0 1 1 0 34 56
5 0 1 0 1 28 47
4 0 1 0 0 23 38
3 0 0 1 1 17 29
2 0 0 1 0 11 20
1 0 0 0 1 6 10
0 0 0 0 0 0 0

28 2004-11-12
 TB62217AFG
Setting Table (4) D11, D12, D13, and D14
Current A setting
Set angle value
Data Bit Step Current A3 Current A2 Current A1 Current A0 Current (%)
(degrees)
11 16 1 1 1 1 90 100
12
13 15 1 1 1 1 84 100
14
14 1 1 1 0 79 98
13 1 1 0 1 73 96
12 1 1 0 0 68 92
11 1 0 1 1 61 88
10 1 0 1 0 56 83
9 1 0 0 1 51 77
8 1 0 0 0 45 71
7 0 1 1 1 39 63
6 0 1 1 0 34 56
5 0 1 0 1 28 47
4 0 1 0 0 23 38
3 0 0 1 1 17 29
2 0 0 1 0 11 20
1 0 0 0 1 6 10
0 0 0 0 0 0 0

Setting Table (5) D8 and D15

Phase A setting (this table applies also to phase B.)

The polarity of the phase A current of a stepping motor is determined as listed below.

Data Bit Name Function Phase Setting Phase

OUT A: L, OUT A-: H

0
8 Phase B OUT B: L, OUT B-: H
Switches phase
15 Phase A
OUT A: H, OUT A-: L
1
OUT B: H, OUT B-: L

29 2004-11-12
 TB62217AFG
Functions of External Input Pins

(1) PHASE Input Pin (PHASE X)

This pin indicates the polarity of the H switch used in driving a DC motor. PWM can be applied by
performing time control (duty control) on this pin.

Pin No. Name Function Logical Level Setting Phase

61 PHASE SA L OUT X: L, OUT X-: H

64 SB Switches phase
62 SC H OUT X: H, OUT X-: L
63 SD

(2) ENABLE Input Pin (ENABLE X)

This pin indicates whether to supply the power to a DC motor to be driven.

Pin No. Name Function Logical Level Setting Enable

54 ENABLE SA OFF
Whether to activate L
53 SB (All transistors for the H switch are off.)
50 SC the output
49 SD H Active

(3) SLEEP Input Pin

When the level of this pin is switched from high to low or low to high, all motor drive registers are cleared
(all bits of the 16-bit latch for selecting a motor drive are cleared to low).
After the IC is shut down in motor ISD operation, changing the SLEEP signal from high to low and to high
again causes the IC to return to normal.

Pin No. Name Function Logical Level Setting Sleep

Power consumption reduction mode and initial

L
1 SLEEP Power saving mode setup mode
H Motor operation mode

(4) C_SELECT Input Pin

This pin determines which DC-DC converter to run (ON-OFF combinations) when the power is turned on.

Pin No. Name Function Logical Level Setting Phase

A ch: OFF
Low B ch: OFF
C ch: OFF

DC-DC converter A ch: ON

48 C_SELECT Mid B ch: ON
mode at start
C ch: OFF
A ch: OFF
High B ch: ON
C ch: ON

Note: If the C_SELECT pin is on the mid level, channel B is turned on before channel A. If it is high, channel B is
turned on before channel C.

30 2004-11-12
 TB62217AFG
Protection Operations
(1) When the RESET output mask is “1” in the extended setup mode

Detected Error and Detection Block Operation State

DC/DC A DC/DC B DC/DC C Motor Entire IC DC/DC DC/DC DC/DC Reset Output Reset Method
Motor
VSD VSD VSD ISD TSD A B C

Not Not Not Not Not Normal Normal Normal Normal

H ⎯
detected detected detected detected detected operation operation operation operation
Not Not Not Not DCDC Normal Normal Normal
Detected H SLEEP/POR
detected detected detected detected OFF operation operation operation
Not Not Not Not Normal DCDC Normal Normal
Detected H SLEEP/POR
detected detected detected detected operation OFF operation operation
Not Not Not Not Normal Normal DCDC Normal
Detected H SLEEP/POR
detected detected detected detected operation operation OFF operation
Not Not Not Not Normal Normal Normal
Detected OFF L pulse SLEEP/POR
detected detected detected detected operation operation operation
Not Not Not Not Shut Shut Shut Shut
Detected L POR
detected detected detected detected down down down down

Stop state in the protection operations listed above

• Shut-down = all the functions stop as a failure related to the entire system occurs. They can be restarted
only by initializing using the POR when the VM power is turned on again.
• OFF = only the motor block stops operating. It can be restarted by changing the SLEEP signal from high
to low and to high again.
• L Pulse: The ORT keeps producing low pulses for 40 ms (if OSCM = 800 kHz).
• DC-DC OFF = only the DC-DC converter concerned stops operating. It can be restarted as stated below
depending on the logic level on which the SLEEP signal is when the converter stops operating.

(1) If the SLEEP is low when the DC-DC converter stops, it can be restarted by changing the SLEEP
signal from low to high.
(2) If the SLEEP is high when the DC-DC converter stops, it can be restarted by changing the SLEEP
signal from high to low and to high again.

31 2004-11-12
 TB62217AFG
(2) When the RESET output mask is “0” in the extended setup mode
Detected Error and Detection Block Operation State
DC/DC A DC/DC B DC/DC C Motor Entire IC Reset Output Reset Method
DC/DC A DC/DC B DC/DC C Motor
VSD VSD VSD ISD TSD
Not Not Not Not Not Normal Normal Normal Normal
H ⎯
detected detected detected detected detected operation operation operation operation
Not Not Not Not Shut Shut Shut Shut
Detected L POR
detected detected detected detected Down Down Down Down
Not Not Not Not Shut Shut Shut Shut
Detected L POR
detected detected detected detected Down Down Down Down
Not Not Not Not Shut Shut Shut Shut
Detected L POR
detected detected detected detected Down Down Down Down
Not Not Not Not Normal Normal Normal
Detected OFF L Pulse SLEEP/POR
detected detected detected detected operation operation operation
Not Not Not Not Shut Shut Shut Shut
Detected L POR
detected detected detected detected Down Down Down Down

Stop state in the protection operations listed above

• Shut-down = all the functions stop as a failure related to the entire system occurs. They can be restarted
only by initializing using the POR when the VM power is turned on again.
• OFF = only the motor block stops operating. It can be restarted by changing the SLEEP signal from high
to low and to high again.
• Low Pulse: Low pulses are generated for 40 ms (if OSCM = 800 kHz).

Protection Circuit Dead Band Time

(example in which the reference clock (Osc_M) frequency is 800 kHz)
Protection Protection Mask
Function Block Detected Width Example: Time for OSCM = 800 kHz Reset Method

Supplying VM power
TSD Entire IC 12 to 16CLK 15 to 20 µs
again
No function is
DC-DC converter ⎯ ⎯
available
ISD Driving the SLEEP pin
Motor 4 to 8CLK 5 to 10 µs low or supplying VM
power again
Supplying VM power
VSD DC-DC converter 12 to 16CLK 15 to 20 µs
again

Note: To put protection into effect, the protection circuit must keep operating for at least the time stated above.

32 2004-11-12
 TB62217AFG
(1) Extreme Voltage Drop Protection Function VSD (when detected, the IC is shut down)

Set voltage
+40% (typ.)
Set voltage
DC-DC converter Set voltage
Channel A/B/C output −30% (typ.)
12~16 CLK
GND

Reset output

GND

(2) Extreme Voltage Drop Protection Function VSD During Current Limiter Operation
(when detected, the IC is shut down)

Set voltage +40% (typ.)

OSC_D: 3 CLK
Set voltage
DC-DC converter −30% Set voltage −15% (typ.)
Channel A/B/C output
GND
Current limiter operation Limiter state
GND

Reset output
GND

(3) IC Overheat Protection Function (TSD) (when detected, the IC is shut down)

Overheat
protection value

IC junction temperature
12~16 CLK

Reset output

GND

Note: A low-pulse period of 40 ms is applied when OSC_DM frequency = 800 kHz and clock = 1.25 µs.

4) Motor Over Current Protection Function (when detected, only the motor is stopped)

Over current

Motor output current

4~8 CLK
GND
32768 clock
Reset output (40 ms typ.)

GND

33 2004-11-12
 TB62217AFG
Power Supply Sequence
If the C_SELECT pin is driven mid or high
The 1st DC-DC converter represents channel B, and the 2nd DC-DC converter, channel A or C.

6V 6V

10 µs
POR
POR

Internal logic start

10 ms Internal logic

1st DC-DC converter operation start

20 ms
1st DC-DC converter

2nd DC-DC converter operation start

20 ms
2nd DC-DC converter

Protection mask end

Protection mask

ORT
100 ms
ORT
Serial data acceptable
max 320 ms

Note: If the C_SELECT pin specifies that all DC-DC converters be off, the ORT reset time is 320 ms.

If serial data specifies DC-DC converters be turned on after the power is turned on (C_SELECT: Low)

DC-DC converter channel A operation start

Channel A protection mask

100 ms

DC-DC converter channel B operation start

Channel B protection mask

100 ms

DC-DC converter channel C operation start

Channel C protection mask

100 ms

34 2004-11-12
 TB62217AFG
Maximum Ratings (Ta = 25°C)

Characteristics Symbol Rating Unit Remark

Motor output voltage VM 50 V

Motor output current IOST 1.3 A/phase Stepper

(Note 1) IOSAP 8? A DC motor S (500 ns)

(Note 2)
IOSAE 3 A DC motor S (100 ms)
ICO A 750 mA
DC-DC converter output current IDC B 400 mA
IDC C 400 mA
Current detection pin voltage VRS VM ± 4.5 V
Reset pin supply voltage VRST 5 V
Reset output current IRST −60 mA
Logic input voltage VIN −0.4 to 6.0 V
When Ta exceeds 25°C, this
1.25 W figure must be de-rated by
10.0mW /°C. (Note 3)
Power dissipation PD
When Ta exceeds 25°C, this
4.2 W figure must be de-rated by
33.65mW /°C. (Note 4)
Operating temperature Topr −40 to 85 °C
Storage temperature Tstg −55 to 150 °C
Junction temperature Tj 150 °C

Note 1: See other tables for pairing.

Note 2: Peak maximum during DC motor drive (below 500 ns)

Note 3: Stand-alone measurement (Ta = 25°C)

Note 4: When the IC is mounted on a dedicated board (Ta = 25°C)

Ta: IC ambient temperature
Topr: IC ambient temperature during operation
Tj: IC chip temperature during operation
The maximum Tj value is limited by the TSD (thermal shut-down circuit) temperature

35 2004-11-12
 TB62217AFG
Recommended Operating Conditions (Ta = 0 to 85°C)

Characteristics Symbol Test Condition Min Typ. Max Unit

6
Excluding motor block 27 40 V
VM supply voltage VM (Note 1)
Motor block 18 27 40
Per phase (in single-axis drive) at Ta =
IOLA Stepper ⎯ 0.6 1.0
25°C
Per H-bridge with peak of 500 ns at Ta
Output current ⎯ 0.8 6.4 A
= 25°C
IOSL DC
Per H-bridge with pulse of 100 ms at
⎯ 0.8 2.4
Ta = 25°C
IDCi A
Before the ORT signal is output ⎯ ⎯ 100 mA
(Note 2)
DC-DC converter initial output
current IDCi B
IDCi C Before the ORT signal is output ⎯ ⎯ 100 mA
(Note 2)
IDC A After the ORT signal is output ⎯ ⎯ 600 mA
DC-DC converter output current IDC B
After the ORT signal is output ⎯ ⎯ 300 mA
IDC C
Logic input voltage VIN ⎯ GND 3.3 5.0 V
Clock frequency fCLK 1.0 ⎯ 25 MHz
Motor chopping frequency range fchop ⎯ 100 ⎯ kHz
⎯ ⎯ VM = 40 V ⎯ 800 ⎯ ⎯
Vref reference voltage input
Vref 0.8 2.0 3.0 V
range

Note 1: A voltage of 7 V or higher is recommended for typical use. A VM voltage range between 6 V (POR voltage)
and 7 V inclusive allows the DC-DC converter to exhibit much the same characteristics as when VM = 7 V
(except that the voltage error becomes ±10%). However, it is recommended to use the IC at 7 V or higher
(partly to allow for a margin of stability), because both the rising POR (power-on reset voltage) and falling
POR (shut-down voltage) are 6 V.

Note 2: When the power is turned on, soft start is put in effect by limiting the current to the DC-DC converter input
block. The limited current results in the output current being limited. If an attempt is made to turn on the
power with a load current flowing, it is likely that the DC-DC converter may fail to start or that the output
voltage may abruptly increase when the soft-start current is switched.

36 2004-11-12
 TB62217AFG
Motor Block Electrical Characteristics 1
(unless otherwise specified, Ta = 25°C and VM = 18V ~ 40 V)
Test
Characteristics Symbol Test Condition Min Typ. Max Unit
Circuit
HIGH VIH CLK, STROBE, DATA, ENABLE, 2.0 ⎯ ⎯
Logic input voltage DC SLEEP, and PHASE logic input
LOW VIL pins ⎯ ⎯ 0.8 V

Logic input clamp voltage VIK IIK = −10 mA ⎯ ⎯ −0.4

CLK, STROBE, DATA, ENABLE,
Logic input hysteresis VIN(HIS) DC 0.1 0.2 0.3 V
and SLEEP input pins
IIN(H) Vin = 3.3 V at each of the CLK, ⎯ ⎯ 60
Logic input current DC STROBE, DATA, ENABLE, and µA
IIN(L) SLEEP logic input pins ⎯ ⎯ 60

Sleep Mode
IM1 Sleep = L, ALL DC/DC = OFF ⎯ ⎯ 2
(IC bias Current)
Sleep = H
Operating current (VM pin) DC OSC_D = 100 kHz, mA
Motor = OFF
IM2 DC/DC_A = OFF ⎯ ⎯ 15
DC/DC_B = 1.5 V
DC/DC_C = 3.3 V
Iout_chB + Iout_chC = 10 mA
Upper VRS = VM = 40 V, Vout = 0 V,
Output standby current IOH 0 ⎯ 1
side Output OFF Mode
DC µA
Lower VRS = VM = Vout = 40 V
Output leakage current IOL −1 ⎯ 1
side Output OFF Mode

HIGH Vref = 2.0 V, Vref (gain) = 1/10,

VRS (HH) ⎯ 100 ⎯
(reference) TORQUE = (H.H) = 100%
%
MIDDLE Vref = 2.0 V, Vref (gain) = 1/10,
Comparator VRS (HL) DC 83 85 87
HIGH TORQUE = (L.H) = 85%
reference
voltage ratio MIDDLE Vref = 2.0 V, Vref (gain) = 1/10,
VRS (LH) 68 70 72
LOW TORQUE = (H.L) = 70%
Vref = 2.0 V, Vref (gain) = 1/10,
LOW VRS (LL) 48 50 52
TORQUE = (L.L) = 50%
Output current difference between
Output current difference between
∆Iout1 DC adjacent channels at Iout = 600 −5 ⎯ 5 %
channels in constant-current mode
mA
Constant-current output setting
∆Iout2 DC Iout = 600 mA −5 ⎯ 5 %
difference
RS pin current IRS DC VRS = 40 V, VM = 40 V ⎯ ⎯ 10 µA
Iout = 0.6 A, Tj = 25°C, normal
RON (D-S) 1 ⎯ 0.6 0.72
direction
Iout = 0.6 A, Tj = 25°C, reverse
RON (D-S) 1 ⎯ 0.6 0.72
On-state resistance between motor direction
DC Ω
output transistor drain and source Iout = 0.6 A, Tj = 105°C, normal
RON (D-S) 2 ⎯ 0.78 1.01
direction
Iout = 0.6 A, Tj = 105°C, reverse
RON (D-S) 2 ⎯ 0.78 1.01
direction

37 2004-11-12
 TB62217AFG
Motor Block Electrical Characteristics 2
(unless otherwise specified, Ta = 25°C and VM =18V ~ 40 V)
Test
Characteristics Symbol Test Condition Min Typ. Max Unit
Circuit
Vref input voltage Vref DC When motor output is active 0.8 ⎯ 3.0 V
When motor output is inactive and
Vref input current Iref DC ⎯ ⎯ 1.0 µA
Vref = 2.0 V
Vref
1/9.6 1/10 1/10.4
(Gain10) When motor output is active and
Vref attenuation ratio DC ⎯
Vref Vref = 2 V
1/19.2 1/20 1/20.8
(Gain20)
VMR
⎯ ⎯ 14 15
(Up)
Motor power return voltage DC V
VMR
13 14 ⎯
(Down)
Recommended capacitance for External capacitance at fosc_M =
Cosc_M ⎯ ⎯ 220 ⎯ pF
OSC_M pin 800 kHz
Operating current for motor over ISD
DC fchop = 100 kHz 3.0 5.0 6.0 A
current protection circuit (Note)

Note: Over current protection circuit

If an abnormal current higher than the corresponding rating flows through a motor, the overcurrent protection
circuit triggers the internal shut-down circuit to turn off the output block. In this case, the currently latched
function data is cleared.
The overcurrent protection circuit is kept tripped for the motor block until (1) the power is turned on again or
(2) the SLEEP returns to a high level.
If ISD comes in effect, the output becomes inactive (ALL OFF state) and is kept so until a normal condition is
recovered. However, be sure to insert a fuse into the power supply for sake of fail-safe.

38 2004-11-12
 TB62217AFG
Electrical Characteristics DC_3
(unless otherwise specified, Ta = 25°C, VM =18V ~ 40 V, and motor Iout = 1.0 A)
Test
Characteristics Symbol Test Condition Min Typ. Max Unit
Circuit
θA = 90 (θ16) ⎯ 100 ⎯
θA = 84 (θ15) ⎯ 100 ⎯
θA = 79 (θ14) 93 98 ⎯
θA = 73 (θ13) 91 96 ⎯
θA = 68 (θ12) 87 92 97
θA = 62 (θ11) 83 88 93
θA = 56 (θ10) 78 83 88
θA = 51 (θ9) 72 77 82
Chopper current vector ⎯ DC θA = 45 (θ8) 66 71 76
θA = 40 (θ7) 58 63 68
θA = 34 (θ6) 51 56 61
θA = 28 (θ5) 42 47 52
θA = 23 (θ4) 33 38 43
θA = 17 (θ3) 24 29 34
θA = 11 (θ2) 15 20 25
θA = 6 (θ1) 5 10 15
θA = 0 (θ0) ⎯ 0 ⎯

39 2004-11-12
 TB62217AFG
Electrical Characteristics DC_4 (unless otherwise specified, Ta = 25°C and VM = 40 V)
Test
Characteristics Symbol Test Condition Min Typ. Max Unit
Circuit
(Automatically created within the
IC)
Internal logic supply voltage Vcc DC 4.5 5.0 5.5 V
External capacitance: Under
consideration
TjTSD
TSD operating temperature DC ⎯ 130 150 170 °C
(Note 1)
−20°C (serial setting) 110 150
PRE TSD detection temperature PRE TSD DC −30°C (serial setting) 100 140 °C

−30°C (serial setting) 90 130

VTHO
H 3.2 ⎯ ⎯
(H)
Th_out output voltage V
VTHO
L 0 ⎯ 0.4
(L) When pull up to 3.3 V with an
LO external resistance of 1 kΩ
H 3.2 ⎯ ⎯
(H)
LOGIC OUT V
LO
L 0 ⎯ 0.4
(L)

Note: The maximum Tj should not exceed 120°C.

Thermal shut-down (TSD) circuit

TSD comes in effect if the IC junction reaches a rated temperature. It causes the internal reset circuit to
operate, thus turning off the output block. (Only one TSD circuit is mounted on the IC.)

The TSD operating temperature can be set anywhere in a range between 130°C (min) and 170°C (max).
When TSD comes in effect, the currently latched function data is initialized and the output is stopped.

Once the supply voltage drops to or below the POR voltage to shut down the IC, increasing the supply
voltage above the POR reset voltage initializes and restarts the IC.

40 2004-11-12
 TB62217AFG
DC-DC Converter Block Electrical Characteristics (Tj = 0 to 120°C and VM = 7 to 40 V)
Test
Characteristics Symbol Test Condition Min Typ. Max Unit
Circuit
VM = 6.5 V~40 V
Tj = 0~120°C
Output voltage error ∆Vout DC 0.5 mA~600 mA (large) −7.0 0 7.0 %
0.5 mA~300 mA (small)
DCDC output = 1.5 to 5 V

DC-DC converter output-off VM = 40 V, upper side −0.1 ⎯ 0.1

IOL_DC DC µA
leakage current VM = 40 V, lower side −0.1 ⎯ 0.1
Iout = 300 mA, Tj = 25°C, reverse
On-state resistance between RON (DS) A1 ⎯ 0.7 0.84
direction
output transistor drain and source DC Ω
(large DCDC Unit: Ach) Iout = 300 mA, Tj = 105°C, reverse
RON (DS) A2 ⎯ 0.9 1.1
direction
RON (DS) Iout = 150 mA, Tj = 25°C, reverse
On-state resistance between ⎯ 1.4 1.7
BC1 direction
output transistor drain and source DC Ω
(small DCDC Unit: B, Cch) RON (DS) Iout = 150 mA, Tj = 105°C, reverse
⎯ 1.8 2.2
BC2 direction
ILIM (L)
0.8 1.2 1.6
DC (large)
Current limiter value (steady state) ⎯ A
ILIM (S)
0.5 0.6 0.85
DC (small)
ILIM (L)
DC 0.2 0.3 0.4
DC (large)
Current limiter value (starting) ⎯ A
ILIM (S)
0.2 0.3 0.4
DC (small)
VSD (U) In reference to the set voltage. +30 +40 +50
%
VSD (L) The current limiter is inactive. −40 −30 −20
Abnormal-voltage protection circuit
VSD (LU) In reference to the set voltage. +30 +40 +50
%
VSD (LL) The current limiter is active. −20 −15 −5
OSC_D capacitor value Cosc_D ⎯ External capacitor value 47 120 ⎯ pF
Feedback voltage VFB DC ⎯ ⎯ 1.5 ⎯ V
DC/DC A, B, Cch All OFF ⎯ 0 0.8
C_SELECT voltage VC_sel DC DC/DC A, Bch ON 1.25 2.5 3.75 V

DC/DC Bch, Cch ON 4.5 5.0 ⎯

Reset Block Electrical Characteristics DC (Tj = 0 to 120°C and VM = 7 to 40 V)

Test
Characteristics Symbol Test Condition Min Typ. Max Unit
Circuit
Rising side.
VMR
All functions change from OFF to 5.2 ⎯ 6.0
(ALL, Up) ON.
POR output voltage for VM supply
DC V
voltage detection
Falling side.
VMR
All functions change from ON to 5.2 ⎯ 6.0
(ALL, Down) OFF.
ORT signal output current IRST DC Reset pin voltage = 0.4 V 2 ⎯ ⎯ mA
Vort (H) Pulled up to 3.3 V with an external 3.2 ⎯ ⎯
ORT output pin voltage DC V
Vort (L) resistance of 1 kΩ 0 ⎯ 0.4

41 2004-11-12
 TB62217AFG
Motor Block AC Electrical Characteristics
(Ta = 25°C, VM = 40 A, and motor impedance = 6.8 mH/5.7 Ω)
Test
Characteristics Symbol Test Condition Min Typ. Max Unit
Circuit
Vin = 3.3 V
Input clock frequency fCLK AC 1.0 ⎯ 25 MHz
CLK input pin
tw (CLK) 40 ⎯ ⎯
Minimum clock pulse width twp (CLK) AC Vin = 3.3 V 20 ⎯ ⎯ ns

twn (CLK) 20 ⎯ ⎯
tSTROBE 40 ⎯ ⎯
Minimum STROBE pulse width tSTROBE (H) AC Vin = 3.3 V 20 ⎯ ⎯ ns

tSTROBE (L) 20 ⎯ ⎯
tsuSIN-CLK 10 ⎯ ⎯ ns
Data setup time AC Vin = 3.3 V
tsuST-CLK 10 ⎯ ⎯
thSIN-CLK 10 ⎯ ⎯
Data hold time AC Vin = 3.3 V ns
thCLK-ST 10 ⎯ ⎯
Tr(s) 6.8 mH/5.7 Ω load 0.1 0.3 0.5
Tf(s) (Small mode) 0.1 0.3 0.5
Tr(L) 6.8 mH/5.7 Ω load 0.1 0.3 0.5
Tf(L) (Large mode) 0.1 0.3 0.5
tpLH (STB) Step Motor mode ⎯ 15 ⎯
6.8 mH/5.7 Ω load between
tpHL (STB) STROBE (↑) and OUT ⎯ 10 ⎯

Output switching time tpLH (OscM) AC Step Motor mode ⎯ 1.2 ⎯ µs

6.8 mH/5.7 Ω load between Osc
tpHL (OscM) down edge and OUT 2.5

tpLH (ENA) DC Motor mode 0.3 ⎯ 0.9

tpHL (ENA) Between ENABLE edge and OUT 0.3 ⎯ 0.9
tpLH
0.3 ⎯ 0.9
(PHASE) DC Motor mode
tpHL Between PHASE edge and OUT
0.3 ⎯ 0.9
(PHASE)
Noise rejection analog dead band tBLANK
AC Iout = 0.6 A 200 300 400 ns
time (Analog)
Motor chopper reference signal
fOSC_M AC C_OSC_M = 220 pF 600 800 1000 kHz
oscillation frequency
fchop (Min)
Frequency range in which motor Output active (Iout = 0.6 A) with
fchop (Typ.) 40 100 150 kHz
chopping is supported fixed steps
fchop (Max) AC

Output active (Iout = 0.6 A)

Motor chopping setting frequency fchop (M) ⎯ 100 ⎯ kHz
M_osc CLK = 800 kHz

42 2004-11-12
 TB62217AFG

Control signal timing chart

tw(CLK)

CLOCK 50% 50

tsuST-CLK thCLK-ST twn(CLK) twp(CLK)

STROBE 50%

tSTROBE(H)
tSTROBE(L)

thCLK-ST tSTROBE

tsuSIN-CLK

DATA 50% DATA15 50% DATA0 DATA1

OSCM

tpHL(OSCM)
fOSC_M
tpHL(STB)

OUT A - 50%

tpLH(OSCM)

tpLH(STB)
90%

OUT A + 50%
10%

tr tf

PHASE 50%

tpHL(PHASE)

OUT A - 50%

tpLH(PHASE)

OUT A + 50%

ENABLE 50% 50%

tpLH(ENA) tpHL(ENA)

OUT A + 50%

PHASE

OUT A

43 2004-11-12
 TB62217AFG
DC-DC Converter AC Electrical Characteristics (Tj = 0 to 120°C and VM = 40 V)
Test
Characteristics Symbol Test Condition Min Typ. Max Unit
Circuit

Output transistor switching tr_D(L) ⎯ 0.1 ⎯

AC VM = 40 V, DCDC Ach (Large) µs
characteristic (large)
tf_D(L) ⎯ 0.1 ⎯

Output transistor switching tr_D(S) ⎯ 0.1 ⎯

AC VM = 40 V, DCDC B/Cch (small)
characteristic (small) tf_D(S) ⎯ 0.1 ⎯
Output transistor feed-through
tOFF AC VM = 40 V 100 300 ns
prevention time
fchop_D
DC-DC setting frequency AC ⎯ ⎯ 100 200 kHz
(OSC_D)
The DC-DC converter is turned on
independently of others, using
Protection circuit dead band tStrart serial data.
AC ⎯ 100 ⎯ ms
(MASK) time at startup _Mask fosc_M = 800 kHz and after the
STROBE signal has been
accepted
At fosc_M = 800 kHz and after VM
Initial startup delay time tstart1 AC becomes 6 V or higher but before ⎯ 20 ⎯ ms
the first DC-DC converter starts.
At fosc_M = 800 kHz and after the
first DC-DC converter has started
Initial startup delay time 2 tstart2 AC ⎯ 20 ⎯ ms
but before the second DC-DC
converter starts.
Startup soft mode period tsoft AC fosc_M = 800 kHz ⎯ 20 ⎯ ms
At fosc_M = 800 kHz and after VM
LVCO detection dead band time tLVCO AC becomes 6 V or lower but before ⎯ 10 ⎯ µs
the ORT becomes low.
At fosc_M = 800 kHz and after VM
POR detection dead band time tPOR AC becomes 6 V or lower but before ⎯ 10 ⎯ ms
the internal logic starts.

VM Active
90% Pch G)
Pch GATE
Non- Active
ODX
10% Active
Nch GATE
Nch G)
DGND
tr D(L) tf D(L) Non- Active
tr D(S) tf D(S)
OFF

H
STROBE
L

Active
DC/DC
output
tStart_Mask Non- Active

Mask Active
signal
Non- Active

OSCD

fchop_D

44 2004-11-12
 TB62217AFG
Other Electrical Characteristics AC (Tj = 0 to 120°C and VM = 7 to 40 V)
Test
Characteristics Symbol Test Condition Min Typ. Max Unit
Circuit
From VM power-on POR release
Startup reset release time 1 trst1
AC fosc_M = 800 kHz (114688 clock ⎯ 140 ⎯ ms
(Protection mask time) (Init)
pulses)
From VM power-on POR release
Startup reset release time 2 trst2
AC fosc_M = 800 kHz (262144 clock ⎯ 320 ⎯ ms
(with no DC-DC converter in use) (DCDC OFF)
pulses)
ORT output low-pulse width when fosc_M = 800 kHz (32768 clock
trst(ON) AC 40 ⎯ ⎯ ms
the motor ISD is active pulses)
IRST = 20 mA
tRST Pulled up to CC with a resistance
ORT signal output delay time AC ⎯ 50 ⎯ ns
(Delay) of 200 Ω
Ccc = 0.1 µF
fosc_M = 800 kHz
Internal initial setup timing tInit_time AC ⎯ 10 ⎯ ms
After POR release
tSleep
SLEEP pulse width AC fosc_M = 800 kHz 10 ⎯ ⎯ µs
(ON)
tSleep
SLEEP release delay time AC fosc_M = 800 kHz ⎯ ⎯ 10 µs
(delay)

tLVCO

VM
POR

tPOR

Active
POR tInit_time
Non- Active
Active

Non- Active
t_start1 t_soft Active
1’stDC/DC
Non- Active
t_start2 t_soft Active
2’ndDC/DC
Non- Active
trst1 / trst2 H
ORT
L

Active

Non-Active

Active
ORT
Non-Active

tRST Delay) trst ON)

45 2004-11-12
 TB62217AFG
Calculating the Motor Setting Constant Current
The motor setting current value is determined by RRS and Vref as follows:

Torque (Torque = 100, 85, 70, 50% : input serial data )

Iout (max) = Vref (gain) × Vref (V) ×
RRS ( Ω ) × 100%

Assume, for example:

Vref (gain) = 1/10: The attenuation ratio is typically 1/10 when Vref = 1/10.
Vref =2 (V)
Torque =100 (%)

Producing Iout = 1.0 A requires RRS = 0.20 Ω (at least 0.2 W).

The Vref (gain) is fixed at 1/10 for stepping motors and selectable from 1/10 and 1/20 for DC motors.

The error of constant current setting is 5 % when excluding Vref and Rs .

Calculating the Oscillation Frequency

(chopping reference frequency) for the Motor and DC-DC Converter Blocks

(1) Calculating the OSC Reference Frequency for the Motor Block (typical)

fosc_M = 61820 × C (pF) ^ −0.8043 (kHz)

Hence, the OSC frequency for the motor block is about 810 kHz when Cosc_M = 220 pF.
The chopping frequency for stepping motors is about 1/8 the above frequency, that is, 810/8 (= 101) kHz.
In addition, only the fast decay mode is available for DC motor drive.

(2) Calculating the OSC Frequency for the DC-DC Converter Block (typical)

f OSCD = 5315.3 × C (pF) ^ −0.8341 (kHz)

Hence, the OSC frequency for the DC-DC converter block is about 100 kHz when Cosc_D = 120 pF.

46 2004-11-12
 TB62217AFG
Power Supply Sequence

(1) If C_SELECT = low

VM
POR release

VM
voltage

POR

Soft start mode 20 ms

0

Active
DC/DC ALL OFF Full mode
status
Non-active
10 ms
H
ORT 320 ms
L

Re-writable
Init DATA
All clear Initial value Rewritten with serial data
Extended DATA
All cleared
Initialize
Re-writable
DC/DC DC/DC
control all off (C_Sel = L)
All cleared
Rewritten with serial data
Active
OSC_M
Non-active

Active
OSC_D
Non-active

47 2004-11-12
 TB62217AFG
(2) Normal Start (C_SELECT = mid or high)

VM
VM = 15.0 V
POR release

VM
voltage
POR
Soft start
mode 20ms
0

DC/DC Active
status ALL OFF Full mode
Non-active
10 ms
10 ms

ORT

Re-writable
Init DATA
All clear Initial value Rewritten with serial data
Extended DATA
All cleared
Initialize

SLEEP

Controlled by Re-writable
DC/DC
C SELECT Controlled with serial data
control
All cleared
DC/DC control start

Motor driver OFF OFF

control (Data cleared) (Data cleared)
Operable
(if VM = 15 V or higher)
Active
OSC_M
Non-active

Active
OSC_D
Non-active

Note: POR release → Initialize 10 ms

Initialize → first DCDC start 10 ms
DCDC soft start mode 20 ms

48 2004-11-12
 TB62217AFG
(3) If VM Voltage Drops at Startup (C_SELECT = mid or high)

VM

VM
voltage
POR

10 ms Soft start
mode 20 ms
0 Below 10 µs
Active
DC/DC
status ALL OFF Full mode
Non-active
10 ms
Initialize
H
ORT
L

Re-writable
Init DATA
All clear Initial value Rewritten with serial data
Extended DATA
All cleared

Re-writable
DC/DC Controlled by
control All clear C_SELECT Controlled with serial data
All cleared

Active
OSC_M
Non-active

Active
OSC_D
Non-active

49 2004-11-12
 TB62217AFG
(4) VM Voltage Drop (normal)

VM
VM = 15.0 V

VM
voltage

POR

VM = 0 V

DC/DC Active
Full mode ALL OFF
status
Non-active
10 µs

ORT H

Re-writable
Init DATA
Rewritten with serial data ALL L
Extended DATA All cleared

Re-writable
DC/DC
Rewritten with serial data ALL OFF
control
All cleared

Active
Motor driver Operable OFF (Data cleared)
control (if VM = 15 V or higher)
Non-active

Active
OSC_M
Non-active

Active
OSC_D
Non-active

50 2004-11-12
 TB62217AFG
(5) Supply Voltage Drop (if the VM supply voltage does not cross the POR level)

VM = 15 V

VM
voltage

POR

VM = 0 V

Active
DC/DC Full mode
status
Non-active

H
ORT ORT = H
L

Re-writable
Init DATA
Rewritten with serial data
Extended DATA
All cleared

Re-writable
DC/DC
Rewritten with serial data
control
All cleared

Active
Motor driver
Not operating (if VM = 15 V or lower)
control
Non-active

Active
OSC_M
Non-active

Active
OSC_D
Non-active

51 2004-11-12
 TB62217AFG
(6) Supply Voltage Drop (if the VM supply voltage crosses the POR level)

VM = 15 V

Shut down (ALL OFF)

VM
voltage
POR Initialize

DCDC start
VM = 0 V
Soft start
10 µs mode 20 ms
Active
DC/DC Full mode ALL OFF Full mode
Status
Non-active
10 ms 10 ms
H
ORT
L

Re-writable
Init DATA Rewritten with Rewritten with
serial data ALL = L Initial value
Extended DATA serial data
All cleared

Re-writable
DC/DC Rewritten with Controlled by Rewritten with
serial data ALL = L C_SELECT serial data
control
All cleared

Active
Motor driver Not operating Not operating
(if VM = 15 V or lower) OFF (DATA = ALL L) (if VM = 15 V or lower)
control
Non-active

Active
OSC_M
Non-active

Active
OSC_D
Non-active

52 2004-11-12
 TB62217AFG
Mixed decay Mode Current Waveform and Setting
In constant-current control, the current fluctuation width (current pulsating component) decay mode can be set
to any of four points, 0 to 3, using 2-bit serial data.
The abbreviation “NF” stands for “negative feedback”. It refers to a point where the output current has reached
the set current value. The lower the mixed decay timing value, the lower is the current ripple component (current
crest value), leading to a lower current decay ability.

fchop
CR pin
internal clock
waveform
Set current value
DECAY MODE 0
NF
12.5%
MIXED
DECAY MDT
CHARGE MODE → NF: Set current value reached
→ SLOW MODE → MIXED DECAY TIMMING →
FAST MODE → CHARGE MODE

DECAY MODE 1 Set current value

NF

37.5%
MIXED
DECAY MDT
CHARGE MODE → NF: Set current value reached
→ SLOW MODE → MIXED DECAY TIMMING →
FAST MODE → CHARGE MODE

DECAY MODE 2 Set current value

NF
75%
MIXED
DECAY MDT
CHARGE MODE → NF: Set current value reached
→ SLOW MODE → MIXED DECAY TIMMING →
FAST MODE → CHARGE MODE

DECAY MODE 3
Set current value
FAST
DECAY

CHARGE MODE → NF: Set current value reached

→ FAST MODE

100% 75% 50% 25% 0

53 2004-11-12
 TB62217AFG
Relationships Between the OSC_M and Output Drive Timing

OSC-charge delay OSC-fast delay

H

fosc _M

L
tchop
H
Output 50%
voltage A
L
H
Output
50% 50%
voltage A
L
Set current

Output
current

L
Charge Slow Fast

OSC_M and Charge Delay

A delay of up to 1.25 ns (when fchop = 100 kHz and fCR = 800 kHz) can occur between the OSC waveform and
internal OSC_M CLK, because the rising level of the OSC waveform is used in converting the OSC waveform to the
internal M_CLK.

CR-CR CLK delay

CR waveform

Internal M_CLK

54 2004-11-12
 TB62217AFG
VSD Threshold Change Timing During DC-DC Converter Block Current Limiter
Operation
When the limiter enters an operating state, the VSD circuit starts operating if this state continues for 3 OSC_D
periods.

OSC_D

OSC_D_CLK
(Internal signal)
Case 1

Limiter
operating state
(1)
VSD threshold Normal operation continued
change (L: −15%)

Case 2

Limiter
operating state
(1) (2)
VSD threshold Normal operation continued
change (L: −15%)
Case 3

Limiter
operating state
(1) (2) (3)
VSD threshold Normal operation continued
change (L: −15%)

Case 4

Limiter
operating state
(1) (2) (3) (4)
VSD threshold
change (L: −15%) VSD detected → shut-down

55 2004-11-12
 TB62217AFG
Output-stage Transistor Operation Mode

VM VM VM

RRS

RRS
RRS
RS pin RS pin RS pin
U1 U2 U1 U2 U1 U2

ON OFF OFF OFF OFF ON

Note Note Note

Load
Load Load
L1 L2 L1 L2 L1 L2

OFF ON ON ON ON OFF

PGND PGND PGND

Change mode Slow mode Fast mode

Output-stage Transistor Operation Functions

CLK U1 U2 L1 L2

CHARGE ON OFF OFF ON

SLOW OFF OFF ON ON
FAST OFF ON ON OFF

Note: The above table summarizes how each transistor behaves when the current flows in the indicated direction.
The table below summarizes how each transistor behaves when the current flows in the opposite direction.

CLK U1 U2 L1 L2

CHARGE OFF ON ON OFF

SLOW OFF OFF ON ON
FAST ON OFF OFF ON

56 2004-11-12
 TB62217AFG
PD-Ta (package power dissipation) This item to be revised once package
characteristics are fixed.

Transient thermal resistance of THQFP64 stand-alone and on a PC board

(for reference only)
5
Rth (stand-alone)

Rth (4-layer board)

(for reference only)
4
(W)

3
Power dissipation PD

0
0 25 50 75 100 125 150 175

Temperature (°C)

THQFP64-P-1010-0.50

Note: The board assumed in simulation is Toshiba's ideal board (for reference only).

57 2004-11-12
 TB62217AFG
Operating Time of The Motor Over Current Protection Circuit
(ISD dead band time and ISD operating time)

fosc_M oscillation Output stop (RESET state)

(chopping reference waveform)

Fosc
(OSC_M)

min
Dead band time max

ISD BLANK time ISD operating time

Time when over current starts flowing through the output stage (over current state start)

Reference diagram: Timing chart showing over current flowing through a motor

The over current protection circuit has the dead band time to avoid detecting over current accidentally from
current spikes in switching. The dead band time is in synchronization with the frequency of the OSC for setting
up the chopping frequency (OSC_M).

The time between the instant when over current starts flowing through the output stage and the instant
when the output stops is as follows:

When dead band time = 4 × fosc_M period

Minimum: 4 × fosc_M period

Maximum: 8 × fosc_M period (+ synchronization time + 1 fosc_M time)

However, the operating time stated above applies when the over current flows ideally. The over current circuit
may not work depending on the output control mode and timing.
Therefore, a protection fuse needs to be inserted in the VM power supply.
(The required rating of the fuse varies depending on the conditions under which the IC is used. Therefore,
select a rating that will not cause the maximum power dissipation of the IC to be exceeded and that will not
pose any problem.)

58 2004-11-12
 TB62217AFG
Application Circuit Example

M M

For C_SEL:2.5V
200kohm

from ASIC
from ASIC
3.3V

from ASIC
from ASIC
from ASIC
from ASIC

from ASIC
from ASIC

from ASIC
SBD

M M

59 2004-11-12
 TB62217AFG
Marking

Vendor Name

(TOSHIBA)
TOSHIBA Product Name

217AF TB62~ omitted.

26GA11 Weekly Code

JAPAN
Country of
Manufacture
1PIN Mark

1PIN

Lot traceability correspondence

G
lot code
Weekly
Manufacture year Wafer / Assembly
1 figure traceability code
Production factory

Toshiba Oita factory

60 2004-11-12
 TB62217AFG
Package Dimensions (THQFP64-P-1010-0.50)

Heat sink

Weight: 0.45 g (typ.)

Note: The heat sink provided on the bottom surface of the package is 5.5 mm × 5.5 mm (tentative).

61 2004-11-12