TB6575FNG: PWM Sensorless Controller For 3-Phase Full-Wave BLDC Motors
TB6575FNG: PWM Sensorless Controller For 3-Phase Full-Wave BLDC Motors
                                         TB6575FNG
PWM Sensorless Controller for 3-Phase Full-Wave BLDC Motors
Features
•   3-phase full-wave sensorless drive
•   PWM chopper drive
•   PWM duty cycle control by analog input
•   20-mA current sink capability on PWM output pins
•   Overcurrent protection
                                                                            Weight: 0.14 g (typ.)
•   Forward/reverse rotation
•   Lead angle control (7.5° and 15°)
•   Overlap commutation
•   Rotation speed sensing signal
•   DC excitation mode to improve startup characteristic
•   DC excitation time and forced commutation time for startup operation can be changed.
•   Forced commutation frequency can be selected. (fXT/(6 × 216), fXT/(6 × 217), fXT/(6 × 218) )
•   Output polarity switching (P-channel + N-channel, N-channel + N-channel)
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                                                                                                      TB6575FNG
Block Diagram
                                                                                                        15 OUT_VP
       SC 2
                                                                                      PWM               17 OUT_WP
   START 8                                                                          generator
                   DC excitation
                   control circuit                                                                      14 OUT_UN
       IP 9
                                                                                                        16 OUT_VN
                      Forced
      FST 24        commutation                                      Timing
                 frequency setting                                                                      18 OUT_WN
                                                                     control
                     Maximum
     FMAX 4         commutation
                 frequency setting
                                                                                   Overcurrent
                                                                                                        22 OC
                    Lead angle                                                      protection
       LA 12
                      setting
CW_CCW 6
SEL_LAP 20
                                               Clock                                      Position
                                                                                                        23 WAVE
                                             generation                                 recognition
                                             10          11                    1
                                          XTout          XTin               GND
Pin Assignment
GND 1 24 FST
SC 2 23 WAVE
OS 3 22 OC
FMAX 4 21 VDD
VSP 5 20 SEL_LAP
CW_CCW 6 19 Duty
FG_OUT 7 18 OUT_WN
START 8 17 OUT_WP
IP 9 16 OUT_VN
XTout 10 15 OUT_VP
XTin 11 14 OUT_UN
LA 12 13 OUT_UP
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Pin Description
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Functional Description
  1. Sensorless drive
        On receiving an analog voltage command input, the rotor is aligned to a known position in DC excitation
      mode, and then the rotation is started in forced commutation mode by applying a PWM signal to the motor.
      As the rotor moves, back-EMF is acquired.
        When a signal indicating the polarity of each of the phase voltages including back-EMF is applied to the
      position signal input pin, automatic switching occurs from the forced commutation PWM signal to the
      natural commutation PWM signal (which is generated based on the back-EMF sensing) to drive a BLDC
      motor in sensorless mode.
  2. Startup operation
        When the motor is stationary, there is no back-EMF and the motor position is unknown. For this reason,
      the rotor is aligned to a known position in DC excitation mode and then the rotation is started in forced
      commutation mode. An external capacitor sets the times that the TB6575FNG stays in DC excitation and
      forced commutation modes. Those times vary depending on the motor type and motor loading. Thus, they
      must be adjusted experimentally.
VSP (5 pin)
VSP
                                           VAD (L)
             SC (2 pin)                    TUP                                  TUP (typ.) = C1 × VSP/3.8 µA (s)
   START_SP (8 pin)                              VDD
IP (9 pin)
                                                 VDD
                                                  2
                                       (a) (b)                                       GND
VSP 5
                                                                                                          TB6575FNG
          (a): DC excitation period : TFIX (typ.) = 0.69 × C1 × R1 (s)                               2
          (b): Forced commutation period                                                      C1
                                                                                                              9        8
                                                                                                                  R1
C2
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The rotor is aligned to a known position in DC excitation mode for period (a), during which the IP pin voltage
decreases to half VDD level. The time constant for the period is determined by C2 and R1. After that, switching
occurs to forced commutation mode represented by (b). The duty cycles for DC excitation and forced commutation
modes are determined according to the SC pin voltage. When the number of turn of a motor is time more than
forced commutation frequency, the motor switches to sensorless mode. The duty cycle for sensorless mode is
determined by the VSP value.
   4. PWM frequency
          The PWM frequency is determined by an external oscillator.
             PWM frequency (fPWM) = fXT/256
             * fXT: Crystal oscillator frequency
          The PWM frequency must be sufficiently high, compared with the electrical frequency of the motor and
        within the switching performance of the transistors.
OS = High or Open
              → Duty cycle = 0%
           VAD (L) ≤ VDUTY ≤ VAD (H)
              → Figure at the right (1/64 to 63/64)
           VAD (H) ≤ VDUTY ≤ VDD
              → Duty cycle = 100% (63/64)
                                                                    0%                                            VSP
                                                                          VAD (L)                  VAD (H)
                                                                          1 V (typ.)               4 V (typ.)
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6. Fault protection
     When a signal indicating the following faults is applied to the WAVE pin, the output transistors are
   disabled. After about one second, the motor is restarted. This operation is repeated as long as a fault is
   detected.
        • The maximum commutation frequency is exceeded.
        • The rotation speed falls below the forced commutation frequency.
VSP = 1 V or higher
VSP (Pin5)
(a)
SC (Pin9) VSP
1V
Fault detected
Detection error time < 1/fp fp: PWM frequency = fXT/256 fXT: Crystal oscillator frequency
Output ON
            Pin voltage
                                                                Pin voltage
                           Reference voltage
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8. Lead angle control
       The motor runs with a lead angle of 0° in forced commutation mode at startup. After switching to natural
     commutation, the lead angle automatically changes to the value set by the LA pin.
  Back-EMF                                U                      V                      W
 PWM signal
  (1) Lead angle of 0°      30°
     OUT_UP
     OUT_UN
     OUT_VP
     OUT_VN
     OUT_WP
     OUT_WN
  (2) Lead angle of 7.5°   22.5°
     OUT_UP
     OUT_UN
     OUT_VP
     OUT_VN
     OUT_WP
     OUT_WN
  (3) Lead angle of 15°    15°
     OUT_UP
     OUT_UN
     OUT_VP
     OUT_VN
     OUT_WP
     OUT_WN
*OS = High
9. Overlap commutation
       When SEL_LAP = high, the TB6575FNG is configured to allow for 120° commutation. When SEL_LAP =
     low, it is configured to allow for overlap commutation. In overlap commutation, there is an overlap period
     during which both the outgoing transistor and incoming transistor are conducting (as shown in the shaded
     areas). This period varies according to the lead angle.
  Back-EMF                                U                      V                      W
 PWM signal
  (1) Lead angle of 7.5°
     OUT_UP
     OUT_UN
     OUT_VP
     OUT_VN
     OUT_WP
     OUT_WN
  (2) Lead angle of 15°
     OUT_UP
     OUT_UN
     OUT_VP
     OUT_VN
     OUT_WP
     OUT_WN
*OS = High
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Absolute Maximum Ratings (Ta = 25°C)
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Electrical Characteristics (Ta = 25°C, VDD = 5 V)
                                               Test
          Characteristics         Symbol                            Test Condition      Min    Typ.   Max    Unit
                                              Circuit
  Static power supply current       IDD         ⎯       VSP = 0 V, XTin = H             ⎯      0.7    1      mA
                                                        VSP = 2.5 V, XTin = 4 MHz,
  Dynamic power supply current    IDD (opr)     ⎯                                       ⎯       2      6     mA
                                                        Output open
                                                        VIN = 5 V, OC, WAVE, SEL_LAP
                                  IIN-1 (H)     ⎯                                       ⎯       0      1
                                                        FMAX, FST, OS
                                                        VIN = 0 V, OC, WAVE, SEL_LAP,
  Input current                   IIN-1 (L)     ⎯                                       −75    −50    ⎯      µA
                                                        FMAX, FST, OS
                                  IIN-2 (H)     ⎯       VIN = 5 V, CW_CCW, LA, VSP      ⎯      50     75
                                  IIN-2 (L)     ⎯       VIN = 0 V, CW_CCW, LA, VSP      −1      0     ⎯
                                                        OC, SEL_LAP, CW_CCW
                                  VIN-1 (H)     ⎯                                       3.5    ⎯       5
                                                        WAVE, LA, FMAX, OS
                                                        OC, SEL_LAP, CW_CCW
                                  VIN-1 (L)     ⎯                                       GND    ⎯      1.5
                                                        WAVE, LA, FMAX, OS
  Input voltage                                                                                               V
                                  VIN-2 (H)     ⎯       FST                              4     ⎯       5
                                  VIN-2 (M)     ⎯       FST                              2     ⎯       3
                                  VIN-2 (L)     ⎯       FST                             GND    ⎯       1
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Input Equivalent Circuit
  1. VSP pin                                                      2. SEL_LAP, FMAX, FST, WAVE and OS pins
                                                                                                100 kΩ
                             1 kΩ
      Input pin                         Startup time                 Input pin                                          Internal logic
                          100 kΩ
                                        setting block                                             1 kΩ
                                                                        Hysteresis width
                                                                        WAVE : 450 mV (typ.)
VDD VDD
                             1 kΩ
      Input pin                         Internal logic
                          100 kΩ
                  150 Ω             150 Ω
  XTin pin                                       XTout pin           OC pin                                              Internal logic
                                                                                      200 kΩ
                                                                                                         5 pF
0.5 V
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Application Circuit Example                                                                                   MCU
                                                                                  5V
                                                                         Duty                                                                                                           VM
                                                                          19             21             24      7
                                                                                          VDD            OS      FG_OUT
Speed command
 (analog voltage)    VSP
                                 Startup time        6-bit AD            PWM                                          OUT_UP
                    5                                                                                                       13
                                    setting         converter           control
                                                                                                                      OUT_VP                                                                    M
                     SC                                                                                                     15
                    2                                                                                                 OUT_WP
                     START                                                                                 PWM              17
                    8                                                                                    generator
                                    1-phase excitation                                                                OUT_UN
                     IP                                                                                                     14
                                                                                                                                                                                        100 kΩ × 3
                                      control circuit
  VDD               9
                                                                                                                      OUT_VN
   2                                                                                                                        16
                     FST
                                  Startup commutation                                                                 OUT_WN
                    24                                                                 Timing
                                   frequency setting                                                                        18
                                                                                       setting
                                                                                                                                                                                1Ω
                     FMAX
                                 Maximum commutation
                    4
                                   frequency setting
                                                                                                        Overcurrent       OC
     VDD                                                                                                                    22
                                                                                                                                                                       100 kΩ
                      LA                                                                                 protection
                                                                                                                                                    10 kΩ
                    12             Lead angle setting                                                                              (*1)
                                                                                                                                                                                1 kΩ
                      CW_CCW
                                                                                                                                                                                22 pF
                     6
                                                                                                                                                                       100 kΩ
                     SEL_LAP
                    20
                                                                                                                                                            TA75393P
                                                             Clock                                          Position    WAVE
                                                                                                                            23
                                                           generation                                     recognition
                                                           XTout    XTin                          GND
                                                          10       11                            1
  Note 1: Utmost care is necessary in the design of the output, VCC, VM, and GND lines since the IC may be destroyed by short-circuiting between outputs, air contamination faults,
         or faults due to improper grounding, or by short-circuiting between contiguous pins.
  Note 2: The above application circuit including component values is reference only. Because the values may vary depending on the motor type, the optimal values must be
           determined experimentally.
  *1: Connect a resistor, if necessary, to prevent malfunction due to noise.
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                             TB6575FNG
Package Dimensions
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                                                                                        TB6575FNG
Notes on Contents
1. Block Diagrams
 Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified
 for explanatory purposes.
2. Equivalent Circuits
 The equivalent circuit diagrams may be simplified or some parts of them may be omitted for
 explanatory purposes.
3. Timing Charts
 Timing charts may be simplified for explanatory purposes.
4. Application Circuits
 The application circuits shown in this document are provided for reference purposes only. Thorough
 evaluation is required, especially at the mass production design stage.
 Toshiba does not grant any license to any industrial property rights by providing these examples of
 application circuits.
5. Test Circuits
 Components in the test circuits are used only to obtain and confirm the device characteristics. These
 components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
 application equipment.
IC Usage Considerations
  Notes on handling of ICs
[1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
     exceeded, even for a moment. Do not exceed any of these ratings.
     Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
     injury by explosion or combustion.
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     TB6575FNG
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