Linear Products

DC Brush Motor Control

Using the TPIC2101

In many applications, a key design The sleep state is the power

goal is to minimize variations in conserving state. The run state is SYSTEM BENEFITS
power delivered to a load as the the normal operating state of the
supply voltage varies. This device. Fault state is entered when Constant Load Voltage
application brief describes a the device detects an over voltage
simple DC brush motor control or over current condition. The Over Voltage/Current
circuit using the Texas Instruments device features two input modes Protection
TPIC2101 to maintain a constant (Manual and Auto), soft start,
effective voltage across the motor. over/under voltage protection, and Low Power Consumption
the ability to limit the power During Sleep State
The TPIC2101 is a pulse-width
dissipation of an externally driven
modulated (PWM) power FET Built-In Soft Start
device.
predriver used for speed control of
DC brush motors. It can also be
used for other applications Theory of Operation generates a pulse width drive to an
requiring PWM. The device has Figure 1 illustrates a fan motor external power NMOS transistor
three states: sleep state, run state, circuit used in an automobile which is proportional to the input
and fault state. application. The TPIC2101 signal while also compensating for

Manual Vbat Vbat

Configuration
+
4.7 µF +
1 14 27.4 kΩ 470 µF
V5P5 CCS
MAN AUTO +
DC
499 Ω 2 13 Brush
MAN AREF Output Connected Motor
1 kΩ 12 39 Ω for Drain Sensing
Vbat
0.1 µF 0.1 µF D1
499 Ω 3
MBR1045
Auto
Configuration AUTO + Q1
0.047 µF IRF530 D2
TPIC2101 15 µF 330 Ω 1N4148
11
GD
24 kΩ 4
SPEED 82 Ω
R4
45.3 kΩ 5 0.1 Ω
Rosc 10 1N4148 NI
6 GND
Input Connection Cosc
for Test R1 R3
0.0022 µF 33 kΩ 100 kΩ
9
7 ILS
INT R2 C1
+
4.7 µF 8 11.5 kΩ 200 pF
ILR

0.1 µF

Figure 1. Fan Motor Schematic with PWM Speed Control

Application Brief
supply voltage changes. For a 20 kHz. The output pulse width in INT pin. Both the MAN and AUTO
detailed description of each pin, Auto mode is determined by the pins sink 2 mA in the Manual
refer to the TPIC2101 data sheet. formula, PWMout = (( 2.88 + 13.12 mode. Therefore, simply placing a
(1– input duty cycle)) / Vbat)*100%. resistor between the two pins will
Operation Modes Figures 2 and 2A demonstrate the generate the required input signal.
Auto Mode Auto mode operation. For example, a 1 kΩ potentiometer
To assert the Auto mode, an open can be used to generate the 0 V to
Figure 2 shows the input 2.2 V required for a full range
collector PWM signal is used to
configuration for Auto mode. output. The output pulse width in
pull the AUTO pin low while the
Figure 2A shows the relationship Manual mode is determined by the
MAN (manual) pin is open. The
between PWM in (input PWM at formula, PWMout = (( 2.88 + 6.56)
input PWM frequency required is
the base of the NPN transistor) and ( Vman– Vauto ) / Vbat)* 100%.
approximately 100 Hz. This signal
Veff (effective motor voltage). Figure 3 shows the input
is conditioned by the internal
circuitry and becomes an output at configuration for the Manual mode
the SPEED pin. An external RC Manual Mode of operation. Figure 3A illustrates
integrates this signal, which then To assert Manual mode, the MAN the relationship between the
becomes the input for the INT pin is pulled high, and the voltage differential voltage (Vman – Vauto)
(integrator) pin. At the INT pin a difference between the MAN and and the effective motor voltage.
DC voltage of 0.72 V to 4 V AUTO pins, 0 V to 2.2 V, Note: In both Auto and Manual modes, the
corresponds to an input pulse determines the IC’s output PWM INT pin actually controls the output pulse
width from 100% to 0% as seen at drive signal of approximately 18% width by comparing VCOSC and VINT. When
pin 3, and will generate an output to 100% depending on Vbat. Just VCOSC is greater than VINT the GD output is
PWM drive signal at the GD (gate as in Auto mode, the input signal is turned off. These waveforms are illustrated
drive) pin varying from 18% to conditioned by the internal in Figure 5. The INT pin could be used as an
100% depending on the supply circuitry, output at the SPEED pin, input for some special applications not re-
voltage, (Vbat). The output gate and via an external RC becomes quiring the input signal conditioning
drive frequency is approximately an input of 0.72 V to 4 V DC at the

Open 2, MAN Vbat

Must pulse 1 in 2048 osc Voltage difference between
clocks to stay alive. pin 2 and pin 3 is the input 2, MAN
output pulse width is signal. 0 V to 2.2 V controls
proportional to input % high, output pulse width from
(pin 3 low). 3, AUTO 18% to 100%

1 kΩ 3, AUTO

Figure 2. Auto Mode Input Figure 3. Manual Mode Input

Figure 2A. Auto Mode Effective Voltage Figure 3A. Manual Mode Effective Voltage
by floating the SPEED pin and applying the
input signal directly to the INT pin as shown
in Figure 4.

Vbat MAN

2, MAN
Cosc and
INT overlay
Cint = 680 pF
NC 4, SPEED
0 to 4 Volts
GD
7, INT Gate Out

Figure 4. Aux Mode Method

Sleep State
Figure 5. Soft Start
When the integrated circuit is not in
Run state it is in Sleep state. In this placed between the MAN pin and Fault States
condition the supply current for the the AUTO pin to command a 100% Over Voltage
IC is reduced from a maximum of output pulse width. The INT
10 mA to less than 200 µA. The capacitor was reduced to 680 pF Over voltage is sensed by the Vbat
purpose of Sleep state is to for a start up time of approximately pin internally and is not user
preserve battery life when 350 µs (this short time is used to adjustable. Over voltage occurs
applicable. make the waveform more visible). when Vbat rises between 17 V and
On the top trace, the rising edge 20 V. During over voltage
Soft Start shows when Manual mode is condition, GD will be turned off and
In order to prevent abrupt asserted. the device will enter Fault state.
application of power to the motor, Recovery is automatic when Vbat
The second trace shows the decreases 0.5 V to 1 V below the
the TPIC2101 includes a soft start oscillator which generates the
feature that gradually ramps the over voltage threshold. Hysteresis
output PWM frequency. The third will ensure that the condition does
output signal. When Run state is trace is an overlay of trace two, and
asserted, the output GD is not toggle off and on near the
illustrates the rise time of the INT threshold.
increased in width from 0 to the pin. The bottom trace shows the
commanded percent width over GD pulse width increasing from Over Current (limit)
approximately 1 second. As 0% to 100% as the INT pin voltage
previously discussed, the SPEED If while the GD pin is high, ILS
rises.
pin outputs the conditioned input ( current limit sense ) pin is higher
signal, and the INT pin controls the Under Voltage than ILR ( current limit reference )
IC’s output pulse width. The pin, the internal circuitry will pull
resistor between the SPEED and Under voltage occurs when Vbat the INT pin low, thereby reducing
INT pins has a minimum value of falls below 8 V. Under voltage the commanded output GD pulse
20 kΩ, and the capacitor is conditions will cause the device to width. This is on a pulse by pulse
selected for the start up time enter Sleep state with the gate basis. This limits the power
desired, usually 4.7 µF for drive held low. Recovery is dissipation of the output device in
approximately 1 second to full on. automatic when Vbat increases the short term.
approximately 1 V above the under
Figure 5 demonstrates the soft voltage threshold. Hysteresis Over Current (fault)
start feature for Manual mode. For prevents the device from toggling If the above condition persists
this illustration a 1 kΩ resistor was in and out of Sleep state. during the next 64,000 pulses, the
IC will enter Fault state with the GD
held low for 64,000 pulses. At that
time, one automatic restart will be
attempted. If the Over Current
condition occurs a second 5 mA/div
Iint
consecutive time, the IC will
remain in Fault state until the Load Current
device is cycled through a Sleep within range
ILS, ILR = 1.45 V
state to a Run state. This is
accomplished when the input
2 A/div
command is removed and IDRAIN
reestablished. Note that 64,000
pulses at 20 kHz is approximately GD
Vbat = 12 V
three seconds. The actual time will
be proportional to the PWM
frequency in use. For a more Figure 6. Normal Run State
detailed description of the internal
circuit refer to the TPIC2101 data
sheet.
Figures 6 – 8 illustrate the device’s
response to overload conditions
using a drain sense configuration.
Refer to Figure 1 for the detailed
schematic. Figure 6 demonstrates
normal operation without overload.
The top trace shows the current in
the lead to the INT capacitor. The
second trace shows the voltage at
the ILS pin. The voltage at the ILS
pin rises from zero at the beginning
of each pulse at a rate determined
by R3 and C1 until it reaches one
diode drop above the drain voltage Figure 7. Run State at Threshold
of the external transistor. This is
compared by the internal circuitry
to the voltage set at the ILR pin.
This reference voltage is set by the
voltage divider R1/R2 from VAREF.
The third trace shows the drain 5 mA/div
current of the external transistor
well under the threshold setting Load Current gets
threshold just after
determined by the reference
ILS rises to value
voltage. The bottom trace shows ILS, ILR = 1.45 V
the GD voltage.
2 A/div
In Figure 7, the load has been IDRAIN
increased to the threshold setting. GD
The top trace shows that the Vbat = 12 V
internal circuit is pulling current out
of the INT capacitor which lowers
the demand voltage at the INT pin. Figure 8. Run State Over Threshold
The second trace is reaching the overall schematic Figure 1, the GD VFD1 = 0.7 V (Diode forward
threshold set by the ILR pin. The pin goes high turning the external voltage) Using these component
third trace shows the drain current transistor full on for a time equal to values, VILS = 1.42 V. Also, if the
at the higher level, and the bottom the commanded pulse width. bias at the ILR pin is set by divider
trace reflects the narrower drive During that time current flows R1, R2 from AREF to a value of
signal, as compared to Figure 6. through the motor and transistor. 1.45 V, overload will trip at 1.45 V
When GD goes low, the transistor +/– 10 mV.
Figure 8 illustrates the effect of an
turns off, but the current in the
additional load increase. As the The advantage of drain sensing is
motor continues to flow by way of
load continues to increase, the that the output device is power
pulse width is substantially re- the recirculation diode, D1, using
dissipation limited. As power
duced. If the load continues to in- the energy stored in the motor
dissipation increases, the
crease until the pulse width is less inductance.
temperature of the external FET
than the rise time of the sensing also increases. This rise in
voltage at the ILS pin (determined When GD is low, the ILS pin is held
temperature results in a higher
by R3 and C1), overload detect is low internally. When GD goes
RDS(on). Therefore,sinceVDRAIN =
no longer functioning, and a mini- high, capacitor C1 starts charging
IDRAIN *RDS(on), VDRAIN, which is
mum pulse width has been through R3 from AREF, and the
being sensed, responds to that
reached. Therefore, the compo- voltage at ILS rises until it is
increase. The disadvantage of this
nents should be selected to obtain clamped by forward biasing diode
method is that the characteristics
the minimum width required for D2 to the drain of the external
of the external transistor, such as
starting the motor, within the transistor Q1. Therefore, during
VSAT drain-to-source, must be
64,000 pulses (approximately 3 the on time, the voltage at the ILS
considered when selecting the
seconds), or a fault will be sensed. pin becomes, VILS = ID* ( R5 +
FET.
On the other hand, the pulse can- RDS(on) ) + VFD1,
not be so wide that it allows the ex- ID = drain current = 3.6 A (at
ternal transistor to exceed its pow-
Conclusions
desired trip point)
er rating. R4 = 0.1 Ω (This non-inductive The TPIC2101 provides a cost
resistor is used for monitoring the effective means of maintaing a
Run State current. It is not required for this constant effective voltage in DC
Although other output methods connection, but must be motor applications.
can be used, this brief summarizes considered if there)
Run state using the drain voltage RDS(on) = 0.1 Ω (On resistance at
sensing method. Referring to the 3.6 A from IRF530 data sheet)
SLIT110
 IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current and complete.

TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED

TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.

Copyright  1998, Texas Instruments Incorporated