ICM7217

4-Digit LED Display,

August 1997 Programmable Up/Down Counter

Features Description
• Four Decade, Presettable Up-Down Counter with The ICM7217 is a four digit, presettable up/down counter with
Parallel Zero Detect an onboard presettable register continuously compared to the
counter. The ICM7217 is intended for use in hard-wired
• Settable Register with Contents Continuously applications where thumbwheel switches are used for loading
Compared to Counter data, and simple SPDT switches are used for chip control.
• Directly Drives Multiplexed 7 Segment Common This circuit provides multiplexed 7 segment LED display
Anode or Common Cathode LED Displays outputs, with common anode or common cathode
• On-Board Multiplex Scan Oscillator configurations available. Digit and segment drivers are
provided to directly drive displays of up to 0.8 inch
• Schmitt Trigger On Count Input character height (common anode) at a 25% duty cycle. The
frequency of the onboard multiplex oscillator may be
• TTL Compatible BCD I/O Port, Carry/Borrow, Equal, controlled with a single capacitor, or the oscillator may be
and Zero Outputs allowed to free run. Leading zeros can be blanked. The
• Display Blank Control for Lower Power Operation; data appearing at the 7 segment and BCD outputs is
Quiescent Power Dissipation <5mW latched; the content of the counter is transferred into the
latches under external control by means of the Store pin.
• All Terminals Fully Protected Against Static Discharge
The ICM7217 (common anode) and ICM7217A (common
• Single 5V Supply Operation cathode) versions are decade counters, providing a
maximum count of 9999, while the ICM7217B (common
anode) and ICM7217C (common cathode) are intended for
timing purposes, providing a maximum count of 5959.
This circuit provides 3 main outputs; a CARRY/BORROW
output, which allows for direct cascading of counters, a
ZERO output, which indicates when the count is zero, and
an EQUAL output, which indicates when the count is equal
to the value contained in the register. Data is multiplexed to
and from the device by means of a three-state BCD I/O port.
The CARRY/BORROW, EQUAL, ZERO outputs, and the
BCD port will each drive one standard TTL load.
To permit operation in noisy environments and to prevent
multiple triggering with slowly changing inputs, the count
input is provided with a Schmitt trigger.
Input frequency is guaranteed to 2MHz, although the device will
typically run with fIN as high as 5MHz. Counting and comparing
(EQUAL output) will typically run 750kHz maximum.

Ordering Information
PART TEMP. RANGE DISPLAY DRIVER COUNT OPTION/
NUMBER (oC) PACKAGE TYPE MAX COUNT PKG. NO.

ICM7217AIPI -25 to 85 28 Ld PDIP Common Cathode Decade/9999 E28.6

ICM7217CIPl -25 to 85 28 Ld PDIP Common Cathode Timing/5959 E28.6

ICM7217IJI -25 to 85 28 Ld CERDIP Common Anode Decade/9999 F28.6

lCM7217BlJl -25 to 85 28 Ld CERDIP Common Anode Timing/5959 F28.6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3167.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
9-12
 ICM7217

Pinouts
ICM7217 (PDIP) ICM7217 (CERDIP)
COMMON ANODE COMMON CATHODE
TOP VIEW TOP VIEW

CARRY/BORROW 1 28 D1 CARRY/BORROW 1 28 SEG d

ZERO 2 27 D2 ZERO 2 27 SEG b
EQUAL 3 26 D3 EQUAL 3 26 SEG f
BCD I/O 8s 4 25 D4 BCD I/O 8s 4 25 SEG c
BCD I/O 4s 5 24 VDD BCD I/O 4s 5 24 VDD
BCD I/O 2s 6 23 DISPLAY CONT. BCD I/O 2s 6 23 SEG a
BCD I/O 1s 7 ICM7217 22 SEG g BCD I/O 1s 7 ICM7217A 22 SEG e
COUNT INPUT 8 ICM7217B 21 SEG b COUNT INPUT 8 ICM7217C 21 SEG g
STORE 9 20 VSS STORE 9 20 DISPLAY CONT.
UP/DOWN 10 19 SEG e UP/DOWN 10 19 VSS
LOAD REGISTER/OFF 11 18 SEG f LOAD REGISTER/OFF 11 18 D1
LOAD COUNTER/I/O OFF 12 17 SEG d LOAD COUNTER/I/O OFF 12 17 D2
SCAN 13 16 SEG a SCAN 13 16 D3
RESET 14 15 SEG c RESET 14 15 D4

Functional Block Diagram

4 4 4 4 4 4 4 4
ZERO
T.G. T.G. T.G. T.G. T.G. T.G. T.G. T.G.
1 2 3 4 4 3 2 1
4 4 4 4 4 4 4 4

D1 D2 D3 D4
10 1 10 2 10 3 10 4 4 D1 3 D2 2 D3 1 D4
VDD RS RS RS RS REG. REG. REG. REG.
4
ZERO ZERO ZERO ZERO
4 4 4 4
UP/DN U/D U/D U/D U/D

COUNT CL CARRY CL CARRY CL CARRY CL CARRY COMP. COMP. COMP. COMP.

4 4 4 4
VSS

CARRY/BARROW EQUAL

VDD
T.G. T.G. T.G. T.G. STORE
8s
4 4 4 4 L.R. VDD
4s
BDC RESET
2s I/O
LATCH LATCH LATCH LATCH
1s VDD
MUX MUX MUX MUX L.C. LOAD
MUX. I/O VSS COUNTER
4 4 4 4 RESET AND
DISPLAY VDD
CONTROL LOAD
VSS REGISTER
LOGIC
VDD
DISPLAY BLANK + OFF VSS DISPLAY
SEGMENT DECODER CONTROL

4 4
DIGIT MUX
SEGMENT DRIVERS DIGIT DRIVERS
MUX.
(7) (4) SCAN
BCD I/O INPUTS OSCILLATOR
COM. ANODE: PULL DOWN
COM. CATHODE: PULL UP
A B C D E F G D4 D3 D2 D1

9-13
 ICM7217

Absolute Maximum Ratings Thermal Information

Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)
Input Voltage (Any Terminal) . . . . . . . .(VSS - 0.3V) to (VDD + 0.3V) CERDIP Package . . . . . . . . . . . . . . . . 55 14
(Note 1) PDIP Package . . . . . . . . . . . . . . . . . . . 55 N/A
Maximum Junction Temperature
Operating Conditions PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater
than VDD or less than VSS may cause destructive device latchup. For this reason it is recommended that the power supply to the device
be established before any inputs are applied and that in multiple systems the supply to the ICM7217 be turned on first.
2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications VDD = 5V, VSS = 0V, TA = 25oC, Display Diode Drop 1 .7V, Unless Otherwise Specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Current Display Off, LC, DC, UP/DN, - 350 500 µA
(Lowest Power Mode), IDD (7217) ST, RS, BCD I/O Floating or at VDD (Note 1)
Supply Current, OPERATING, IOP Common Anode, Display On, all “8’s” 140 200 - mA
Supply Current, OPERATING, IOP Common Cathode, Display On, all “8’s” 50 100 - mA
VSUPPLY , VDD 4.5 5 5.5 V
Digit Driver Output Current, IDIG Common Anode, VOUT = VDD - 2.0V 140 200 - mAPEAK
SEGment Driver Common Anode, VOUT = +1.5V 20 35 - mAPEAK
Output Current, ISEG
Digit Driver, Output Current, IDIG Common Cathode, VOUT = +1.0V -50 -75 - mAPEAK
SEGment Driver Common Cathode VOUT = VDD - 2V -9 -12.5 - mAPEAK
Output Current, ISEG
ST, RS, UP/DN Input VIN = VDD - 2V (Note 1) 5 25 - µA
Pullup Current, IP
3 Level Input Impendance, ZIN 40 - 350 kΩ
BCD I/O Input, High Voltage ICM7217 Common Anode (Note 2) 1.5 - - V
VBIH
ICM7217 Common Cathode (Note 2) 4.40 - - V
BCD I/O Input, Low Voltage ICM7217 Common Anode (Note 2) - - 0.60 V
VBIL
ICM7217 Common Cathode (Note 2) - - 3.2V V
BCD I/O Input, Pullup Current ICM7217 Common Cathode VIN = VDD - 2V 5 25 - µA
IBPU (Note 2)
BCD I/O Input ICM7217 Common Anode VIN = +2V (Note 2) 5 25 - µA
Pulldown Current, IBPD
BCD I/O, ZERO, EQUAL Outputs IOH = -100µA 3.5 - - V
Output High Voltage, VOH
BCD I/O, CARRY/BORROW IOL = 1.6mA - - 0.4 V
ZERO, EQUAL Outputs
Output Low Voltage, VOL
Count Input Frequency, fIN -20oC to 70oC - 5 - MHz
Guaranteed 0 - 2 MHz
Count Input Threshold, VTH (Note 3) - 2 - V
Count Input Hysteresis, VHYS (Note 3) - 0.5 - V
Count Input LO, VCIL - - 0.40 V
Count Input HI, VCIH 3.5 - - V
Display Scan Free-running (SCAN Terminal Open Circuit) - 2.5 10 kHz
Oscillator Frequency, fDS

9-14
 ICM7217

Switching Specifications VDD = 5V, VSS = 0V, TA = 25oC

PARAMETER MIN TYP MAX UNIT

UP/DOWN Setup Time, tUCS 300 - - ns

UP/DOWN Hold Time, tUCH 1500 750 - ns

COUNT Pulse Width High, tCWH 250 100 - ns

COUNT Pulse Width Low, tCWI 250 100 - ns

COUNT to CARRY/BORROW Delay, tCB - 750 - ns

CARRY/BORROW Pulse Width tBW - 100 - ns

COUNT to EQUAL Delay, tCE - 500 - ns

COUNT to ZERO Delay, tCZ - 300 - ns

RESET Pulse Width, tRST 1000 500 - ns

NOTES:
1. In the ICM7217 the UP/DOWN, STORE, RESET and the BCD I/O as inputs have pullup or pulldown devices which consume power when
connected to the opposite supply. Under these conditions, with the display off, the device will consume typically 750µA.
2. These voltages are adjusted to allow the use of thumbwheel switches for the ICM7217. Note that a high level is taken as an input logic
zero for ICM7217 common-cathode versions.
3. Parameters not tested (Guaranteed by Design).

Timing Waveforms

SCAN

10µs TYP 400µs TYP

FREE-RUNNING FREE-RUNNING
INTERNAL OSC
OUTPUT

D4

D3
INTERNAL
(BCD AND
SEGMENT
D2
ENABLE)
D1

D4

INTERNAL
D3
(COMMON
ANODE
DIGIT INTERDIGIT BLANK
D2
STROBES)
D1

FIGURE 1. MULTIPLEX TIMING

9-15
 ICM7217

Timing Waveforms
tUCS tUCH

UP/DOWN

tCWH tCWL

COUNT INPUT

tCB tBW

CARRY/BORROW

tCEL tCEH

EQUAL

tCZL tCZH

ZERO

FIGURE 2. COUNT AND OUTPUTS TIMING

LOAD COUNTER
(OR LOAD REGISTER)

SCAN

D4

D3

D2

D1
INTERNAL INPUT COUNT INHIBITED IF
OPERATING OUTPUT LOAD COUNTER
MODE

BCD I/O D4 D3 D2 D1
DN OUT IN IN IN IN D4 OUT D3 OUT

= HIGH IMPEDANCE
= THREE-STATE W/PULLDOWN

FIGURE 3. BCD I/O AND LOADING TIMING

9-16
 ICM7217

Typical Performance Curves

300 80
4.5 ≤ VDD ≤ 6V TA = 25oC

V+ = 5.5V
ICM7217 60 ICM7217
ICM7217B ICM7217B
200
IDIG (mA)

ISEG (mA)
40
V+ = 4.5V

100
V+ = 5V
25oC
20
85oC
-20oC

0 0
0 1 2 3 0 1 2 3
VDD - VOUT (V) VOUT (V)

FIGURE 4. TYPICAL IDIG vs V+ FIGURE 5. TYPICAL ISEG vs VOUT

80 200
V+ = 5V V+ = 5V

-20oC
-20oC
60 ICM7217 150 ICM7217A
ICM7217B ICM7217C
IDIGIT (mA)
ISEG (mA)

40 100
25oC
25oC

20 50
85oC 85oC

0
0
0 1 2 3 0 1 2 3
VOUT (V) VOUT (V)

FIGURE 6. TYPICAL ISEG vs VOUT FIGURE 7. TYPICAL IDIGIT vs VOUT

200 30
-20oC
TA = 25oC 4.5 ≤ VDD − VSS ≤ 6V

V+ = 5.5V 25oC
150
20 ICM7217A
ICM7217A ICM7217C
ISEG (mA)

ICM7217C
IDIGIT (mA)

100 V+ = 4.5V
85oC

V+ = 5V 10

50

0 0
0 1 2 3 0 1 2 3
VOUT (V) VDD - VOUT (V)

FIGURE 8. TYPICAL IDIGIT vs VOUT FIGURE 9. TYPICAL ISEG vs VDD - VOUT

9-17
 ICM7217

Detailed Description
Control Outputs Display Outputs and Control
The CARRY/BORROW output is a positive going pulse The Digit and SEGment drivers provide a decoded
occurring typically 500ns after the positive going edge of the 7-segment display system, capable of directly driving com-
COUNT INPUT. It occurs when the counter is clocked from mon anode LED displays at typical peak currents of
9999 to 0000 when counting up and from 0000 to 9999 when 35mA/seg. This corresponds to average currents of
counting down. This output allows direct cascading of 8mA/seg at 25% multiplex duty cycle. For the common cath-
counters. The CARRY/BORROW output is not valid during ode versions, peak segment currents are 12.5mA, corre-
load counter and reset operation. When the count is 6000 or sponding to average segment currents of 3.1mA. Figure 1
higher, a reset generates a CARRY/BORROW pulse. shows the multiplex timing. The DISPLAY pin controls the
display output using three level logic. The pin is self-biased
The EQUAL output assumes a negative level when the
to a voltage approximately 1/2 (VDD); this corresponds to
contents of the counter and register are equal.
normal operation. When this pin is connected to VDD , the
The ZERO output assumes a negative level when the segments are disabled and when connected to VSS , the
content of the counter is 0000. leading zero blanking feature is inhibited. For normal opera-
tion (display on with leading zero blanking) the pin should be
The CARRY/BORROW, EQUAL and ZERO outputs will drive left open. The display may be controlled with a 3 position
a single TTL load over the full range of supply voltage and SPDT switch; see Test Circuit.
ambient temperature; for a logic zero, these outputs will sink
1.6mA at 0.4V and for a logic one, the outputs will source Multiplex SCAN Oscillator
>60µA. A 10kΩ pull-up resistor to VDD on the EQUAL or
The on-board multiplex scan oscillator has a nominal free-
ZERO outputs is recommended for highest speed operation,
running frequency of 2.5kHz. This may be reduced by the
and on the CARRY/BORROW output when it is being used
addition of a single capacitor between the SCAN pin and the
for cascading. Figure 2 shows control outputs timing
positive supply. Capacitor values and corresponding nominal
diagram.
oscillator frequencies, digit repetition rates, and loading
times are shown in Table 1.

SCAN INPUT SCAN INPUT

ICM7217 ICM7217
R1 R2
10kΩ 20kΩ
500Ω

C 500Ω
1MΩ 0.01µF

1MΩ 0.01µF

FIGURE 10A. FIGURE 10B.

VDD = 5V

10kΩ 7 8 4 3kΩ

ICM7555
3
SCAN INPUT
200Ω
ICM7217
2
6 1 8s

0.05µF 0.05µF
0V

FIGURE 10C.
FIGURE 10. BRIGHTNESS CONTROL CIRCUITS

9-18
 ICM7217

TABLE 1. ICM7217 MULTIPLEXED RATE CONTROL depending on inputs to the LOAD COUNTER or LOAD
REGISTER pins; (see below). When functioning as outputs,
SCAN the BCD I/O pins will drive one standard TTL load. Common
NOMINAL DIGIT CYCLE anode versions have internal pull down resistors and com-
SCAN OSCILLATOR REPETITION TIME
mon cathode versions have internal pull up resistors on the
CAPACITOR FREQUENCY RATE (4 DIGITS)
four BCD I/O lines when used as inputs.
None 2.5kHz 625Hz 1.6ms
20pF 1.25kHz 300Hz 3.2ms
LOADing the COUNTER and REGISTER
90pF 600Hz 150Hz 8ms The BCD I/O pins, the LOAD COUNTER (LC), and LOAD
REGISTER (LR) pins combine to provide presetting and
The internal oscillator output has a duty cycle of compare functions. LC and LR are 3-level inputs, being self-
approximately 25:1, providing a short pulse occurring at the biased at approximately 1/2VDD for normal operation. With
oscillator frequency. This pulse clocks the four-state counter both LC and LR open, the BCD I/O pins provide a multi-
which provides the four multiplex phases. The short pulse plexed BCD output of the latch contents, scanned from MSD
width is used to delay the digit driver outputs, thereby provid- to LSD by the display multiplex.
ing inter-digit blanking which prevents ghosting. The digits
are scanned from MSD (D4) to LSD (D1). See Figure 1 for When either the LOAD COUNTER (Pin 12) or LOAD
the display digit multiplex timing. REGISTER (Pin 11) is taken low, the drivers are turned off
and the BCD pins become high-impedance inputs. When LC
During load counter and load register operations, the is connected to VDD , the count input is inhibited and the lev-
multiplex oscillator is disconnected from the SCAN input and els at the BCD pins are multiplexed into the counter. When
is allowed to free-run. In all other conditions, the oscillator LR is connected to VDD , the levels at the BCD pins are mul-
may be directly overdriven to about 20kHz, however the tiplexed into the register without disturbing the counter.
external oscillator signal should have the same duty cycle as When both are connected to VDD , the count is inhibited and
the internal signal, since the digits are blanked during the both register and counter will be loaded.
time the external signal is at a positive level (see Figure 1).
To insure proper leading zero blanking, the interdigit blank- The LOAD COUNTER and LOAD REGISTER inputs are
ing time should not be less than about 2µs. Overdriving the edge-triggered, and pulsing them high for 500ns at room
oscillator at less than 200Hz may cause display flickering. temperature will initiate a full sequence of data entry cycle
operations (see Figure 3). When the circuit recognizes that
The display brightness may be altered by varying the duty either or both of the LC or LR pins input is high, the multiplex
cycle. Figure 10 shows several variable-duty-cycle oscilla- oscillator and counter are reset (to D4). The internal
tors suitable for brightness control at the ICM7217 SCAN oscillator is then disconnected from the SCAN pin and the
input. The inverters should be CMOS CD4000 series and preset circuitry is enabled. The oscillator starts and runs with
the diodes may be any inexpensive device such as lN914. a frequency determined by its internal capacitor, (which may
Counting Control, STORE, RESET vary from chip to chip). When the chip finishes a full 4-digit
multiplex cycle (loading each digit from D4 to D3 to D2 to D1
As shown in Figure 2, the counter is incremented by the in turn), it again samples the LOAD REGISTER and LOAD
rising edge of the COUNT INPUT signal when UP/DOWN is COUNTER inputs. If either or both is still high, it repeats the
high. It is decremented when UP/DOWN is low. A Schmitt load cycle, if both are floating or low, the oscillator is
trigger on the COUNT INPUT provides hysteresis to prevent reconnected to the SCAN pin and the chip returns to normal
double triggering on slow rising edges and permits operation operation. Total load time is digit “on” time multiplied by 4. lf
in noisy environments. The COUNT INPUT is inhibited dur- the Digit outputs are used to strobe the BCD data into the
ing reset and load counter operations. BCD I/O inputs, the input must be synchronized to the
The STORE pin controls the internal latches and appropriate digit (Figure 3). Input data must be valid at the
consequently the signals appearing at the 7-Segment and trailing edge of the digit output.
BCD outputs. Bringing the STORE pin low transfers the con- When LR is connected to GROUND, the oscillator is
tents of the counter into the latches. inhibited, the BCD I/O pins go to the high impedance state,
The counter is asynchronously reset to 0000 by bringing the and the segment and digit drivers are turned off. This allows
RESET pin low. The circuit performs the reset operation by the display to be used for other purposes and minimizes
forcing the BCD input lines to zero, and “presetting” all four power consumption. In this display off condition, the circuit
decades of counter in parallel. This affects register loading; if will continue to count, and the CARRY/BORROW, EQUAL,
LOAD REGISTER is activated when the RESET input is low, ZERO, UP/DOWN, RESET and STORE functions operate
the register will also be set to zero. The STORE, RESET and as normal. When LC is connected to ground, the BCD I/O
UP/DOWN pins are provided with pullup resistors of approxi- pins are forced to the high impedance state without disturb-
mately 75kΩ. ing the counter or register. See “Control Input Definitions”
(Table 2) for a list of the pins that function as three-state self-
BCD I/O Pins biased inputs and their respective operations.
The BCD I/O port provides a means of transferring data to Note that the ICM7217 and ICM7217B have been designed
and from the device. The ICM7217 versions can multiplex to drive common anode displays. The BCD inputs are high
data into the counter or register via thumbwheel switches, true, as are the BCD outputs.

9-19
 ICM7217

CD4069 1N4148 CD4069 1N4148

INPUT OUTPUT INPUT OUTPUT

INPUT OUTPUT INPUT OUTPUT

High High High Disconnected
Low Disconnected Low High
FIGURE 11A. CMOS INVERTER FIGURE 11B. CMOS INVERTER

CD4502B
CD74HC03
INPUT A INPUT A OUTPUT
OUTPUT

INPUT B
INPUT B

INPUT B INPUT A OUTPUT INPUT B INPUT A OUTPUT

High High Low High High Disconnected
High Low Disconnected High Low Disconnected
Low High Disconnected Low High High
Low Low Disconnected Low Low Low
FIGURE 11C. CMOS OPEN DRAIN FIGURE 11D. CMOS THREE-STATE BUFFER

FIGURE 11. DRIVING 3-LEVEL INPUTS OF ICM7217

VDD
50kΩ
DN DIGIT LINE DISPLAY
CONTROL
DISPLAY 50kΩ
CONTROL ICM7217A
50kΩ VDD ICM7217C
DN DIGIT LINE
ICM7217
ICM7217B

FIGURE 12A. COMMON ANODE FIGURE 12B. COMMON CATHODE

FIGURE 12. FORCING LEADING ZERO DISPLAY

VDD VDD

DIGIT SEGMENT
DRIVE 2N2219 DRIVE 2N2219
OR SIMILAR OR SIMILAR

ICM7217 ICM7217
ICM7217B VSS ICM7217C VSS
VDD VDD

SEGMENT DIGIT
DRIVE 2N6034 DRIVE
2N6034
OR SIMILAR OR SIMILAR

VSS VSS

FIGURE 13A. COMMON ANODE DISPLAY FIGURE 13B. COMMON CATHODE DISPLAY

FIGURE 13. DRIVING HIGH CURRENT DISPLAYS

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 ICM7217

VDD = 5V VDD = 5V

35
34
D4
LCD DISPLAY 33
D3
37 - 40 32
D2
ICM7211 31
D1
2 - 26 30 4 24
DB3 8s VDD
29 5
DB2 4s
28 SEGMENTS 28 6 23
AND BACKPLANE DB1 2s DC
27 7 20
DB0 1s

8 D1 28
COUNT
9 D2 27
STORE
ICM7217
10 D3 26
UP/DN IJI
14 D4 25
RESET

2 4 2 4 2 4 2 4
1 8 1 8 1 8 1 8

C C C C

10kΩ - 20kΩ

FIGURE 14. LCD DISPLAY INTERFACE (WITH THUMBWHEEL SWITCHES)

The lCM7217A and the ICM7217C are used to drive com- cause erroneous glitches on the EQUAL and ZERO outputs
mon cathode displays, and the BCD inputs are low true. when codes cross.
BCD outputs are high true.
LOAD COUNTER or LOAD REGISTER, and RESET input
Notes on Thumbwheel Switches and Multiplexing can not be activated at the same time or within a short
period of each other. Operation of each input must be
As it was mentioned, the ICM7217 is basically designed to
delayed 1.6ms typical (5ms for guaranteed proper operation)
be used with thumbwheel switches for loading the data to
relating to the preceding one.
the device. See Figure 14 and Figure 17.
Counter and register can be loaded together with the same
The thumbwheel switches used with these circuits (both
value if LC and LR inputs become activated exactly at the
common anode and common cathode) are TRUE BCD
same time.
coded; i.e. all switches open corresponds to 0000. Since the
thumbwheel switches are connected in parallel, diodes must Notice the setup and hold time of UP/DOWN input when it is
be provided to prevent crosstalk between digits. In order to changing during counting operation. Violation of UP/ DOWN
maintain reasonable noise margins, these diodes should be hold time will result in incrementing or decrementing the
specified with low forward voltage drops (IN914). Similarly, if counter by 1000, 100 or 10 where the preceding digit is
the BCD outputs are to be used, resistors should be inserted transitioning from 5 to 6 or 6 to 5.
in the Digit lines to avoid loading problems.
The RESET input may be susceptible to noise if its input rise
Output and Input Restrictions time is greater than about 500µs This will present no prob-
lems when this input is driven by active devices (i.e., TTL or
LOAD COUNTER and LOAD REGISTER operations take
CMOS logic) but in hardwired systems adding virtually any
1.6ms typical (5ms maximum) after LC or LR are released.
capacitance to the RESET input can cause trouble. A simple
During this load period the EQUAL and ZERO outputs are
circuit which provides a reliable power-up reset and a fast
not valid (see Figure 3). Since the Counter and register are
rise time on the RESET input is shown on Figure 15.
compared by XOR gates, loading the counter or register can

9-21
 ICM7217

When using the circuit as a programmable divider (÷ by n

VDD
with equal outputs) a short time delay (about 1µs) is needed 0.047µF
from the EQUAL output to the RESET input to establish a N.O.
10Ω
pulse of adequate duration. (See Figure 16).
RESET INPUT
When the circuit is configured to reload the counter or regis-
ICM7217
ter with a new value from the BCD lines (upon reaching
10kΩ 5kΩ
EQUAL), loading time will be digit “on” time multiplied by
four. If this load time is longer than one period of the input VSS
count, a count can be lost. Since the circuit will retain data in
the register, the register need only be updated when a new FIGURE 15. POWER ON RESET
value is to be entered. RESET will not clear the register.

VDD

47pF
33K
EQUAL RESET

FIGURE 16. EQUAL TO RESET DELAY

Test Circuit
c
a a a a a
COMMON ANODE DISPLAY f b f b f b f b d
g g g g f
e c e c e c e c e
d d d d b

D4 D3 D2
g
D1

THUMBWHEEL SWITCHES
CARRY 1 28
ZERO 2 27

D4 D3 D2 D1 EQUAL 3 26
BCD I/O 8s 4 25
DISPLAY

9999
BCD I/O 4s 5 24
CONTROL
BCD I/O 2s 6 23
BCD I/O 1s 7 ICM7217 22
COUNT INPUT 8 ICM7217B 21
STORE
9 20
UP/DOWN
10 19
LOAD REGISTER
11 18
LOAD COUNTER
12 17
SCAN
13 16
RESET
14 15
VDD N.O.
VDD

+5V

VSS

9-22
 ICM7217

Applications a “fine” control. CD40106Bs are used as a monostable

multivibrator and reset time delay.
3-Level Inputs
Tape Recorder Position Indicator/controller
ICM7217 has three inputs with 3-level logic states; High, Low
and Disconnected. These inputs are: LOAD REGISTER/OFF, The circuit in Figure 20 shows an application which uses the
LOAD COUNTER/I/O OFF and DISPLAY CONT. up/down counting feature of the ICM7217 to keep track of
tape position. This circuit is representative of the many
The circuits illustrated on Figure 11 can be used to drive applications of up/down counting in monitoring dimensional
these inputs in different applications. position.
Fixed Decimal Point In the tape recorder application, the LOAD REGISTER,
In the common anode versions, a fixed decimal point may be EQUAL and ZERO outputs are used to control the recorder.
activated by connecting the DP segment lead from the appro- To make the recorder stop at a particular point on the tape,
priate digit (with separate digit displays) through a 39Ω series the register can be set with the stop point and the EQUAL
resistor to Ground. With common cathode devices, the DP output used to stop the recorder either on fast forward, play
segment lead should be connected through a 75Ω series or rewind.
resistor to VDD .
To make the recorder stop before the tape comes free of the
To force the device to display leading zeroes after a fixed reel on rewind, a leader should be used. Resetting the
decimal point, use a bipolar transistor and base resistor in a counter at the starting point of the tape, a few feet from the
configuration like that shown in Figure 12 with the resistor end of the leader, allows the ZERO output to be used to stop
connected to the digit output driving the DP for left hand DP the recorder on rewind, leaving the leader on the reel.
displays, and to the next least significant digit output for right
hand DP display. The 1MΩ resistor and 0.0047µF capacitor on the COUNT
INPUT provide a time constant of about 5ms to debounce
Driving Larger Displays the reel switch. The Schmitt trigger on the COUNT INPUT of
For displays requiring more current than the ICM7217 can the ICM7217 squares up the signal before applying it to the
provide, the circuits of Figure 13 can be used. counter. This technique may be used to debounce
switch-closure inputs in other applications.
LCD Display Interface
Precision Elapsed Time/Countdown Timer
The low-power operation of the ICM7217 makes an LCD
interface desirable. The Intersil ICM7211 4-digit, BCD-to-LCD The circuit in Figure 21 uses an ICM7213 precision one
display driver easily interfaces to the ICM7217 as shown in minute/one second timebase generator using a 4.1943MHz
Figure 14. Total system power consumption is less than 5mW. crystal for generating pulses counted by an ICM7217B. The
System timing margins can be improved by using capacitance thumbwheel switches allow a starting time to be entered into
to ground to slow down the BCD lines. the counter for a preset-countdown type timer, and allow the
register to be set for compare functions. For instance, to
The 10kΩ - 20kΩ resistors on the switch BCD lines serve to make a 24-hour clock with BCD output the register can be
isolate the switches during BCD output. preset with 2400 and the EQUAL output used to reset the
counter. Note the 10K resistor connected between the LOAD
Unit Counter with BCD Output
COUNTER terminal and Ground. This resistor pulls the
The simplest application of the ICM7217 is a 4-digit unit LOAD COUNTER input low when not loading, thereby
counter (Figure 18). All that is required is an ICM7217, a inhibiting the BCD output drivers. This resistor should be
power supply and a 4 digit display. Add a momentary switch eliminated and SW4 replaced with an SPDT center-off
for reset, an SPDT center-off switch to blank the display or switch if the BCD outputs are to be used.
view leading zeroes, and one more SPDT switch for up/
down control. Using an ICM7217A with a common-cathode This technique may be used on any 3-level input. The 100kΩ
calculator-type display results in the least expensive digital pullup resistor on the count input is used to ensure proper
counter/display system available. logic voltage swing from the ICM7213. For a less expensive
(and less accurate) timebase, an ICM7555 timer may be
Inexpensive Frequency Counter/ Tachometer used in a configuration like that shown in Figure 19 to
This circuit uses the low power ICM7555 (CMOS 555) to generate a 1Hz reference.
generate the gating, STORE and RESET signals as shown 8-Digit Up/Down Counter
in Figure 19. To provide the gating signal, the timer is con-
This circuit (Figure 22) shows how to cascade counters and
figured as an a stable multivibrator, using RA, RB and C to
retain correct leading zero blanking. The NAND gate detects
provide an output that is positive for approximately one sec-
whether a digit is active since one of the two segments a or b
ond and negative for approximately 300µs - 500µs. The pos-
itive waveform time is given by tWP = 0.693 (RA + RB)C is active on any unblanked number. The flip flop is clocked
by the least significant digit of the high order counter, and if
while the negative waveform is given by two = 0.693 RBC.
this digit is not blanked, the Q output of the flip flop goes high
The system is calibrated by using a 5MΩ potentiometer for
and turns on the NPN transistor, thereby inhibiting leading
RA as a “coarse” control and a 1kΩ potentiometer for RB as
zero blanking on the low order counter.

9-23
 ICM7217

It is possible to use separate thumbwheel switches for measured must be multiplied by 60. This can be done
presetting, but since the devices load data with the oscillator electronically using a phase-locked loop, or mechanically by
free-running, the multiplexing of the two devices is difficult to using a disc rotating with the object with the appropriate
synchronize. number of holes drilled around its edge to interrupt the light
from an LED to a photo-dector. For faster updating, use 0.1s
Precision Frequency Counter/Tachometer
gating, and multiply the rotational frequency by 600.
The circuit shown in Figure 23 is a simple implementation of
Auto-Tare System
a four digit frequency counter, using an ICM7207A to provide
the one second gating window and the STORE and RESET This circuit uses the count-up and count-down functions of
signals. In this configuration, the display reads hertz directly. the ICM7217, controlled via the EQUAL and ZERO outputs,
With Pin 11 of the ICM7027A connected to VDD , the gating to count in SYNC with an ICL7109A and ICL7109D Con-
time will be 0.1s; this will display tens of hertz at the least verter as shown in Figure 24. By RESETing the ICM7217 on
significant digit. For shorter gating times, an ICM7207 may a “tare” value conversion, and STORE-ing the result of a true
be used (with a 6.5536MHz crystal), giving a 0.01s gating value conversion, an automatic fare subtraction occurs in the
with Pin 11 connected to VDD , and a 0.1s gating with Pin 11 result.
open.
The ICM7217 stays in step with the ICL7109 by counting up
To implement a four digit tachometer, the ICM7207A with and down between 0 and 4095, for 8192 total counts, the
one second gating should be used. To get the display to read same number as the ICL7109 cycle. See applications note
directly in RPM, the rotational frequency of the object to be No. A047 for more details.

TABLE 2. CONTROL INPUT DEFINITIONS ICM7217

INPUT TERMINAL VOLTAGE FUNCTION

STORE 9 VDD (or floating) Output Latches Not Updated

VSS Output Latches Updated

UP/DOWN 10 VDD (or floating) Counter Counts Up

VSS Counter Counts Down

RESET 14 VDD (or floating) Normal Operation

VSS Counter Reset

LOAD COUNTER/ 12 Unconnected Normal Operation

I/O OFF VDD Counter Loaded with BCD data
VSS BCD Port Forced to Hi-Z Condition

LOAD REGlSTER/ 11 Unconnected Normal Operation

OFF VDD Register Loaded with BCD Data
VSS Display Drivers Disabled; BCD Port
Forced to Hi-Z Condition, mpx Counter
Reset to D4; mpx Oscillator Inhibited

DISPLAY CONTrol 23 Common Anode Unconnected Normal Operation

20 Common Cathode Segment Drivers Disabled
VDD Leading Zero Blanking Inhibited
VSS

9-24
 ICM7217

TO D4 STROBE TO D1 STROBE TO D4 STROBE TO D1 STROBE

C C C C

8 1 8 1 8 1 8 1
4 2 4 2 4 2 4 2

IN914 OR
EQUIVALENT

8 4 2 1 8 4 2 1

TO BCD INPUTS OF ICM7217, ICM7217B TO BCD INPUTS OF ICM7217A, ICM7217C

FIGURE 17. THUMBWHEEL SWITCH/DIODE CONNECTIONS

CARRY 1 21 - 23
7 SEGMENTS
ZERO 2 25 - 28

COMMON CATHODE
LED DISPLAY
4
5
BCD I/O
6
7
ICM7217A
COUNT INPUT 8 24 VDD
DISPLAY
9 CONTROL BLANK
STORE 20 NORMAL
INHIBIT LZB

19

14 15 - 18
4-DIGIT
RESET

FIGURE 18. UNIT COUNTER

9-25
 ICM7217

RA
5M 8 4
3K 10K
VDD RS 24
7 3 9 VDD
DIS OUT STORE
0.047µF
LED DISPLAY
RB ICM7217
1K
2 8
TR GATE COUNT
6
TH

VSS CV
1 5 14
0.47µF RESET
C VSS

20
GND

INVERTERS: CD40106B COUNT INPUT

NANDS: CD4011B
FIGURE 19A.

300µs 1s

GATE

50µs

STORE

RESET

FIGURE 19B.
FIGURE 19. INEXPENSIVE FREQUENCY COUNTER

STOP ZERO COMMON CATHODE

LOGIC TO GENERATE LED DISPLAY
RECORDER CONTROL EQ 1 28
SIGNALS CARRY d
ZERO b
EQUAL f 7 SEGMENTS
REEL SWITCH THUMBWHEEL SWITCHES
CLOSED ONCE/REV c
VDD

1M
4 DIGIT 9999 BCD I/O
a
e
VDD

COUNT IN g BLANK
STORE VDD
NORMAL
VDD
FORWARD UP/DOWN INHIBIT LZB
REWIND LOAD REG D1
0.0047µF N.O.
LOAD CTR D2
VDD
SET PT SCAN 4 DIGITS
D3
N.O.
RESET D4
RESET

FIGURE 20. TAPE RECORDER POSITION INDICATOR

9-26
 ICM7217

VDD
RUN MIN/SEC
100K

STOP SW1
1 14

2 13 RUN HRS/MIN

3 12

4 ICM7213 11
30pF
5 10 VDD
(4V MAX) TO LOGIC GENERATING
6 9 EQUAL SIGNALS FOR CONTROL OF
ZERO EXTERNAL EQUIPMENT
7 8

4
30pF 4.1943MHz CARRY D1
CRYSTAL
RS < 75Ω ZERO D2 DIGITS
EQUAL D3 4
THUMBWHEEL SWITCHES
D4

5959 4
BCD
I/O
VDD
DIS. CONT.

g
VDD BLANK
SW6
INHIBIT
VDD

LZB
COUNT IN
b
STORE
VDD VSS
ELAPSED COMMON ANODE
SW2 UP/DOWN
COUNTDOWN e LED DISPLAY
VDD LOAD REG
LOAD SET PT. f
SW3
DISPLAY OFF d
LOAD CTR 7
10K SEGMENTS
SCAN a
RESET c

VDD PRESET SW4 ICM7217

RESET SW5

FIGURE 21. PRECISION TIMER

9-27
 ICM7217

COMMON-ANODE
LED DISPLAY

COUNT INPUT

CARRY OUT 4 DIGITS CARRY/BORROW

1 25 - 28 4 DIGITS 7 SEGMENTS
4-7
BCD OUTPUTS 4 D1
HIGH ORDER DIGITS
BCD OUTPUTS
HIGH ORDER DIGITS

24 V+ 1 25 - 28
7 SEGMENTS 4-7
20 4
ICM7217

24 V+
8
20
9 1A
UP/DOWN 15 - 19 ICM7217
V+
10 21, 22
N.O. 1B 1/
4 23
14 CD4011
RESET
HIGH ORDER 8
9 15 - 19
10 21, 22
14

LOW ORDER

V+ D
1/
2 NPN
CD4013 Q TRANSISTOR
50kΩ 3kΩ
50kΩ
CL

FIGURE 22. 8-DIGIT UP/DOWN COUNTER

9-28
 ICM7217

COMMON ANODE
V+ = 5V LED DISPLAY

22pF 22pF 10kΩ 25 - 28

4 DIGITS
4
BCD 5 24
OUT
14 6
13 7
2

ICM7207A
ICM7217
10kΩ 10
4
5
COUNT
6 8 15 - 19
CRYSTAL STORE 21, 22 7 SEGMENTS
1/ 9
4
f = 5.24288MHz CD4011
RS = 75Ω
RESET 20
14

INPUT

FIGURE 23. PRECISION FREQUENCY COUNTER (MHz MAXIMUM)

400mV +5V
FULL SCALE 4 DIGIT COMMON ANODE
INPUT LED DISPLAY
+ -
S S
D Q D Q 270
Q Q 7
0.1µF R R
+5V LED
MINUS SIGN
1 GND VDD 40 +5V
100K
2 STATUS REF IN - 39
3 POL REF CAP - 38
1µF
4 OR REF CAP + 37 10K
5 B12 REF IN + 36 5 x 1N4148

6 B11 1 CARRY/ D0 28
IN HI 35 BORROW 7
7 B10 2 ZERO D1 27
IN LO 34
8 B9 3 EQUAL D2 26
COMMON 33
0.1µF 4 BCD 8 D3 25
9 B8 INT 32
0.22µF 5 BCD 4 VDD 24 +5V
10 B7 ICM7109 AZ 31
6 BCD 2 DISP. 23 47µF
11 B6 BUF 30 CONT.
47K 7 BCD 1 G 22
12 B5 REF OUT 29 100K
13 B4 VSS 28 8 COUNT B 21

14 B3 SEND 27 +5V 9 STORE VSS 20

15 B2 RUN/HOLD 26 10 UP/DOWN E 19
100pF
16 B1 BUF OSC OUT 25 +5V 11 LOAD REG. F 18
10µF 12 LOAD CTR. D 17
17 TEST OSC SEL 24
100K
18 LBEN OSC OUT 23 13 SCAN A 16

19 HBEN OSC IN 22 14 RESET C 15

20 CE/LOAD MODE 21 +5V ICM7217

TARE

FIGURE 24. AUTO-TARE SYSTEM FOR A/D CONVERTER

9-29
 ICM7217

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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9-30
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