DG201A, DG202

Data Sheet June 1999 File Number 3117.2

Quad SPST, CMOS Analog Switches Features

The DG201A and DG202 quad SPST analog switches are • Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
designed using Intersil’s 44V CMOS process. These
• Low rDS(ON) (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . 175Ω
bidirectional switches are latch-proof and feature break-
before-make switching. Designed to block signals up to • TTL, CMOS Compatible
30VP-P in the OFF state, the DG201A and DG202 offer the • Latch-Up Proof
advantages of low ON resistance (≤175Ω), wide input signal
range (±15V) and provide both TTL and CMOS compatibility. • True Second Source

The DG201A and DG202 are specification and pinout • Maximum Supply Ratings. . . . . . . . . . . . . . . . . . . . . . 44V
compatible with the industry standard devices. • Logic Inputs Accept Negative Voltages

Ordering Information Functional Block Diagrams

DG201A
TEMP. PKG.
PART NUMBER RANGE (oC) PACKAGE NO.
S1
DG201AAK -55 to 125 16 Ld CERDIP F16.3 IN1
D1
DG201ABK -25 to 85 16 Ld CERDIP F16.3
S2
DG201ACJ 0 to 70 16 Ld PDIP E16.3 IN2

DG201ACY 0 to 70 16 Ld SOIC M16.3 D2

S3
DG202AK -55 to 125 16 Ld CERDIP F16.3 IN3

DG202CJ 0 to 70 16 Ld PDIP E16.3 D3

S4

IN4
Pinout
D4
DG201A, DG202
(CERDIP, PDIP, SOIC)
TOP VIEW DG202

IN1 1 16 IN2 S1
IN1
D1 2 15 D2
D1
S1 3 14 S2
S2
V- 4 13 V+ (SUB-
-
STRATE) IN2
GND 5 12 NC D2
S4 6 11 S3 S3

D4 7 10 D3 IN3
D3
IN4 8 9 IN3
S4
IN4
D4

SWITCHES SHOWN FOR LOGIC “1” INPUT

TRUTH TABLE
LOGIC DG201A DG202
0 ON OFF
1 OFF ON
Logic “0” ≤0.8V, Logic “1” ≥ 2.4V

4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
 DG201A, DG202

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V CERDIP Package. . . . . . . . . . . . . . . . . 75 20
VIN to Ground (Note 1) . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A
VS or VD to V+ (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . +2 to (V-) -2V SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A
VS or VD to V- (Note 1) . . . . . . . . . . . . . . . . . . . . . . . -2 to (V+) +2V Maximum Junction Temperature
Current, any Terminal Except S or D . . . . . . . . . . . . . . . . . . . . 30mA Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 70mA Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions (SOIC - Lead Tips Only)
Temperature Range
“A” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
“B” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Signals on VS , VD , or VIN exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications V+ = 15V, V- = -15V, GND = 0V, TA = 25oC

“A” SUFFIX “B” AND “C” SUFFIX

(NOTE 3) (NOTE 3)
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON See Figure 1 - 480 600 - 480 - ns

Turn-OFF Time, tOFF See Figure 1 - 370 450 - 370 - ns

Charge Injection, Q CL = 1nF, RS = 0, VS = 0V - 20 - - 20 - pC

OFF Isolation, OIRR VIN = 5V, RL = 75Ω, VS = 2.0V, - 70 - - 70 - dB

f = 100kHz
Crosstalk (Channel to Channel), CCRR - -90 - - -90 - dB

Source OFF Capacitance, CS(OFF) f = 140kHz, VIN = 5V, VS = VD = 0V - 5.0 - - 5.0 - pF

Drain OFF Capacitance, CD(OFF) - 5.0 - - 5.0 - pF

Channel ON Capacitance, - 16 - - 16 - pF
CD(ON) + CS(ON)

DIGITAL INPUT CHARACTERISTICS

Input Current with Voltage High, IIH VIN = 2.4V -1.0 -0.0004 - -1.0 -0.0004 - µA

VIN = 15V - 0.003 1.0 - 0.003 1.0 µA

Input Current with Voltage Low, IIL VIN = 0V -1.0 -0.0004 - -1.0 -0.0004 - µA

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG -15 - 15 -15 - 15 V

Drain-Source ON Resistance, rDS(ON) VD = ±10V, VIN = 0.8V (DG201A) - 115 175 - 115 200 Ω
IS = 1mA, VIN = 2.4V (DG202)

Source OFF Leakage Current, IS(OFF) VIN = 2.4V VS = 14V, VD = -14V - 0.01 1.0 - 0.01 5.0 nA
(DG201A)
VIN = 0.8V VS = -14V, VD = 14V -1.0 -0.02 - -5.0 -0.02 - nA
(DG202)
Drain OFF Leakage Current, ID(OFF) VS = -14V, VD = 14V - 0.01 1.0 - 0.01 5.0 nA

VS = 14V, VD = -14V -1.0 -0.02 - -5.0 -0.02 - nA

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 DG201A, DG202

Electrical Specifications V+ = 15V, V- = -15V, GND = 0V, TA = 25oC (Continued)

“A” SUFFIX “B” AND “C” SUFFIX

(NOTE 3) (NOTE 3)
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Drain ON Leakage Current, ID(ON) VIN = 0.8V VD = VS = 14V - 0.1 1.0 - 0.1 5.0 µA
(Note 5) (DG201A)
VIN = 2.4V VD = VS = -14V -1.0 -0.15 - -5.0 -0.15 - µA
(DG202)

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ All Channels ON or OFF - 0.9 2 - 0.9 2 mA

Negative Supply Current, I- -1 -0.3 - -1 -0.3 - mA

Electrical Specifications V+ = 15V, V- = -15V, GND = 0V, TA Over Operating Temperature Range

“A” SUFFIX

(NOTE 3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUT CHARACTERISTICS

Input Current with Voltage High, IIH VIN = 2.4V -10 - - µA

VIN = 15V - - 10 µA

Input Current with Voltage Low, IIL VIN = 0V -10 - - µA

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG -15 - 15 V

Drain-Source ON Resistance, rDS(ON) VD = ±10V, VIN = 0.8V (DG201A) - - 250 Ω

IS = 1mA, VIN = 2.4V (DG202)

Source OFF Leakage Current, IS(OFF) VIN = 2.4V (DG201A) VS = 14V, VD = -14V - - 100 nA
VIN = 0.8V (DG202)
VS = -14V, VD = 14V -100 - - nA

Drain OFF Leakage Current, ID(OFF) VS = -14V, VD = 14V - - 100 nA

VS = 14V, VD = -14V -100 - - nA

Drain ON Leakage Current, ID(ON) (Note 5) VIN = 0.8V (DG201A) VD = VS = 14V - - 200 µA
VIN = 2.4V (DG202)
VD = VS = -14V -200 - - µA

NOTES:
3. Typical values are for design aid only, not guaranteed and not subject to production testing.
4. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet.
5. ID(ON) is leakage from driver into ON switch.

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 DG201A, DG202

Test Circuits and Waveforms

RL
VO = VS
LOGIC “0” = SWITCH ON RL + rDS(ON)
LOGIC † 3V 15V
INPUT V+
50% SWITCH
tr < 20ns SWITCH
INPUT
tf < 20ns S1 D1 OUTPUT
VS = 2V VO
SWITCH
INPUT
VS RL CL
IN1 1kΩ
90% 90% LOGIC 35pF
INPUT
SWITCH
OUTPUT
tON tOFF GND (REPEAT TEST FOR
V- IN2 , IN3 AND IN4)
† Logic shown for DG201A, invert for DG202. -15V

FIGURE 1. tON AND tOFF SWITCHING TEST CIRCUIT AND MEASUREMENT POINTS

∆VO
RS SX DX
VO
SWITCH
OUTPUT

INX
VS CL = 1nF

INX
ON ON
OFF

NOTES:
6. ∆VO = Measured voltage error due to charge injection.
7. The error in coulombs is Q = CL x ∆VO .
FIGURE 2. CHARGE INJECTION TEST CIRCUIT AND MEASUREMENT POINTS

+15V +15V

C C

SIGNAL V+ SIGNAL V+
GENERATOR VS GENERATOR 3 VS1 VD1 50Ω

VS VS

INX
VIN 0V, IN1 IN2 0V, 2.4V
2.4V
ANALYZER ANALYZER
CHAN A CHAN A
VD VD2 VS2
CHAN B CHAN B NC
GND V- GND V-
RL C RL C

-15V -15V

C = 0.001µF||0.1µF VS C = 0.001µF||0.1µF VS 1
Chip Capacitors OIRR = 20 Log -------
- Chip Capacitors CCRR = 20 Log -----------
VD VD 2

FIGURE 3. OFF ISOLATION TEST CIRCUIT FIGURE 4. CHANNEL TO CHANNEL CROSSTALK TEST
CIRCUIT

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 DG201A, DG202

Dual-In-Line Plastic Packages (PDIP)

E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C B1 0.045 0.070 1.15 1.77 8, 10
L
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.735 0.775 18.66 19.68 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES:
E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC -
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eB - 0.430 - 10.92 7
Publication No. 95.
L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3. N 16 16 9
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Rev. 0 12/93
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendic-
ular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

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 DG201A, DG202

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

c1 LEAD FINISH F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
-A- -D- 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

BASE INCHES MILLIMETERS

(c)
METAL
E SYMBOL MIN MAX MIN MAX NOTES
b1 A - 0.200 - 5.08 -
M M
-B- (b)
b 0.014 0.026 0.36 0.66 2

SECTION A-A
b1 0.014 0.023 0.36 0.58 3
bbb S C A-B S D S
b2 0.045 0.065 1.14 1.65 -
D
BASE b3 0.023 0.045 0.58 1.14 4
PLANE Q
-C- A c 0.008 0.018 0.20 0.46 2
SEATING
PLANE L c1 0.008 0.015 0.20 0.38 3
α
S1 D - 0.840 - 21.34 5
A A eA
b2 E 0.220 0.310 5.59 7.87 5
b e eA/2 c e 0.100 BSC 2.54 BSC -
ccc M C A - B S D S aaa M C A - B S D S eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat- L 0.125 0.200 3.18 5.08 -
ed adjacent to pin one and shall be located within the shaded Q 0.015 0.060 0.38 1.52 6
area shown. The manufacturer’s identification shall not be used
S1 0.005 - 0.13 - 7
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be α 90o 105o 90o 105o -
measured at the centroid of the finished lead surfaces, when aaa - 0.015 - 0.38 -
solder dip or tin plate lead finish is applied.
bbb - 0.030 - 0.76 -
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 -
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a M - 0.0015 - 0.038 2, 3
partial lead paddle. For this configuration dimension b3 replaces N 16 16 8
dimension b2.
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.

4-6
 DG201A, DG202

Small Outline Plastic Packages (SOIC)

N M16.3 (JEDEC MS-013-AA ISSUE C)

16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA H 0.25(0.010) M B M
INCHES MILLIMETERS
E
SYMBOL MIN MAX MIN MAX NOTES
-B-
A 0.0926 0.1043 2.35 2.65 -
1 2 3 A1 0.0040 0.0118 0.10 0.30 -
L
B 0.013 0.0200 0.33 0.51 9
SEATING PLANE C 0.0091 0.0125 0.23 0.32 -
-A- D 0.3977 0.4133 10.10 10.50 3
D A h x 45o
E 0.2914 0.2992 7.40 7.60 4
-C- e 0.050 BSC 1.27 BSC -
α
e H 0.394 0.419 10.00 10.65 -
A1
C h 0.010 0.029 0.25 0.75 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 16 16 7

NOTES: α 0o 8o 0o 8o -
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 0 12/93
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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