4-Channel, Software-Selectable, True

Bipolar Input, 12-Bit Plus Sign ADC

Data Sheet AD7324
FEATURES FUNCTIONAL BLOCK DIAGRAM
VDD REFIN/OUT VCC
12-bit plus sign SAR ADC
True bipolar input ranges AD7324
Software-selectable input ranges
±10 V, ±5 V, ±2.5 V, 0 V to +10 V VIN0
2.5V
VREF
13-BIT
1 MSPS throughput rate VIN1 I/P
T/H
SUCCESSIVE
VIN2 MUX APPROXIMATION
4 analog input channels with channel sequencer VIN3 ADC

Single-ended, true differential, and pseudo differential

analog input capability
High analog input impedance
DOUT
Low power: 21 mW SCLK
CHANNEL CONTROL LOGIC
Full power signal bandwidth: 22 MHz SEQUENCER AND REGISTERS CS
Internal 2.5 V reference DIN

High speed serial interface

VDRIVE
Power-down modes

04864-001
16-lead TSSOP package AGND VSS DGND

iCMOS™ process technology Figure 1.

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The AD73241 is a 4-channel, 12-bit plus sign, successive 1. The AD7324 can accept true bipolar analog input signals,
approximation ADC designed on the iCMOS (industrial ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.
CMOS) process. iCMOS is a process combining high voltage 2. The four analog inputs can be configured as four single-
silicon with submicron CMOS and complementary bipolar ended inputs, two true differential input pairs, two pseudo
technologies. It enables the development of a wide range of high differential inputs, or three pseudo differential inputs.
performance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage parts could achieve. 3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-
Unlike analog ICs using conventional CMOS processes, iCMOS compatible interface.
components can accept bipolar input signals while providing 4. Low power, 31 mW maximum, at 1 MSPS throughput rate.
increased performance, dramatically reduced power consumption, 5. Channel sequencer.
and reduced package size.
The AD7324 can accept true bipolar analog input signals. The Table 1. Similar Products Selection Table
AD7324 has four software-selectable input ranges: ±10 V, ±5 V, Device Throughput Number of
Number Rate Number of bits Channels
±2.5 V, and 0 V to +10 V. Each analog input channel can be
AD7329 1000 kSPS 12-bit plus sign 8
independently programmed to one of the four input ranges.
AD7328 1000 kSPS 12-bit plus sign 8
The analog input channels on the AD7324 can be programmed
AD7327 500 kSPS 12-bit plus sign 8
to be single-ended, true differential, or pseudo differential.
AD7323 500 kSPS 12-bit plus sign 4
The ADC contains a 2.5 V internal reference. The AD7324 also AD7322 1000 kSPS 12-bit plus sign 2
allows for external reference operation. If a 3 V reference is AD7321 500 kSPS 12-bit plus sign 2
applied to the REFIN/OUT pin, the AD7324 can accept a true
bipolar ±12 V analog input. Minimum ±12 V VDD and VSS
supplies are required for the ±12 V input range. The ADC has a
high speed serial interface that can operate at throughput rates
up to 1 MSPS.

Protected by U.S. Patent No. 6,731,232.

1

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD7324 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Control Register ......................................................................... 22

Functional Block Diagram .............................................................. 1 Sequence Register ....................................................................... 23

General Description ......................................................................... 1 Range Register ............................................................................ 24

Product Highlights ........................................................................... 1 Sequencer Operation ..................................................................... 25

Revision History ............................................................................... 2 Reference ..................................................................................... 27

Specifications..................................................................................... 3 VDRIVE ............................................................................................ 27

Timing Specifications .................................................................. 7 Modes of Operation ....................................................................... 28

Absolute Maximum Ratings............................................................ 8 Normal Mode.............................................................................. 28

ESD Caution .................................................................................. 8 Full Shutdown Mode.................................................................. 28

Pin Configuration and Function Description .............................. 9 Autoshutdown Mode ................................................................. 29

Typical Performance Characteristics ........................................... 10 Autostandby Mode ..................................................................... 29

Terminology .................................................................................... 14 Power vs. Throughput Rate ....................................................... 30

Theory of Operation ...................................................................... 16 Serial Interface ................................................................................ 31

Circuit Information .................................................................... 16 Microprocessor Interfacing ........................................................... 32

Converter Operation .................................................................. 16 AD7324 to ADSP-218x .............................................................. 32

Analog Input Structure .............................................................. 17 AD7324 to ADSP-BF53x ........................................................... 32

Typical Connection Diagram ................................................... 19 Application Hints ........................................................................... 33

Analog Input ............................................................................... 19 Layout and Grounding .............................................................. 33

Driver Amplifier Choice ............................................................ 21 Power Supply Configuration .................................................... 33

Registers ........................................................................................... 22 Outline Dimensions ....................................................................... 34

Addressing Registers .................................................................. 22 Ordering Guide .......................................................................... 34

REVISION HISTORY
12/13—Rev. A to Rev. B
Changes to Circuit Information Section and Table 6 ................ 16
Changes to Addressing Registers Section.................................... 22
Changes to Power Supply Configuration Section ...................... 33
1/10—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................ 5
Change to Endnote 1 in Table 4 ...................................................... 8
Added Power Supply Configuration Section, Figure 54,
and Table 16 ..................................................................................... 33

12/05—Revision 0: Initial Version

Rev. B | Page 2 of 36
Data Sheet AD7324

SPECIFICATIONS
Unless otherwise noted, VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to
3.0 V internal/external, fSCLK = 20 MHz, fS = 1 MSPS, TA = TMAX to TMIN; For VCC < 4.75 V, all specifications are typical.

Table 2.
B Version
Parameter 1 Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE FIN = 50 kHz sine wave
Signal-to-Noise Ratio (SNR) 2 76 dB Differential mode
72.5 dB Single-ended/pseudo differential mode
Signal-to-Noise + Distortion 75 dB Differential mode; ±2.5 V and ±5 V ranges
(SINAD)2
76 dB Differential mode; 0 V to 10 V and ±10 V ranges
72 dB Single-ended/pseudo differential mode; ±2.5 V and
±5 V ranges
72.5 dB Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges
Total Harmonic Distortion (THD)2 −80 dB Differential mode; ±2.5 V and ±5 V ranges
−82 dB Differential mode; 0 V to +10 V and ±10 V ranges
−77 dB Single-ended/pseudo differential mode; ±2.5 V and
±5 V ranges
−80 dB Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges
Peak Harmonic or Spurious −80 dB Differential mode; ±2.5 V and ±5 V ranges
Noise (SFDR)2
−82 dB Differential mode; 0 V to +10 V and ±10 V ranges
−78 dB Single-ended/pseudo differential mode; ±2.5 V and
±5 V ranges
−79 dB Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges
Intermodulation Distortion (IMD)2 fa = 50 kHz, fb = 30 kHz
Second-Order Terms −88 dB
Third-Order Terms −90 dB
Aperture Delay 3 7 ns
Aperture Jitter3 50 ps
Common-Mode Rejection Ratio −79 dB Up to 100 kHz ripple frequency; see Figure 17
(CMRR)2
Channel-to-Channel Isolation2 −72 dB FIN on unselected channels up to 100 kHz; see Figure 14
Full Power Bandwidth 22 MHz At 3 dB
5 MHz At 0.1 dB
DC ACCURACY 4 All dc accuracy specifications are typical for 0 V to
10 V mode.
Single-ended/pseudo differential mode 1 LSB =
FSR/4096, unless otherwise noted.
Differential mode 1 LSB = FSR/8192, unless otherwise
noted.
Resolution 13 Bits
No Missing Codes 12-bit Bits Differential mode
plus sign
(13 bits)
11-bit Bits Single-ended/pseudo differential mode
plus sign
(12 bits)
Integral Nonlinearity2 ±1.1 LSB Differential mode
±1 LSB Single-ended/pseudo differential mode
−0.7/+1.2 LSB Single-ended/pseudo differential mode
(LSB = FSR/8192)
Rev. B | Page 3 of 36
AD7324 Data Sheet
B Version
Parameter 1 Min Typ Max Unit Test Conditions/Comments
Differential Nonlinearity2 −0.9/+1.5 LSB Differential mode; guaranteed no missing codes to
13 bits
±0.9 LSB Single-ended mode; guaranteed no missing codes to
12 bits
−0.7/+1 LSB Single-ended/pseudo differential mode
(LSB = FSR/8192)
Offset Error2, 5 −4/+9 LSB Single-ended/pseudo differential mode
−7/+10 LSB Differential mode
Offset Error Match2, 5 ±0.6 LSB Single-ended/pseudo differential mode
±0.5 LSB Differential mode
Gain Error2, 5 ±8 LSB Single-ended/pseudo differential mode
±14 LSB Differential mode
Gain Error Match2, 5 ±0.5 LSB Single-ended/pseudo differential mode
±0.5 LSB Differential mode
Positive Full-Scale Error2, 6 ±4 LSB Single-ended/pseudo differential mode
±7 LSB Differential mode
Positive Full-Scale Error Match2, 6 ±0.5 LSB Single-ended/pseudo differential mode
±0.5 LSB Differential mode
Bipolar Zero Error2, 6 ±8.5 LSB Single-ended/pseudo differential mode
±7.5 LSB Differential mode
Bipolar Zero Error Match2, 6 ±0.5 LSB Single-ended/pseudo differential mode
±0.5 LSB Differential mode
Negative Full-Scale Error2, 6 ±4 LSB Single-ended/pseudo differential mode
±6 LSB Differential mode
Negative Full-Scale Error Match2, 6 ±0.5 LSB Single-ended/pseudo differential mode
±0.5 LSB Differential mode
ANALOG INPUT
Input Voltage Ranges Reference = 2.5 V; see Table 6
(Programmed via Range ±10 V VDD = 10 V min, VSS = −10 V min, VCC = +2.7 V to +5.25 V
Register)
±5 V VDD = +5 V min, VSS = −5 V min, VCC = +2.7 V to +5.25 V
±2.5 V VDD = +5 V min, VSS = −5 V min, VCC = +2.7 V to +5.25 V
0 to 10 V VDD = +10 V min, VSS = AGND min, VCC = +2.7 V to +5.25 V
Pseudo Differential VIN(−) VDD = +16.5 V, VSS = −16.5 V, VCC = +5 V; see Figure 40
Input Range and Figure 41
±3.5 V Reference = 2.5 V; range = ±10 V
±6 V Reference = 2.5 V; range = ±5 V
±5 V Reference = 2.5 V; range = ±2.5 V
+3/−5 V Reference = 2.5 V; range = 0 V to +10 V
DC Leakage Current ±80 nA VIN = VDD or VSS
3 nA Per channel, VIN = VDD or VSS
Input Capacitance3 13.5 pF When in track, ±10 V range
16.5 pF When in track, ±5 V and 0 V to +10 V ranges
21.5 pF When in track, ±2.5 V range
3 pF When in hold, all ranges
REFERENCE INPUT/OUTPUT
Input Voltage Range 2.5 3 V
Input DC Leakage Current ±1 µA
Input Capacitance 10 pF
Reference Output Voltage 2.5 V
Reference Output Voltage Error ±5 mV
at 25°C

Rev. B | Page 4 of 36
Data Sheet AD7324
B Version
Parameter 1 Min Typ Max Unit Test Conditions/Comments
Reference Output Voltage ±10 mV
TMIN to TMAX
Reference Temperature 25 ppm/°C
Coefficient
3 ppm/°C
Reference Output Impedance 7 Ω
LOGIC INPUTS
Input High Voltage, VINH 2.4 V
Input Low Voltage, VINL 0.8 V VCC = 4.75 V to 5.25 V
0.4 V VCC = 2.7 V to 3.6 V
Input Current, IIN ±1 µA VIN = 0 V or VDRIVE
Input Capacitance, CIN3 10 pF
LOGIC OUTPUTS
Output High Voltage, VOH VDRIVE − V ISOURCE = 200 µA
0.2 V
Output Low Voltage, VOL 0.4 V ISINK = 200 µA
Floating-State Leakage Current ±1 µA
Floating-State Output 5 pF
Capacitance3
Output Coding Straight natural binary Coding bit set to 1 in control register
Twos complement Coding bit set to 0 in control register
CONVERSION RATE
Conversion Time 800 ns 16 SCLK cycles with SCLK = 20 MHz
Track-and-Hold Acquisition 305 ns Full-scale step input; see the Terminology section
Time2, 3
Throughput Rate 1 MSPS See the Serial Interface section; VCC = 4.75 V to 5.25 V
770 kSPS VCC < 4.75 V
POWER REQUIREMENTS Digital inputs = 0 V or VDRIVE
VDD 12 16.5 V See Table 6
VSS −12 −16.5 V See Table 6
VCC 2.7 5.25 V See Table 6; typical specifications for VCC < 4.75 V
VDRIVE 2.7 5.25 V
Normal Mode (Static) 0.9 mA VDD/VSS = ±16.5 V, VCC/VDRIVE = 5.25 V
Normal Mode (Operational) fSAMPLE = 1 MSPS
IDD 360 µA VDD = 16.5 V
ISS 410 µA VSS = −16.5 V
ICC and IDRIVE 3.4 mA VCC/VDRIVE = 5.25 V
Autostandby Mode (Dynamic) fSAMPLE = 250 kSPS
IDD 200 µA VDD = 16.5 V
ISS 210 µA VSS = −16.5 V
ICC and IDRIVE 1.3 mA VCC/VDRIVE = 5.25 V
Autoshutdown Mode (Static) SCLK on or off
IDD 1 µA VDD = 16.5 V
ISS 1 µA VSS = −16.5 V
ICC and IDRIVE 1 µA VCC/VDRIVE = 5.25 V
Full Shutdown Mode SCLK on or off
IDD 1 µA VDD = 16.5 V
ISS 1 µA VSS = −16.5 V
ICC and IDRIVE 1 µA VCC/VDRIVE = 5.25 V

Rev. B | Page 5 of 36
AD7324 Data Sheet
B Version
Parameter 1 Min Typ Max Unit Test Conditions/Comments
POWER DISSIPATION
Normal Mode (Operational) 31 mW VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V
21 mW VDD = +12 V, VSS = −12 V, VCC = +5 V
Full Shutdown Mode 38.25 µW VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V
1
Temperature range is −40°C to +85°C.
2
See the Terminology section.
3
Sample tested during initial release to ensure compliance.
4
For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless
otherwise noted.
5
Unipolar 0 V to 10 V range with straight binary output coding.
6
Bipolar range with twos complement output coding.

Rev. B | Page 6 of 36
Data Sheet AD7324
TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25, VREF = 2.5 V to 3.0 V internal/external,
TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted. 1

Table 3.
Limit at TMIN, TMAX Description
Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit VDRIVE ≤ VCC
fSCLK 50 50 kHz min
14 20 MHz max
tCONVERT 16 × tSCLK 16 × tSCLK ns max tSCLK = 1/fSCLK
tQUIET 75 60 ns min Minimum time between end of serial read and next falling edge of CS
t1 12 5 ns min Minimum CS pulse width
t2 2 25 20 ns min CS to SCLK setup time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
45 35 ns min Unipolar input range (0 V to 10 V)
t3 26 14 ns max Delay from CS until DOUT three-state disabled
t4 57 43 ns max Data access time after SCLK falling edge
t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width
t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width
t7 13 8 ns min SCLK to data valid hold time
t8 40 22 ns max SCLK falling edge to DOUT high impedance
10 9 ns min SCLK falling edge to DOUT high impedance
t9 4 4 ns min DIN setup time prior to SCLK falling edge
t10 2 2 ns min DIN hold time after SCLK falling edge
tPOWER-UP 750 750 ns max Power up from autostandby
500 500 µs max Power up from full shutdown/autoshutdown mode, internal reference
25 25 µs typ Power up from full shutdown/autoshutdown mode, external reference
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2
When using VCC = 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.

t1
CS
tCONVERT
t2 t6
SCLK 1 2 3 4 5 13 14 15 16
2 IDENTIFICATION BITS t7 t5 t8
t3 t4 tQUIET
DOUT ADD1 ADD0 SIGN DB11 DB10 DB2 DB1 DB0
THREE- ZERO t10 THREE-STATE
STATE t9
04864-002

REG REG DON’T

DIN WRITE MSB LSB CARE
SEL1 SEL2

Figure 2. Serial Interface Timing Diagram

Rev. B | Page 7 of 36
AD7324 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
Table 4. may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
Parameter Rating
other conditions above those indicated in the operational
VDD to AGND, DGND −0.3 V to +16.5 V
section of this specification is not implied. Exposure to absolute
VSS to AGND, DGND +0.3 V to −16.5 V
maximum rating conditions for extended periods may affect
VDD to VCC VCC − 0.3 V to 16.5 V
device reliability.
VCC to AGND, DGND −0.3 V to +7 V
VDRIVE to AGND, DGND −0.3 V to +7 V
AGND to DGND −0.3 V to +0.3 V ESD CAUTION
Analog Input Voltage to AGND 1 VSS − 0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V
REFIN to AGND −0.3 V to VCC + 0.3 V
Input Current to Any Pin ±10 mA
Except Supplies 2
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP Package
θJA Thermal Impedance 150.4°C/W
θJC Thermal Impedance 27.6°C/W
Pb-Free Temperature, Soldering
Reflow 260(0)°C
ESD 2.5 kV
1
If the analog inputs are being driven from alternative VDD and VSS supply
circuitry, Schottky diodes should be placed in series with the AD7324 VDD
and VSS supplies. See Power Supply Configuration section.
2
Transient currents of up to 100 mA do not cause SCR latch-up.

Rev. B | Page 8 of 36
Data Sheet AD7324

PIN CONFIGURATION AND FUNCTION DESCRIPTION

CS 1 16 SCLK

DIN 2 15 DGND

DGND 3 14 DOUT
AD7324
AGND 4 TOP VIEW 13 VDRIVE
(Not to Scale)
REFIN/OUT 5 12 VCC

VSS 6 11 VDD

VIN0 7 10 VIN2

04864-003
VIN1 8 9 VIN3

Figure 3. TSSOP Pin Configuration

Table 5. Pin Function Description

Pin No. Mnemonic Description
1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7324 and frames the serial data transfer.
2 DIN Data In. Data should be written to the on-chip registers is provided on this input and is clocked into the
register on the falling edge of SCLK (see the Reference section).
3, 15 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7324. The DGND and AGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
4 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7324. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
5 REFIN/OUT Reference Input/Reference Output. The on-chip reference is available on this pin for external use to the
AD7324. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor
should be placed on the reference pin. Alternatively, the internal reference can be disabled, and an
external reference applied to this input. On power-up, the external reference mode is the default
condition (see the Reference section).
6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
7, 8, 10, 9 VIN0 to VIN3 Analog Input 0 to Analog Input 3. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the channel address Bit ADD1
and Bit ADD0 in the control register. The inputs can be configured as four single-ended inputs, two true
differential input pairs, two pseudo differential inputs, or three pseudo differential inputs. The config-
uration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and Bit Mode 0, in
the control register. The input range on each input channel is controlled by programming the range
register. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each analog input
channel when a +2.5 V reference voltage is used (see the Reference section).
11 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
12 VCC Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7324.
This supply should be decoupled to AGND. Specifications apply from VCC = 4.75 V to 5.25 V.
13 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VCC,
but it should not exceed VCC by more than 0.3 V.
14 DOUT Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The
data stream consists of a leading ZERO bit, two channel identification bits, the sign bit, and 12 bits of
conversion data. The data is provided MSB first (see the Serial Interface section).
16 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the
AD7324. This clock is also used as the clock source for the conversion process.

Rev. B | Page 9 of 36
AD7324 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0 1.0
4096 POINT FFT VCC = VDRIVE = 5V INT/EXT 2.5V REFERENCE
VCC = VDRIVE = 5V 0.8 TA = 25°C ±10V RANGE
–20 VDD, VSS = ±15V VDD, VSS = ±15V +INL = +0.55LSB
TA = 25°C 0.6 –INL = –0.68LSB
INT/EXT 2.5V REFERENCE
–40 ±10V RANGE 0.4

INL ERROR (LSB)

FIN = 50kHz
SNR = 77.30dB 0.2
SNR (dB)

–60 SINAD = 76.85dB

THD = –86.96dB 0
SFDR = –88.22dB
–80 –0.2

–0.4
–100
–0.6
–120
–0.8

–140 –1.0
0 1024 2048 3072 4096 5120 6144 7168 8192

04864-007
04864-004
0 50 100 150 200 250 300 350 400 450 500 512 1536 2560 3584 4608 5632 6656 7680
FREQUENCY (kHz) CODE

Figure 4. FFT True Differential Mode Figure 7. Typical INL True Differential Mode

1.0
0
4096 POINT FFT 0.8
VCC = VDRIVE = 5V
–20 VDD, VSS = ±15V 0.6
TA = 25°C
INT/EXT 2.5V REFERENCE 0.4
DNL ERROR (LSB)

–40 ±10V RANGE

FIN = 50kHz 0.2
SNR = 74.67dB
SNR (dB)

–60 SINAD = 74.03dB 0

THD = –82.68dB
SFDR = –85.40dB –0.2
–80
–0.4
–100
–0.6 VCC = VDRIVE = 5V ±10V RANGE
TA = 25°C +DNL = +0.79LSB
–0.8 VDD, VSS = ±15V –DNL = –0.38LSB
–120
INT/EXT 2.5V REFERENCE
–1.0
0 1024 2048 3072 4096 5120 6144 7168 8192

04864-043
–140 512 1536 2560 3584 4608 5632 6656 7680
04864-005

0 50 100 150 200 250 300 350 400 450 500

CODE
FREQUENCY (kHz)

Figure 5. FFT Single-Ended Mode Figure 8. Typical DNL Single-Ended Mode

1.0
1.0
0.8
0.8
0.6
0.6
0.4
INL ERROR (LSB)

0.4
DNL ERROR (LSB)

0.2
0.2
0
0
–0.2
–0.2 VCC = VDRIVE = 5V
–0.4
VCC = VDRIVE = 5V TA = 25°C
–0.4 TA = 25°C VDD, VSS = ±15V
VDD, VSS = ±15V –0.6
INT/EXT 2.5V REFERENCE
–0.6 INT/EXT 2.5V REFERENCE ±10V RANGE
±10V RANGE –0.8 +INL = +0.87LSB
–0.8 +DNL = +0.72LSB –INL = –0.49LSB
–DNL = –0.22LSB –1.0
0 1024 2048 3072 4096 5120 6144 7168 8192
04864-044

–1.0 512 1536 2560 3584 4608 5632 6656 7680

0 1024 2048 3072 4096 5120 6144 7168 8192
04864-006

512 1536 2560 3584 4608 5632 6656 7680 CODE

CODE

Figure 6. Typical DNL True Differential Mode Figure 9. Typical INL Single-Ended Mode

Rev. B | Page 10 of 36
Data Sheet AD7324
–50 80
VCC = 5V
–55 VDD/VSS = ±12V ±10V DIFF ±5V DIFF
TA = 25°C
75 ±2.5V DIFF
–60 fS = 1MSPS
±10V SE
–65 0V TO +10V SE 0V TO +10V DIFF
70 0V TO +10V SE
±5V SE
–70

SINAD (dB)
THD (dB)

±2.5V SE
±10V DIFF
–75 ±5V DIFF 65 ±10V SE ±5V SE
±2.5V DIFF 0V TO +10V DIFF
–80
60
–85
±2.5V SE
–90 VCC = 3V
55 VDD/VSS = ±12V
–95 TA = 25°C
fS = 1MSPS
–100 50

04864-008

04864-011
10 100 1000 10 100 1000
ANALOG INPUT FREQUENCY (kHz) ANALOG INPUT FREQUENCY (kHz)

Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and
Differential Mode (Diff) at 5 V VCC Differential Mode (Diff) at 3 V VCC

–50 –50
VCC = 3V
VDD/VSS = ±12V

CHANNEL-TO-CHANNEL ISOLATION (dB)

–55 –55
TA = 25°C
–60 fS = 1MSPS VCC = 3V
–60
±10V SE
VCC = 5V
–65
–65
0V TO +10V DIFF
–70 0V TO +10V SE
THD (dB)

–70
±5V SE
–75
–75
–80 ±10V DIFF
±2.5V SE –80
–85
VDD/VSS = ±12V
±5V DIFF –85 SINGLE-ENDED MODE
–90
fS = 1MSPS
–90 TA = 25°C
–95 50kHz ON SELECTED CHANNEL
±2.5V DIFF
–100 –95

04864-012
04864-009

10 100 1000 0 100 200 300 400 500 600

ANALOG INPUT FREQUENCY (kHz) FREQUENCY OF INPUT NOISE (kHz)

Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and True Figure 14. Channel-to-Channel Isolation
Differential Mode (Diff) at 3 V VCC

80 10k
9469
±10V DIFF VCC = 5V
±5V DIFF 9k VDD/VSS = ±12V
75 RANGE = ±10V
±2.5V DIFF
8k 10k SAMPLES
NUMBER OF OCCURRENCES

TA = 25°C
7k
70
±2.5V SE 6k
SINAD (dB)

0V TO +10V SE
65 ±10V SE ±5V SE 5k
0V TO +10V DIFF
4k
60
3k

VCC = 5V 2k
55 VDD/VSS = ±12V
TA = 25°C 1k
fS = 1MSPS 228 303
0 0
50 0
04864-010

04864-013

10 100 1000 –2 –1 0 1 2
ANALOG INPUT FREQUENCY (kHz) CODE

Figure 12. SINAD vs. Analog Input Frequency for Single-Ended (SE) and Figure 15. Histogram of Codes, True Differential Mode
Differential Mode (Diff) at 5 V VCC

Rev. B | Page 11 of 36
AD7324 Data Sheet
8k 2.0
7600
VCC = 5V
VDD/VSS = ±12V 1.5
7k
RANGE = ±10V
10k SAMPLES INL = 500kSPS
1.0 INL = 750kSPS
NUMBER OF OCCURENCES

6k TA = 25°C

INL ERROR (LSB)

5k 0.5

INL = 1MSPS
4k 0
INL = 500kSPS
INL = 750kSPS
3k –0.5

2k –1.0
1201 1165 ±5V RANGE
INL = 1MSPS
–1.5 VCC = VDRIVE = 5V
1k INTERNAL REFERENCE
0 23 11 0 SINGLE-ENDED MODE
0 –2.0
5 7 9 11 13 15 17 19

04864-014

04864-050
–3 –2 –1 0 1 2 3
CODE ±VDD/VSS SUPPLY VOLTAGE (V)

Figure 16. Histogram of Codes, Single-Ended Mode Figure 19. INL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS

–50 –50
100mV p-p SINE WAVE ON EACH SUPPLY
–55 –55 NO DECOUPLING
SINGLE-ENDED MODE
–60 –60 fS = 1MSPS
VCC = 5V
–65 –65

–70 VCC = 5V –70 VCC = 3V

CMRR (dB)

PSRR (dB)

–75 –75
VDD = 12V
–80 VCC = 3V –80

–85 DIFFERENTIAL MODE –85

FIN = 50kHz VSS = –12V
–90 VDD/VSS = ±12V –90
fS = 1MSPS
–95 TA = 25°C –95

–100 –100
04864-055

04864-054
200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
RIPPLE FREQUENCY (kHz) SUPPLY RIPPLE FREQUENCY (kHz)
Figure 17. CMRR vs. Common-Mode Ripple Frequency Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

2.0 –50
VCC = VDRIVE = 5V
DNL = 750kSPS VDD/VSS = ±12V
1.5 –55
TA = 25°C
DNL = 500kSPS
INTERNAL REFERENCE
–60 RANGE = ±10V AND ±2.5V RIN = 100Ω, ±10V RANGE
1.0
RIN = 50Ω,
DNL ERROR (LSB)

–65 ±10V RANGE

0.5 RIN = 2000Ω, ±10V RANGE
DNL = 1MSPS RIN = 1000Ω, ±10V RANGE RIN = 4700Ω,
THD (dB)

–70
±2.5V RANGE
0 DNL = 1MSPS
–75 RIN = 2000Ω,
±2.5V RANGE
–0.5
–80 RIN = 1000Ω,
±2.5V RANGE
–1.0 DNL = 750kSPS DNL = 500kSPS
–85 RIN = 100Ω,
±5V RANGE
VCC = VDRIVE = 5V ±2.5V RANGE
–1.5 –90
INTERNAL REFERENCE RIN = 50Ω,
SINGLE-ENDED MODE ±2.5V RANGE
–2.0 –95
04864-015

5 7 9 11 13 15 17 19 10 100 1000
04864-049

±VDD/VSS SUPPLY VOLTAGE (V) ANALOG INPUT FREQUENCY (kHz)

Figure 18. DNL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,
True Differential Mode

Rev. B | Page 12 of 36
Data Sheet AD7324
–50
VCC = VDRIVE = 5V
VDD/VSS = ±12V
–55
TA = 25°C
INTERNAL REFERENCE
–60 RANGE = ±10V AND ±2.5V
RIN = 100Ω,
–65 ±10V RANGE
RIN = 2000Ω, ±10V RANGE
RIN = 1000Ω, ±10V RANGE RIN = 50Ω,
THD (dB)

–70
±10V RANGE

–75 RIN = 2000Ω,

±2.5V RANGE
–80 RIN = 1000Ω,
±2.5V RANGE
–85 RIN = 100Ω,
±2.5V RANGE
–90 RIN = 50Ω,
±2.5V RANGE
–95

04864-016
10 100 1000
INPUT FREQUENCY (kHz)

Figure 22. THD vs. Analog Input Frequency for Various

Source Impedances, Single-Ended Mode

Rev. B | Page 13 of 36
AD7324 Data Sheet

TERMINOLOGY
Differential Nonlinearity Negative Full-Scale Error
This is the difference between the measured and the ideal 1 LSB This applies when using twos complement output coding and
change between any two adjacent codes in the ADC. any of the bipolar analog input ranges. This is the deviation of
the first code transition (10 … 000) to (10 … 001) from the ideal
Integral Nonlinearity (that is, −4 × VREF + 1 LSB, −2 × VREF + 1 LSB, −VREF + 1 LSB)
This is the maximum deviation from a straight line passing after adjusting for the bipolar zero code error.
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (a point 1 LSB Negative Full-Scale Error Match
below the first code transition) and full scale (a point 1 LSB This is the difference in negative full-scale error between any
above the last code transition). two input channels.
Offset Code Error Track-and-Hold Acquisition Time
This applies to straight binary output coding. It is the deviation The track-and-hold amplifier returns into track mode after the
of the first code transition (00 ... 000) to (00 ... 001) from the 14th SCLK rising edge. Track-and-hold acquisition time is the
ideal, that is, AGND + 1 LSB. time required for the output of the track-and-hold amplifier to
Offset Error Match reach its final value, within ±1/2 LSB, after the end of a conversion.
This is the difference in offset error between any two input For the ±2.5 V range, the specified acquisition time is the time
channels. required for the track-and-hold amplifier to settle to within ±1 LSB.

Gain Error Signal to (Noise + Distortion) Ratio

This applies to straight binary output coding. It is the deviation This is the measured ratio of signal to (noise + distortion) at the
of the last code transition (111 ... 110) to (111 ... 111) from the output of the ADC. The signal is the rms amplitude of the
ideal (that is, 4 × VREF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) fundamental. Noise is the sum of all nonfundamental signals up
after adjusting for the offset error. to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digi-
Gain Error Match tization process. The more levels, the smaller the quantization
This is the difference in gain error between any two input noise. Theoretically, the signal to (noise + distortion) ratio for
channels. an ideal N-bit converter with a sine wave input is given by
Bipolar Zero Code Error Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
This applies when using twos complement output coding and
a bipolar analog input. It is the deviation of the midscale For a 13-bit converter, this is 80.02 dB.
transition (all 1s to all 0s) from the ideal input voltage, that Total Harmonic Distortion
is, AGND − 1 LSB. Total harmonic distortion (THD) is the ratio of the rms sum of
Bipolar Zero Code Error Match harmonics to the fundamental. For the AD7324, it is defined as
This refers to the difference in bipolar zero code error between V2 2 + V3 2 + V 4 2 + V5 2 + V6 2
any two input channels. THD (dB) = 20 log
V1
Positive Full-Scale Error
This applies when using twos complement output coding and where V1 is the rms amplitude of the fundamental, and V2, V3,
any of the bipolar analog input ranges. It is the deviation of the V4, V5, and V6 are the rms amplitudes of the second through the
last code transition (011 … 110) to (011 … 111) from the ideal sixth harmonics.
(4 × VREF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) after adjusting Peak Harmonic or Spurious Noise
for the bipolar zero code error. Peak harmonic or spurious noise is defined as the ratio of the
Positive Full-Scale Error Match rms value of the next largest component in the ADC output
This is the difference in positive full-scale error between any spectrum (up to fS/2, excluding dc) to the rms value of the
two input channels. fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, the
largest harmonic could be a noise peak.

Rev. B | Page 14 of 36
Data Sheet AD7324
Channel-to-Channel Isolation As a result, the second- and third-order terms are specified
Channel-to-channel isolation is a measure of the level of crosstalk separately. The calculation of the intermodulation distortion is
between any two channels. It is measured by applying a full-scale, per the THD specification, where it is the ratio of the rms sum
100 kHz sine wave signal to all unselected input channels and of the individual distortion products to the rms amplitude of
determining the degree to which the signal attenuates in the the sum of the fundamentals expressed in decibels.
selected channel with a 50 kHz signal. Figure 14 shows the worst- PSR (Power Supply Rejection)
case across all eight channels for the AD7324. The analog input Variations in power supply affect the full-scale transition but
range is programmed to be the same on all channels. not the linearity of the converter. Power supply rejection is the
Intermodulation Distortion maximum change in the full-scale transition point due to a
With inputs consisting of sine waves at two frequencies, fa and change in power supply voltage from the nominal value (see the
fb, any active device with nonlinearities creates distortion Typical Performance Characteristics section).
products at sum and difference frequencies of mfa ± nfb, where CMRR (Common-Mode Rejection Ratio)
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms CMRR is defined as the ratio of the power in the ADC output at
are those for which neither m nor n are equal to 0. For example, full-scale frequency, f, to the power of a 100 mV sine wave
the second-order terms include (fa + fb) and (fa − fb), whereas applied to the common-mode voltage of the VIN+ and VIN−
the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), frequency, fS, as
and (fa − 2fb).
CMRR (dB) = 10 log (Pf/PfS)
The AD7324 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. where Pf is the power at frequency f in the ADC output, and PfS
In this case, the second-order terms are usually distanced in is the power at frequency fS in the ADC output (see Figure 17).
frequency from the original sine waves, whereas the third-order
terms are usually at a frequency close to the input frequencies.

Rev. B | Page 15 of 36
AD7324 Data Sheet

THEORY OF OPERATION
CIRCUIT INFORMATION The analog inputs can be configured as four single-ended
inputs, two true differential input pairs, two pseudo differential
The AD7324 is a fast, 4-channel, 12-bit plus sign, bipolar input, inputs, or three pseudo differential inputs. Selection can be
serial ADC. The AD7324 can accept bipolar input ranges that made by programming the mode bits, Mode 0 and Mode 1, in
include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to +10 V the control register.
unipolar input range. A different analog input range can be
programmed on each analog input channel via the on-chip The serial clock input accesses data from the part and provides
registers. The AD7324 has a high speed serial interface that can the clock source for the successive approximation ADC. The
operate at throughput rates up to 1 MSPS. AD7324 has an on-chip 2.5 V reference. However, the AD7324
can also work with an external reference. On power-up, the
The AD7324 requires VDD and VSS dual supplies for the high voltage external reference operation is the default option. If the internal
analog input structures. These supplies must be equal to or greater reference is the preferred option, the user must write to the
than the analog input range. See Table 6 for the requirements of reference bit in the control register to select the internal
these supplies for each analog input range. The AD7324 requires reference operation.
a low voltage 2.7 V to 5.25 V VCC supply to power the ADC core.
The AD7324 also features power-down options to allow power
Table 6. Reference and Supply Requirements for Each saving between conversions. The power-down modes are
Analog Input Range selected by programming the on-chip control register as
Selected Full-Scale described in the Modes of Operation section.
Analog Input Reference Input Minimum
Range (V) Voltage (V) Range (V) AVCC (V) VDD/VSS (V)1 CONVERTER OPERATION
±10 2.5 ±10 3/5 ±10 The AD7324 is a successive approximation ADC built around
3.0 ±12 3/5 ±12
two capacitive DACs. Figure 23 and Figure 24 show simplified
±5 2.5 ±5 3/5 ±5
schematics of the ADC in single-ended mode during the
3.0 ±6 3/5 ±6
acquisition and conversion phases, respectively. Figure 25 and
±2.5 2.5 ±2.5 3/5 ±5
Figure 26 show simplified schematics of the ADC in differential
3.0 ±3 3/5 ±5
0 to +10 2.5 0 to +10 3/5 +10/AGND
mode during acquisition and conversion phases, respectively.
3.0 0 to +12 3/5 +12/AGND The ADC is composed of control logic, a SAR, and capacitive
1
Guaranteed performance for VDD = 12 V to 16.5 V and VSS = −12 V to −16.5 V. DACs. In Figure 23 (the acquisition phase), SW2 is closed and
The performance specifications are guaranteed for VDD = 12 V SW1 is in Position A, the comparator is held in a balanced
to 16.5 V and VSS = −12 V to −16.5 V. With VDD and VSS supplies condition, and the sampling capacitor array acquires the signal
outside this range, the AD7324 is functional but performance is on the input.
not guaranteed. To meet the specified performance specifications CAPACITIVE
DAC
when the AD7324 is configured with the minimum VDD and VSS
COMPARATOR
supplies for a chosen analog input range, the throughput rate B
CS
VIN0
should be decreased from the maximum throughput range (see A SW1
SW2 CONTROL
LOGIC 04864-017

the Typical Performance Characteristics section). Figure 18 and

AGND
Figure 19 show the change in INL and DNL as the VDD and VSS
voltages are varied. When operating at the maximum throughput Figure 23. ADC Acquisition Phase (Single-Ended)
rate, as the VDD and VSS supply voltages are reduced, the INL When the ADC starts a conversion (Figure 24), SW2 opens and
and DNL error increases. However, as the throughput rate is SW1 moves to Position B, causing the comparator to become
reduced with the minimum VDD and VSS supplies, the INL and unbalanced. The control logic and the charge redistribution
DNL error is reduced. DAC are used to add and subtract fixed amounts of charge from
Figure 31 shows the change in THD as the VDD and VSS supplies the capacitive DAC to bring the comparator back into a
are reduced. At the maximum throughput rate, the THD degrades balanced condition. When the comparator is rebalanced, the
significantly as VDD and VSS are reduced. It is, therefore, necessary conversion is complete. The control logic generates the ADC
to reduce the throughput rate when using minimum VDD and output code.
VSS supplies so that there is less degradation of THD and the CAPACITIVE
specified performance can be maintained. The degradation is DAC

due to an increase in the on resistance of the input multiplexer B

CS COMPARATOR

when the VDD and VSS supplies are reduced. VIN0

A SW1
SW2 CONTROL
LOGIC
04864-018

AGND

Figure 24. ADC Conversion Phase (Single-Ended)

Rev. B | Page 16 of 36
Data Sheet AD7324
Figure 25 shows the differential configuration during the The ideal transfer characteristic for the AD7324 when twos
acquisition phase. For the conversion phase, SW3 opens and complement coding is selected is shown in Figure 27. The ideal
SW1 and SW2 move to Position B (Figure 26). The output transfer characteristic for the AD7324 when straight binary
impedances of the source driving the VIN+ and VIN− pins must coding is selected is shown in Figure 28.
be matched; otherwise, the two inputs have different settling
times, resulting in errors. 011...111
011...110

CAPACITIVE

ADC CODE
DAC 000...001
COMPARATOR 000...000
B CS 111...111
VIN+
A SW1 CONTROL
SW3
A SW2 LOGIC
VIN– 100...010
B 100...001
CS
100...000
–FSR/2 + 1LSB AGND – 1LSB +FSR/2 – 1LSB BIPOLAR RANGES

04864-019

04864-021
VREF
CAPACITIVE AGND + 1LSB +FSR – 1LSB UNIPOLAR RANGE
DAC ANALOG INPUT

Figure 25. ADC Differential Configuration During Acquisition Phase Figure 27. Twos Complement Transfer Characteristic (Bipolar Ranges)

CAPACITIVE 111...111
DAC
111...110
COMPARATOR
B CS

ADC CODE
VIN+ 111...000
A SW1 CONTROL
SW3
A SW2 LOGIC
VIN– 011...111
B CS
04864-020

VREF 000...010
CAPACITIVE 000...001
DAC
000...000
–FSR/2 + 1LSB +FSR/2 – 1LSB BIPOLAR RANGES
Figure 26. ADC Differential Configuration During Conversion Phase

04864-022
AGND + 1LSB +FSR – 1LSB UNIPOLAR RANGE
ANALOG INPUT
Output Coding
Figure 28. Straight Binary Transfer Characteristic (Bipolar Ranges)
The AD7324 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control ANALOG INPUT STRUCTURE
register. To change the output coding to straight binary coding, The analog inputs of the AD7324 can be configured as single-
the coding bit in the control register must be set. When ended, true differential, or pseudo differential via the control
operating in sequence mode, the output coding for each register mode bits (see Table 10). The AD7324 can accept true
channel in the sequence is the value written to the coding bit bipolar input signals. On power-up, the analog inputs operate as
during the last write to the control register. four single-ended analog input channels. If true differential or
pseudo differential is required, a write to the control register is
Transfer Functions
necessary after power-up to change this configuration.
The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is Figure 29 shows the equivalent analog input circuit of the
dependent on the analog input range selected. AD7324 in single-ended mode. Figure 30 shows the equivalent
analog input structure in differential mode. The two diodes
Table 7. LSB Sizes for Each Analog Input Range provide ESD protection for the analog inputs.
Input Range Full-Scale Range/8192 Codes LSB Size VDD

±10 V 20 V 2.441 mV D
R1 C2
±5 V 10 V 1.22 mV VIN0

±2.5 V 5V 0.61 mV C1 D
04864-023

0 V to +10 V 10 V 1.22 mV VSS

Figure 29. Equivalent Analog Input Circuit (Single-Ended)

Rev. B | Page 17 of 36
AD7324 Data Sheet
VDD
The AD7324 enters track mode on the 14th SCLK rising edge.
D C2
When running the AD7324 at a throughput rate of 1 MSPS with
R1
VIN+ a 20 MHz SCLK signal, the ADC has approximately
C1 D
1.5 SCLK + t8 + tQUIET
VSS
to acquire the analog input signal. The ADC goes back into
VDD hold mode on the CS falling edge.

D
As the VDD/VSS supply voltage is reduced, the on resistance of
R1 C2
VIN– the input multiplexer increases. Therefore, based on the equation
C1 D for tACQ, it is necessary to increase the amount of acquisition

04864-024
VSS
time provided to the AD7324 and, therefore, decrease the overall
throughput rate. Figure 31 shows that if the throughput rate is
Figure 30. Equivalent Analog Input Circuit (Differential)
reduced when operating with minimum VDD and VSS supplies,
Care should be taken to ensure that the analog input does not the specified THD performance is maintained.
exceed the VDD and VSS supply rails by more than 300 mV. –50
VCC = VDRIVE = 5V
Exceeding this value causes the diodes to become forward –55
INTERNAL REFERENCE
TA = 25°C
biased and to start conducting into either the VDD supply rail or FIN = 10kHz
–60
VSS supply rail. These diodes can conduct up to 10 mA without ±5V RANGE
SE MODE
causing irreversible damage to the part. –65

THD (dB)
In Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and –70

can primarily be attributed to pin capacitance. Resistor R1 is a –75 1MSPS

lumped component made up of the on resistance of the input
–80
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the –85 750kSPS

analog input range selected (see the Specifications section). –90

500kSPS
Track-and-Hold Section –95

04864-051
5 7 9 11 13 15 17 19
The track-and-hold on the analog input of the AD7324 allows ±VDD/VSS SUPPLIES (V)
the ADC to accurately convert an input sine wave of full-scale Figure 31. THD vs. ±VDD/VSS Supply Voltage at 500 kSPS, 750 kSPS,
amplitude to 13-bit accuracy. The input bandwidth of the track- and 1 MSPS
and-hold is greater than the Nyquist rate of the ADC. The
Unlike other bipolar ADCs, the AD7324 does not have a
AD7324 can handle frequencies up to 22 MHz.
resistive analog input structure. On the AD7324, the bipolar
The track-and-hold enters its tracking mode on the 14th SCLK analog signal is sampled directly onto the sampling capacitor.
rising edge after the CS falling edge. The time required to This gives the AD7324 high analog input impedance. An
acquire an input signal depends on how quickly the sampling approximation for the analog input impedance can be
capacitor is charged. With 0 source impedance, 305 ns are calculated from the following formula:
sufficient to acquire the signal to the 13-bit level. The Z = 1/(fS × CS)
acquisition time required is calculated using the following
formula: where fS is the sampling frequency, and CS is the sampling
capacitor value.
tACQ = 10 × ((RSOURCE + R) × C)
CS depends on the analog input range chosen (see the
where C is the sampling capacitance and R is the resistance seen Specifications section). When operating at 1 MSPS, the analog
by the track-and-hold amplifier looking back on the input. For input impedance is typically 75 kΩ for the ±10 V range. As the
the AD7324, the value of R includes the on resistance of the sampling frequency is reduced, the analog input impedance
input multiplexer and is typically 300 Ω. RSOURCE should include further increases. As the analog input impedance increases the
any extra source impedance on the analog input. current required to drive the analog input, therefore, decreases.

Rev. B | Page 18 of 36
Data Sheet AD7324
V+ 5V
TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7324.
AGND
In this configuration, the AGND pin is connected to the analog VIN+ VDD VCC
ground plane of the system, and the DGND pin is connected to AD73241
the digital ground plane of the system. The analog inputs on the
VSS
AD7324 can be configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7324 can operate
with either an internal or external reference. In Figure 32, the
AD7324 is configured to operate with the internal 2.5 V reference. V–

04864-026
A 680 nF decoupling capacitor is required when operating with 1ADDITIONAL PINS OMITTED FOR CLARITY.

the internal reference. Figure 33. Single-Ended Mode Typical Connection Diagram

The VCC pin can be connected to either a 3 V supply voltage or a True Differential Mode
5 V supply voltage. The VDD and VSS are the dual supplies for the The AD7324 can have a total of two true differential analog
high voltage analog input structures. The voltage on these pins input pairs. Differential signals have some benefits over single-
must be equal to or greater than the highest analog input range ended signals, including better noise immunity based on the
selected on the analog input channels (see Table 6). The VDRIVE common-mode rejection of the device and improvements in
pin is connected to the supply voltage of the microprocessor. distortion performance. Figure 34 defines the configuration of
The voltage applied to the VDRIVE input controls the voltage of the true differential analog inputs of the AD7324.
the serial interface. VDRIVE can be set to 3 V or 5 V.
+15V VCC +2.7V TO +5.25V VIN+
+ +
0.1µF 10µF 10µF 0.1µF
AD73241
VIN–
VDD1 VCC
+3V SUPPLY

04864-027
VDRIVE
10µF + 0.1µF 1ADDITIONAL PINS OMITTED FOR CLARITY.
AD7324
Figure 34. True Differential Inputs
CS
VIN0
ANALOG INPUTS VIN1
DOUT
µC/µP The amplitude of the differential signal is the difference
SCLK
±10V, ±5V, ±2.5V
0V TO +10V VIN2 DIN between the signals applied to the VIN+ and VIN− pins in
VIN3
each differential pair (VIN+ − VIN−). VIN+ and VIN− should
DGND
SERIAL
be simultaneously driven by two signals of equal amplitude,
INTERFACE
680nF
REFIN/OUT dependent on the input range selected, that are 180° out of
VSS1 AGND
phase. Assuming the ±4 × VREF mode, the amplitude of the
–15V differential signal is −20 V to +20 V p-p (2 × 4 × VREF),
0.1µF 10µF 1MINIMUM
VDD AND VSS SUPPLY VOLTAGES regardless of the common mode.
04864-025

+
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
The common mode is the average of the two signals
Figure 32. Typical Connection Diagram
(VIN+ + VIN−)/2
ANALOG INPUT and is, therefore, the voltage on which the two input signals
Single-Ended Inputs are centered.
The AD7324 has a total of four analog inputs when operating in This voltage is set up externally, and its range varies with
single-ended mode. Each analog input can be independently reference voltage. As the reference voltage increases, the
programmed to one of the four analog input ranges. In applications common-mode range decreases. When driving the differential
where the signal source is high impedance, it is recommended inputs with an amplifier, the actual common mode range is
to buffer the signal before applying it to the ADC analog inputs. determined by the output swing of the amplifier. If the
Figure 33 shows the configuration of the AD7324 in single- differential inputs are not driven from an amplifier, the
ended mode. common-mode range is determined by the supply voltage on
the VDD supply pin and the VSS supply pin.
When a conversion takes place, the common mode is rejected,
resulting in a noise-free signal of amplitude −2 × (4 × VREF) to +2 ×
(4 × VREF) corresponding to digital Code −4096 to Code +4095.

Rev. B | Page 19 of 36
AD7324 Data Sheet
5 8
±5V RANGE
4 ±5V RANGE
6 ±10V ±2.5V
±5V RANGE RANGE RANGE
3 ±2.5V
RANGE 4
2
±10V
RANGE
VCOM RANGE (V)

VCOM RANGE (V)

1 2
0
0
–1 ±10V
RANGE ±2.5V
–2 RANGE –2
±10V
–3 RANGE
–4
±5V RANGE
–4
VCC = 3V –6
–5 VCC = 5V ±2.5V
VREF = 3V RANGE
VREF = 2.5V

04864-045

04864-048
–6 –8
±16.5V VDD/VSS ±12V VDD/VSS ±16.5V VDD/VSS ±12V VDD/VSS

Figure 35. Common-Mode Range for VCC = 3 V and REFIN/OUT = 3 V Figure 38. Common-Mode Range for VCC = 5 V and REFIN/OUT = 2.5 V
8
Pseudo Differential Inputs
6
±5V RANGE ±5V RANGE The AD7324 can have two pseudo differential pairs or three
±2.5V ±2.5V
pseudo differential inputs referenced to a common VIN− pin.
4 ±10V
RANGE RANGE The VIN+ inputs are coupled to the signal source and must have
VCOM RANGE (V)

RANGE an amplitude within the selected range for that channel as

2 programmed in the range register. A dc input is applied to the
±10V
RANGE
VIN− pin. The voltage applied to this input provides an offset
0 for the VIN+ input from ground or a pseudo ground. Pseudo
differential inputs separate the analog input signal ground from
–2 the ADC ground, allowing cancellation of dc common-mode
VCC = 5V
VREF = 3V voltages. Figure 39 shows the AD7324 configured in pseudo
04864-046

–4 differential mode.
±16.5V VDD/VSS ±12V VDD/VSS
When a conversion takes place, the pseudo ground corresponds
Figure 36. Common-Mode Range for VCC = 5 V and REFIN/OUT = 3 V
to Code −4096, and the maximum amplitude corresponds to
6
Code +4095.
4 V+ 5V
±5V RANGE ±5V RANGE

2
VCOM RANGE (V)

VIN+ VDD VCC

0
AD73241
–2 VIN– VSS
±2.5V ±10V
RANGE RANGE
±10V ±2.5V
–4 RANGE RANGE

–6 V–
04864-028

VCC = 3V
VREF = 2.5V 1ADDITIONAL PINS OMITTED FOR CLARITY.
04864-047

–8
±16.5V VDD/VSS ±12V VDD/VSS Figure 39. Pseudo Differential Inputs
Figure 37. Common-Mode Range for VCC = 3 V and REFIN/OUT = 2.5 V Figure 40 and Figure 41 show the typical voltage range on the
VIN− pin for the different analog input ranges when configured
in the pseudo differential mode.
For example, when the AD7324 is configured to operate in
pseudo differential mode and the ±5 V range is selected with
±16.5 V VDD/VSS supplies and 5 V VCC, the voltage on the VIN−
pin can vary from −6.5 V to +6.5 V.

Rev. B | Page 20 of 36
Data Sheet AD7324
8
±5V RANGE ±5V RANGE
The driver amplifier must be able to settle for a full-scale step to
6 ±2.5V a 13-bit level, 0.0122%, in less than the specified acquisition
PSEUDO INPUT VOLTAGE RANGE (V)

RANGE
±10V
±2.5V
RANGE time of the AD7324. An op amp such as the AD8021 meets this
4 RANGE
requirement when operating in single-ended mode. The AD8021
2 needs an external compensating NPO type of capacitor. The
AD8022 can also be used in high frequency applications where
0
a dual version is required. For lower frequency applications, op
–2 amps such as the AD797, AD845, and AD8610 can be used with
±10V
RANGE the AD7324 in single-ended mode configuration.
–4
Differential operation requires that VIN+ and VIN− be simulta-
–6 0V TO +10V 0V TO +10V
VCC = 5V RANGE RANGE neously driven with two signals of equal amplitude that are 180°
VREF = 2.5V
out of phase. The common mode must be set up externally to the

04864-039
–8
±16.5V VDD/VSS ±12V VDD/VSS AD7324. The common-mode range is determined by the REFIN/
Figure 40. Pseudo Input Range with VCC = 5 V OUT voltage, the VCC supply voltage, and the particular amplifier
used to drive the analog inputs. Differential mode with either an
4
ac input or a dc input provides the best THD performance over a
±5V RANGE wide frequency range. Because not all applications have a signal
±5V RANGE ±2.5V preconditioned for differential operation, there is often a need to
PSEUDO INPUT VOLTAGE RANGE (V)

2 RANGE
perform the single-ended-to-differential conversion.
0 This single-ended-to-differential conversion can be performed
using an op amp pair. Typical connection diagrams for an op
–2
±10V
amp pair are shown in Figure 42 and Figure 43. In Figure 42,
±2.5V
RANGE the common-mode signal is applied to the noninverting input
–4 ±10V
RANGE
RANGE of the second amplifier.
1.5kΩ
0V TO +10V 0V TO +10V
–6 RANGE RANGE
VCC = 3V 3kΩ
VIN
VREF = 2.5V
04864-040

–8 V+
±16.5V VDD/VSS ±12V VDD/VSS

Figure 41. Pseudo Input Range with VCC = 3 V 1.5kΩ

1.5kΩ

DRIVER AMPLIFIER CHOICE 1.5kΩ

In applications where the harmonic distortion and signal-to-

V–
noise ratio are critical specifications, the analog input of the VCOM
10kΩ

AD7324 should be driven from a low impedance source. Large

04864-029
20kΩ

source impedances significantly affect the ac performance of the

ADC and can necessitate the use of an input buffer amplifier. Figure 42. Single-Ended-to-Differential Configuration with the AD845

When no amplifier is used to drive the analog input, the source 442Ω

impedance should be limited to low values. The maximum 442Ω AD8021

VIN
source impedance depends on the amount of THD that can be V+
tolerated in the application. The THD increases as the source
impedance increases and performance degrades. Figure 21 and 442Ω

Figure 22 show graphs of the THD vs. the analog input frequency
442Ω
for various source impedances. Depending on the input range 442Ω
and analog input configuration selected, the AD7324 can
handle source impedances of up to 4.7 kΩ before the THD
442Ω

starts to degrade. V–

Due to the programmable nature of the analog inputs on the AD8021

04864-030

100Ω
AD7324, the choice of op amp used to drive the inputs is a
function of the particular application and depends on the input Figure 43. Single-Ended-to-Differential Configuration with the AD8021
configuration and the analog input voltage ranges selected.

Rev. B | Page 21 of 36
AD7324 Data Sheet

REGISTERS
The AD7324 has three programmable registers, the control register, the sequence register, and the range register. These registers are write-
only registers.
ADDRESSING REGISTERS
A serial transfer on the AD7324 consists of 16 SCLK cycles. The three MSBs on the DIN line during the 16 SCLK transfer are decoded to
determine which register is addressed. The three MSBs consist of the write bit, the Register Select 1 bit, and the Register Select 2 bit. The
register select bits are used to determine which of the three on-board registers is selected. The write bit determines if the data on the DIN
line following the register select bits loads into the addressed register. If the write bit is 1, the bits load into the register addressed by the
register select bits. If the write bit is 0, the data on the DIN line does not load into any register.
Combinations of the write bit, the Register Select 1 bit, and the Register Select 2 bit other than those specified in Table 8 access registers
for Analog Devices internal use only. Do not access these registers, as doing so may lead to unspecified operation of the device.

Table 8. Decoding Register Select Bits and Write Bit

Write Register Select 1 Register Select 2 Comment
0 0 0 Data on the DIN line during this serial transfer is ignored.
1 0 0 This combination selects the control register. The subsequent 12 bits are loaded into
the control register.
1 0 1 This combination selects the range register. The subsequent 8 bits are loaded into the
range register.
1 1 1 This combination selects the sequence register. The subsequent 4 bits are loaded into
the sequence register.

CONTROL REGISTER
The control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. The
control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7324 configuration for the next
conversion. If the sequence register is being used, data should be loaded into the control register after the range register and the sequence
register have been initialized. The bit functions of the control register are shown in Table 9 (the power-up status of all bits is 0).
MSB LSB
15 14 13 12 11 10 9 8 7 6 5 1 3 2 1 0
Write Register Register ZERO ADD1 ADD0 Mode 1 Mode 0 PM1 PM0 Coding Ref Seq1 Seq2 ZERO 0
Select 1 Select 2

Table 9. Control Register Details

Bit Mnemonic Description
12, 1 ZERO A 0 must be written to this bit to ensure correct operation of the device.
11, 10 ADD1, ADD0 These two channel address bits are used to select the analog input channel for the next conversion if the
sequencer is not being used. If the sequencer is being used, the two channel address bits are used to
select the final channel in a consecutive sequence.
9, 8 Mode 1, Mode 0 These two mode bits are used to select the configuration of the four analog input pins, VIN0 to VIN3. These
pins are used in conjunction with the channel address bits. On the AD7324, the analog inputs can be
configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or
three pseudo differential inputs (see Table 10).
7, 6 PM1, PM0 The power management bits are used to select different power mode options on the AD7324 (see Table 11).
5 Coding This bit is used to select the type of output coding the AD7324 uses for the next conversion result. If
coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary.
When operating in sequence mode, the output coding for each channel is the value written to the coding
bit during the last write to the control register.
4 Ref The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is
enabled and used for the next conversion, and the internal reference is disabled. If Ref = 1, the internal
reference is used for the next conversion. When operating in sequence mode, the reference used for each
channel is the value written to the Ref bit during the last write to the control register.
3, 2 Seq1, Seq2 The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12).

Rev. B | Page 22 of 36
Data Sheet AD7324
The four analog input channels can be configured as three pseudo differential analog inputs, two pseudo differential inputs, two true
differential input pairs, or four single-ended analog inputs.

Table 10. Analog Input Configuration Selection

Mode 1 = 1, Mode 0 = 1 Mode 1 = 1, Mode 0 = 0 Mode 1 = 0, Mode 0 =1 Mode 1 = 0, Mode 0 = 0
Channel Address Bits 3 Pseudo Differential Inputs 2 Fully Differential Inputs 2 Pseudo Differential Inputs 4 Single-Ended Inputs
ADD1 ADD0 VIN+ VIN− VIN+ VIN− VIN+ VIN− VIN+ VIN−
0 0 VIN0 VIN3 VIN0 VIN1 VIN0 VIN1 VIN0 AGND
0 1 VIN1 VIN3 VIN0 VIN1 VIN0 VIN1 VIN1 AGND
1 0 VIN2 VIN3 VIN2 VIN3 VIN2 VIN3 VIN2 AGND
1 1 Not a valid selection VIN2 VIN3 VIN2 VIN3 VIN3 AGND

Table 11. Power Mode Selection

PM1 PM0 Description
1 1 Full Shutdown Mode. In this mode, all internal circuitry on the AD7324 is powered down. Information in the control register
is retained when the AD7324 is in full shutdown mode.
1 0 Autoshutdown Mode. The AD7324 enters autoshutdown on the 15th SCLK rising edge when the control register is updated.
All internal circuitry is powered down in autoshutdown.
0 1 Autostandby Mode. In this mode, all internal circuitry is powered down excluding the internal reference. The AD7324 enters
autostandby mode on the 15th SCLK rising edge after the control register is updated.
0 0 Normal Mode. All internal circuitry is powered up at all times.

Table 12. Sequencer Selection

Seq1 Seq2 Sequence Type
0 0 The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
0 1 Uses sequence of channels that were previously programmed in the sequence register for conversion. The AD7324 starts
converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted, the
AD7324 keeps converting the sequence. The range for each channel defaults to the range previously written into the
range register.
1 0 Used in conjunction with the channel address bits in the control register. This allows continuous conversions on a
consecutive sequence of channels, from Channel 0 up to and including a final channel selected by the channel address bits
in the control register. The range for each channel defaults to the range previously written into the range register.
1 1 The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.

SEQUENCE REGISTER
The sequence register on the AD7324 is a 4-bit, write-only register. Each of the four analog input channels has one corresponding bit in
the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.
MSB LSB
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Write Register Select 1 Register Select 2 VIN0 VIN1 VIN2 VIN3 0 0 0 0 0 0 0 0 0

Rev. B | Page 23 of 36
AD7324 Data Sheet
RANGE REGISTER
The range register is used to select one analog input range per analog input channel. It is an 8-bit, write-only register with two dedicated
range bits for each of the analog input channels from Channel 0 to Channel 3. There are four analog input ranges, ±10 V, ±5 V, ±2.5 V, and
0 V to +10 V. A write to the range register is selected by setting the write bit to 1 and the register select bits to 0 and 1. After the initial write to
the range register occurs, each time an analog input is selected, the AD7324 automatically configures the analog input to the appropriate
range, as indicated by the range register. The ±10 V input range is selected by default on each analog input channel (see Table 13).
MSB LSB
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Write Register Select 1 Register Select 2 VIN0A VIN0B VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B 0 0 0 0 0

Table 13. Range Selection

VINxA VINxB Description
0 0 This combination selects the ±10 V input range on VINx.
0 1 This combination selects the ±5 V input range on VINx.
1 0 This combination selects the ±2.5 V input range on VINx.
1 1 This combination selects the 0 V to +10 V input range on VINx.

Rev. B | Page 24 of 36
Data Sheet AD7324

SEQUENCER OPERATION

POWER ON.

CS

DIN: WRITE TO RANGE REGISTER TO SELECT THE RANGE

FOR EACH ANALOG INPUT CHANNEL.

DOUT: CONVERSION RESULT FROM CHANNEL 0, ±10V

RANGE, SINGLE-ENDED MODE.

CS

DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE

ANALOG INPUT CHANNELS TO BE INCLUDED IN
THE SEQUENCE.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER.

CS

DIN: WRITE TO CONTROL REGISTER TO START THE

SEQUENCE, Seq1 = 0, Seq2 = 1.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER.

CS

DIN: TIE DIN LOW/WRITE BIT = 0TO CONTINUE TO CONVERT

THROUGH THE SEQUENCE OF CHANNELS.
CS
DOUT: CONVERSION RESULT FROM FIRST CHANNEL IN
THE SEQUENCE. DIN TIED LOW/WRITE BIT = 0.
DIN: WRITE TO CONTROL
REGISTER TO STOP THE
SEQUENCE, Seq1 = 0, Seq2 = 0. CONTINUOUSLY CONVERT
STOPPING
A SEQUENCE. ON THE SELECTED SEQUENCE
DOUT: CONVERSION RESULT OF CHANNELS.
FROM CHANNEL IN SEQUENCE.

SELECTING A NEW SEQUENCE.

CS

DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE

NEW SEQUENCE.

DOUT: CONVERSION RESULT FROM CHANNEL X IN

THE FIRST SEQUENCE.

Figure 44. Programmable Sequence Flowchart 04864-031

The AD7324 can be configured to automatically cycle through This initial serial transfer is only necessary if input ranges other
a number of selected channels using the on-chip sequence than the default ranges are required. After the analog input ranges
register with the Seq1 bit and the Seq2 bit in the control register. are configured, a write to the sequence register is necessary to
Figure 44 shows how to program the AD7324 register to operate in select the channels to be included in the sequence. Once the
sequence mode. channels for the sequence have been selected, the sequence can
After power-up, all of the three on-chip registers contain default be initiated by writing to the control register and setting Seq1 to
values. Each analog input has a default input range of ±10 V. If 0 and Seq2 to 1. The AD7324 continues to convert the selected
different analog input ranges are required, a write to the range sequence without interruption provided that the sequence register
register is required. This is shown in the first serial transfer of remains unchanged, and Seq1 = 0 and Seq2 = 1 in the control
Figure 44. register.

Rev. B | Page 25 of 36
AD7324 Data Sheet
If a change to the range register is required during a sequence, it Once the control register is configured to operate the AD7324
is necessary to first stop the sequence by writing to the control in this mode, the DIN line can be held low, or the write bit can
register and setting Seq1 to 0 and Seq2 to 0. Next, the write to be set to 0. To return to traditional multichannel operation, a
the range register should be completed to change the required write to the control register to set Seq1 to 0 and Seq2 to 0 is
range. The previously selected sequence should then be initiated necessary.
again by writing to the control register and setting Seq1 to 0 and When the Seq1 and Seq2 are both set to 0, or when both are set
Seq2 to 1. The ADC converts on the first channel in the sequence. to 1, the AD7324 is configured to operate in traditional multi-
The AD7324 can be configured to convert a sequence of channel mode, where a write to Channel Address Bit ADD1 to
consecutive channels (see Figure 45). This sequence begins by Bit ADD0 in the control register selects the next channel for
converting on Channel 0 and ends with a final channel as conversion.
selected by Bit ADD1 to Bit ADD0 in the control register. In
this configuration, there is no need for a write to the sequence
register. To operate the AD7324 in this mode, set Seq1 to 1 and
Seq2 to 0 in the control register, and then select the final channel
in the sequence by programming Bit ADD1 to Bit ADD0 in the
control register.

POWER ON.

CS

DIN: WRITE TO RANGE REGISTER TO SELECT THE RANGE

FOR ANALOG INPUT CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 0, ±10V

RANGE, SINGLE-ENDED MODE.

CS

DIN: WRITE TO CONTROL REGISTER TO SELECT THE FINAL

CHANNEL IN THE CONSECUTIVE SEQUENCE, SET Seq1 = 1
AND Seq2 = 0. SELECT OUTPUT CODING FOR SEQUENCE.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

RANGE SELECTED IN RANGE REGISTER,
SINGLE-ENDED MODE.

CS

DIN: WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE TO

CONVERT THROUGH THE SEQUENCE OF
CONSECUTIVE CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

RANGE SELECTED IN RANGE REGISTER.

CS

DIN: WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE

THROUGH SEQUENCE OF CONSECUTIVE CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 1,

RANGE SELECTED IN RANGE REGISTER. DIN TIED LOW/WRITE BIT = 0.

CONTINUOUSLY CONVERT
STOPPING ON CONSECUTIVE SEQUENCE
A SEQUENCE. OF CHANNELS.

CS

DIN: WRITE TO CONTROL

REGISTER TO STOP THE
SEQUENCE, Seq1 = 0, Seq2 = 0.
04864-032

DOUT: CONVERSION RESULT

FROM CHANNEL IN SEQUENCE.

Figure 45. Flowchart for Consecutive Sequence of Channels

Rev. B | Page 26 of 36
Data Sheet AD7324
REFERENCE to set the Ref bit to 1. During the control register write, the
conversion result from the first initial conversion is invalid. The
The AD7324 can operate with either the internal 2.5 V on-chip reference buffer requires 500 µs to power up and charge the
reference or an externally applied reference. The internal reference 680 nF decoupling capacitor during the power-up time.
is selected by setting the Ref bit in the control register to 1. On
power-up, the Ref bit is 0, selecting the external reference for the The AD7324 is specified for a 2.5 V to 3 V reference range.
AD7324 conversion. Suitable reference sources for the AD7324 When a 3 V reference is selected, the ranges are ±12 V, ±6 V,
include AD780, AD1582, ADR431, REF193, and ADR391. ±3 V, and 0 V to +12 V. For these ranges, the VDD and VSS supply
must be equal to or greater than the maximum analog input
The internal reference circuitry consists of a 2.5 V band gap range selected, see Table 6.
reference and a reference buffer. When operating the AD7324
in internal reference mode, the 2.5 V internal reference is available VDRIVE
at the REFIN/OUT pin, which should be decoupled to AGND The AD7324 has a VDRIVE feature to control the voltage at which
using a 680 nF capacitor. It is recommended that the internal the serial interface operates. VDRIVE allows the ADC to easily
reference be buffered before applying it elsewhere in the system. interface to both 3 V and 5 V processors. For example, if the
The internal reference is capable of sourcing up to 90 μA. AD7324 is operated with a VCC of 5 V, the VDRIVE pin can be
On power-up, if the internal reference operation is required for powered from a 3 V supply. This allows the AD7324 to accept
the ADC conversion, a write to the control register is necessary large bipolar input signals with low voltage digital processing.

Rev. B | Page 27 of 36
AD7324 Data Sheet

MODES OF OPERATION
The AD7324 has several modes of operation that are designed The AD7324 remains fully powered up at the end of the
to provide flexible power management options. These options conversion if both PM1 and PM0 contain 0 in the control
can be chosen to optimize the power dissipation/throughput register.
rate ratio for different application requirements. The mode of To complete the conversion and access the conversion result
operation of the AD7324 is controlled by the power manage- 16 serial clock cycles are required. At the end of the conversion,
ment bits, Bit PM1 and Bit PM0, in the control register as shown CS can idle either high or low until the next conversion.
in Table 11. The default mode is normal mode, where all internal
circuitry is fully powered up. Once the data transfer is complete, another conversion can be
initiated after the quiet time, tQUIET, has elapsed.
NORMAL MODE
FULL SHUTDOWN MODE
(PM1 = PM0 = 0)
(PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate performance,
with the AD7324 being fully powered up at all times. Figure 46 In this mode, all internal circuitry on the AD7324 is powered
shows the general operation of the AD7324 in normal mode. down. The part retains information in the registers during full
shutdown. The AD7324 remains in full shutdown mode until
The conversion is initiated on the falling edge of CS, and the the power management bits, Bit PM1 and Bit PM0, in the
track-and-hold enters hold mode as described in the Serial control register are changed.
Interface section. Data on the DIN line during the 16 SCLK
transfer is loaded into one of the on-chip registers if the write A write to the control register with PM1 = 1 and PM0 = 1 places
bit is set. The register is selected by programming the register the part into full shutdown mode. The AD7324 enters full shut-
select bits (see Figure 46). down mode on the 15th SCLK rising edge once the control register
is updated.
CS
If a write to the control register occurs while the part is in full
1 16
shutdown mode with the power management bits, Bit PM1 and
SCLK
Bit PM0, set to 0 (normal mode), the part begins to power up
LEADING ZERO, 2 CHANNEL I.D. BITS, SIGN BIT + on the 15th SCLK rising edge once the control register is
DOUT
CONVERSION RESULT
updated. Figure 47 shows how the AD7324 is configured to exit
04864-035

DIN DATA INTO CONTROL/SEQUENCE/RANGE REGISTER full shutdown mode. To ensure the AD7324 is fully powered up,
tPOWER-UP for full shutdown mode should elapse before the next
Figure 46. Normal Mode
CS falling edge

THE PART IS FULLY POWERED UP

ONCE tPOWER-UP HAS ELAPSED
PART IS IN FULL
SHUTDOWN
PART BEGINS TO POWER UP ON THE 15TH
SCLK RISING EDGE AS PM1 = PM0 = 0 tPOWER-UP
CS

1 16 1 16

SCLK

SDATA INVALID DATA CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DIN DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER

04864-041

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS, TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
PM1 = 0, PM0 = 0 IN CONTROL REGISTER

Figure 47. Exiting Full Shutdown Mode

Rev. B | Page 28 of 36
Data Sheet AD7324
AUTOSHUTDOWN MODE As is the case with the autoshutdown mode, the AD7324 enters
(PM1 = 1, PM0 = 0) standby on the 15th SCLK rising edge once the control register is
updated (see Figure 48). The part retains information in the
Once the autoshutdown mode is selected, the AD7324 auto- registers during standby. Once in autostandby mode, the CS
matically enters shutdown on the 15th SCLK rising edge. In signal must remain low to keep the part in autostandby mode.
autoshutdown mode, all internal circuitry is powered down. The
The AD7324 remains in standby until it receives a CS rising
AD7324 retains information in the registers during autoshutdown.
edge. The ADC begins to power up on the CS rising edge. On
The track-and-hold is in hold mode during autoshutdown. On
the CS rising edge, the track-and-hold, which was in hold mode
the rising CS edge, the track-and-hold, which was in hold during
while the part was in standby, returns to track. The power-up
shutdown, returns to track as the AD7324 begins to power up.
time from standby is 700 ns.
The power-up from autoshutdown is 500 µs.
The user should ensure that 700 ns have elapsed before bringing
When the control register is programmed to transition to
CS low to attempt a valid conversion. Once this valid conversion
autoshutdown mode, it does so on the 15th SCLK rising edge.
Figure 48 shows the part entering autoshutdown mode. Once in is complete, the AD7324 again returns to standby on the 15th SCLK
autoshutdown mode, the CS signal must remain low to keep the rising edge. The CS signal must remain low to keep the part in
part in autoshutdown mode. The AD7324 automatically begins to standby mode.
power up on the CS rising edge. The tPOWER-UP for autoshutdown Figure 48 shows the part entering autoshutdown mode. The
is required before a valid conversion, initiated by bringing the sequence of events is the same when entering autostandby mode.
CS signal low, can take place. Once this valid conversion is In Figure 48, the power management bits are configured for
complete, the AD7324 powers down again on the 15th SCLK autoshutdown. For autostandby mode, the power management
rising edge. The CS signal must remain low again to keep the bits, PM1 and PM0, should be set to 0 and 1, respectively.
part in autoshutdown mode.
AUTOSTANDBY MODE
(PM1 = 0, PM0 =1)
In autostandby mode, portions of the AD7324 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to
autoshutdown, but allows the AD7324 to power up much faster.
This allows faster throughput rates to be achieved.

PART BEGINS TO POWER THE PART IS FULLY POWERED UP

UP ON CS RISING EDGE ONCE tPOWER-UP HAS ELAPSED

PART ENTERS SHUTDOWN MODE tPOWER-UP

ON THE 15TH RISING SCLK EDGE
CS AS PM1 = 1, PM0 = 0

1 15 16 1 15 16

SCLK

SDATA VALID DATA VALID DATA

DIN DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER

04864-042

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,

PM1 = 1, PM0 = 0

Figure 48. Entering Autoshutdown/Autostandby Mode

Rev. B | Page 29 of 36
AD7324 Data Sheet
20
POWER VS. THROUGHPUT RATE
18
The power consumption of the AD7324 varies with throughput
16
rate. The static power consumed by the AD7324 is very low, and VARIABLE SCLK

AVERAGE POWER (mW)

a significant power savings can be achieved as the throughput 14
20MHz SCLK
rate is reduced. Figure 49 and Figure 50 shows the power vs. 12

throughput rate for the AD7324 at a VCC of 3 V and 5 V, 10

respectively. Both plots clearly show that the average power 8
consumed by the AD7324 is greatly reduced as the sample
6
frequency is reduced. This is true whether a fixed SCLK value is
4
used or if it is scaled with the sampling frequency. Figure 49 and VCC = 5V
VDD/VSS = ±12V
Figure 50 show the power consumption when operating in 2 TA = 25°C
INTERNAL REFERENCE
normal mode for a fixed 20 MHz SCLK and a variable SCLK 0

04864-053
0 100 200 300 400 500 600 700 800 900 1000
that scales with the sampling frequency. THROUGHPUT RATE (kHz)
12
Figure 50. Power vs. Throughput Rate with 5 V VCC

10
AVERAGE POWER (mW)

20MHz SCLK
8
VARIABLE SCLK

2 VCC = 3V
VDD/VSS = ±12V
TA = 25°C
INTERNAL REFERENCE
0
04864-052

0 100 200 300 400 500 600 700 800 900 1000 1100
THROUGHPUT RATE (kSPS)

Figure 49. Power vs. Throughput Rate with 3 V VCC

Rev. B | Page 30 of 36
Data Sheet AD7324

SERIAL INTERFACE
Figure 51 shows the timing diagram for the serial interface of Data is clocked into the AD7324 on the SCLK falling edge. The
the AD7324. The serial clock applied to the SCLK pin provides 3 MSBs on the DIN line are decoded to select which register is
the conversion clock and controls the transfer of information to being addressed. The control register is a 12-bit register. If the
and from the AD7324 during a conversion. control register is addressed by the 3 MSBs, the data on the DIN
The CS signal initiates the data transfer and the conversion line is loaded into the control on the 15th SCLK rising edge. If the
sequence register or the range register is addressed, the data on
process. The falling edge of CS puts the track-and-hold into hold
the DIN line is loaded into the addressed register on the 11th SCLK
mode and takes the bus out of three-state. Then the analog input
falling edge.
signal is sampled. Once the conversion is initiated, it requires
16 SCLK cycles to complete. Conversion data is clocked out of the AD7324 on each SCLK
falling edge. Data on the DOUT line consists of a leading ZERO
The track-and-hold goes back into track mode on the 14 SCLK th
bit, two channel identifier bits, a sign bit, and a 12-bit conversion
rising edge. On the 16th SCLK falling edge, the DOUT line returns
result. The channel identifier bits are used to indicate which
to three-state. If the rising edge of CS occurs before 16 SCLK cycles
channel corresponds to the conversion result. The leading ZERO
have elapsed, the conversion is terminated, and the DOUT line
bit is clocked out on the CS falling edge, and the first channel
returns to three-state. Depending on where the CS signal is brought
identifier bit is clocked out on the first SCLK falling edge.
high, the addressed register may be updated.

t1
CS
tCONVERT
t2 t6
SCLK 1 2 3 4 5 13 14 15 16
2 IDENTIFICATION BITS t7 t5 t8
t3 t4 tQUIET
DOUT ADD1 ADD0 SIGN DB11 DB10 DB2 DB1 DB0
THREE- ZERO t10 THREE-STATE
STATE t9

04864-036
WRITE REG REG MSB LSB DON’T
DIN SEL1 SEL2 CARE

Figure 51. Serial Interface Timing Diagram (Control Register Write)

Rev. B | Page 31 of 36
AD7324 Data Sheet

MICROPROCESSOR INTERFACING
The serial interface on the AD7324 allows the part to be directly The frequency of the serial clock is set in the SCLKDIV register.
connected to a range of different microprocessors. This section When the instruction to transmit with TFS is given (AX0 = TX0),
explains how to interface the AD7324 with some common the state of the serial clock is checked. The DSP waits until the
microcontroller and DSP serial interface protocols. SCLK has gone high, low, and high again before starting the
transmission. If the timer and SCLK are chosen, so that the
AD7324 TO ADSP-21xx
instruction to transmit occurs on or near the rising edge of SCLK,
The ADSP-21xx family of DSPs interface directly to the AD7324 data can be transmitted immediately or at the next clock edge.
without requiring glue logic. The VDRIVE pin of the AD7324 takes
the same supply voltage as that of the ADSP-21xx. This allows For example, the ADSP-2111 has a master clock frequency of
the ADC to operate at a higher supply voltage than its serial 16 MHz. If the SCLKDIV register is loaded with the value 3, an
interface. The SPORT0 on the ADSP-21xx should be configured SCLK of 2 MHz is obtained, and eight master clock periods elapse
as shown in Table 14. for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and,
Table 14. SPORT0 Control Register Setup subsequently, between transmit instructions. This situation leads
Setting Description to nonequidistant sampling because the transmit instruction
TFSW = RFSW = 1 Alternative framing occurs on an SCLK edge. If the number of SCLKs between
INVRFS = INVTFS = 1 Active low frame signal interrupts is an integer of N, equidistant sampling is implemented
DTYPE = 00 Right justify data by the DSP.
SLEN = 1111 16-bit data word AD7324 TO ADSP-BF53x
ISCLK = 1 Internal serial clock
The ADSP-BF53x family of DSPs interface directly to the
TFSR = RFSR = 1 Frame every word
AD7324 without requiring glue logic, as shown in Figure 53.
IRFS = 0
The SPORT0 Receive Configuration 1 register should be set up
ITFS = 1
as outlined in Table 15.
The connection diagram is shown in Figure 52. The ADSP-21xx
AD73241 ADSP-BF53x1
has TFS0 and RFS0 tied together. TFS0 is set as an output, and
RFS0 is set as an input. The DSP operates in alternative framing SCLK RSCLK0

mode, and the SPORT0 control register is set up as described in CS RFS0

Table 14. The frame synchronization signal generated on the
TFS is tied to CS and, as with all signal processing applications, DIN DT0

requires equidistant sampling. However, as in this example, the DOUT DR0

timer interrupt is used to control the sampling rate of the ADC, VDRIVE

and under certain conditions, equidistant sampling cannot be

achieved.

04864-038
VDD

AD73241 ADSP-21xx1 1ADDITIONAL PINS OMITTED FOR CLARITY.

SCLK SCLK0 Figure 53. Interfacing the AD7324 to the ADSP-BF53x

CS TFS0 Table 15. SPORT0 Receive Configuration 1 Register

RFS0
Setting Description
DIN DT0
RCKFE = 1 Sample data with falling edge of RSCLK
DOUT DR0 LRFS = 1 Active low frame signal
VDRIVE
RFSR = 1 Frame every word
IRFS = 1 Internal RFS used
RLSBIT = 0 Receive MSB first
04864-037

VDD
1ADDITIONAL PINS OMITTED FOR CLARITY.
RDTYPE = 00 Zero fill
IRCLK = 1 Internal receive clock
Figure 52. Interfacing the AD7324 to the ADSP-21xx
RSPEN = 1 Receive enable
The timer registers are loaded with a value that provides an SLEN = 1111 16-bit data-word
interrupt at the required sampling interval. When an interrupt TFSR = RFSR = 1
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, therefore, the
reading of data.

Rev. B | Page 32 of 36
Data Sheet AD7324

APPLICATION HINTS
LAYOUT AND GROUNDING POWER SUPPLY CONFIGURATION
The printed circuit board that houses the AD7324 should be It is recommended that Schottky diodes be placed in series with
designed so that the analog and digital sections are confined to the AD7324 VDD and VSS supply signals. Figure 54 shows this
certain areas of the board. This design facilitates the use of ground Schottky diode configuration. BAT43 Schottky diodes are used.
planes that can easily be separated. V+ 3V/5V

To provide optimum shielding for ground planes, a minimum

etch technique is generally best. All AGND pins on the AD7324 VDD VCC
should be connected to the AGND plane. Digital and analog
VIN0 CS
ground pins should be joined in only one place. If the AD7324 AD73241
is in a system where multiple devices require an AGND and VIN1 SCLK
DGND connection, the connection should still be made at only
VIN2 DOUT
one point. A star point should be established as close as possible
to the ground pins on the AD7324. VIN3 DIN
VSS
Good connections should be made to the power and ground
planes. This can be done with a single via or multiple vias for
each supply and ground pin.

04864-056
V–

Avoid running digital lines under the AD7324 device because 1ADDITIONAL PINS OMITTED FOR CLARITY.

this couples noise onto the die. However, the analog ground Figure 54. Schottky Diode Connection
plane should be allowed to run under the AD7324 to avoid
In an application where non-symmetrical VDD and VSS supplies
noise coupling. The power supply lines to the AD7324 device
are being used, adhere to the following guidelines. Table 16
should use as large a trace as possible to provide low impedance
outlines the VSS supply range that can be used for particular VDD
paths and reduce the effects of glitches on the power supply line.
voltages when non-symmetrical supplies are required. When
To avoid radiating noise to other sections of the board, compo- operating the AD7324 with low VDD and VSS voltages, it is
nents, such as clocks, with fast switching signals should be shielded recommended that these supplies be symmetrical.
with digital ground and never run near the analog inputs. Avoid
crossover of digital and analog signals. To reduce the effects of Table 16. Non-Symmetrical VDD and VSS Requirements
feedthrough within the board, traces should be run at right angles VDD Typical VSS Range
to each other. A microstrip technique is the best method, but 5V −5 V to −5.5 V
its use may not be possible with a double-sided board. In this 6V −5 V to −8.5 V
technique, the component side of the board is dedicated to ground 7V −5 V to −11.5 V
planes, and signals are placed on the other side. 8V −5 V to −15 V
9V −5 V to −16.5 V
Good decoupling is also important. All analog supplies should
10 V to 16.5 V −5 V to −16.5 V
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to AGND. To achieve the best results from
these decoupling components, they must be placed as close as For the 0 to 4 × VREF range, VSS can be tied to AGND as per
possible to the device, ideally right up against the device. The minimum supply recommendations outlined in Table 6.
0.1 µF capacitors should have a low effective series resistance
(ESR) and low effective series inductance (ESI), such as is
typical of common ceramic and surface mount types of
capacitors. These low ESR, low ESI capacitors provide a low
impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.

Rev. B | Page 33 of 36
AD7324 Data Sheet

OUTLINE DIMENSIONS
5.10
5.00
4.90

16 9

4.50
6.40
4.40 BSC
4.30
1 8

PIN 1
1.20
MAX
0.15 0.20
0.05 0.09 0.75
0.30 8° 0.60
0.65 0.19 0° 0.45
SEATING
BSC PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 55. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)
Dimensions show in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD7324BRUZ −40°C to +85°C 16-Lead TSSOP RU-16
AD7324BRUZ-REEL −40°C to +85°C 16-Lead TSSOP RU-16
AD7324BRUZ-REEL7 −40°C to +85°C 16-Lead TSSOP RU-16
1
Z = RoHS Compliant Part.

Rev. B | Page 34 of 36
Data Sheet AD7324

NOTES

Rev. B | Page 35 of 36
AD7324 Data Sheet

NOTES

©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04864-0-12/13(B)

Rev. B | Page 36 of 36