First International IEEE-AESS Conference in Europe about Space and Satellite Telecommunications,

Rome-Italy-October 2-3-4-5/2012

A Low Cost Design of MIL-STD-1553 Devices

Rizwan Hamid Randhawa, Muhammad Imran
Satellite Research & Development Center
Space & Upper Atmosphere Research Commission
Lahore, Pakistan
chaudhary.randhawa@gmail.com, imran_uet@hotmail.com

processor (DSP), a line transceiver, a bus transceiver and

Abstract—This paper suggests a low cost design of MIL-STD- transformers.
1553 bus terminal devices used in various Avionics and
Aerospace applications. The design involves the implementation The main purpose of this work is to reduce the hardware
of MIL-STD-1553 bus core functionality on Digital Signal and cost of the design of bus devices eliminating the need for
Processor (DSP) having on chip Multichannel Buffered Serial a dedicated 1553A/B Advanced Communication Engine
Port (MCBSP). The DSP acts as a host processor and MIL-STD- (ACE) like BU-61580) or bus core IC (HI-15530), control
1553 bus compliant packet generator. Device specific software logic and parallel I/O lines engagement. The same DSP acts as
and the hardware design technique adopted to interface MCBSP a host processor which can be reprogrammed according to
with bus transceiver have also been discussed. With the MIL-STD-1553 multi protocol requirement i.e. Bus Terminal
successful implementation of the idea the terminal device host (BT), Bus Monitor (BM) or Bus Controller (BC).
processor (DSP) could be used for performing all the necessary
functions of 1553A/B protocol eradicating the need of a dedicated II. MIL-STD-1553 BUS CORES
and an expensive bus core IC, parallel I/O lines and different
control logic ICs. The work proves to be a low cost and reduced BU-61580 chip from Data Device Corporation’s (DDC)
hardware design for 1553A/B based devices in Avionics and ACE series integrated BC/RT/BM hybrids shown in Fig 1,
Aerospace systems. provides interface between microprocessor and MIL-STD-
1553 bus in terminal devices. It performs on chip BC/RT/BM
Keywords: 1553A/B, DSP, MCBSP, HI-15530, BU-61580
multiprotocol logic, packet formation, Manchester-II
I. INTRODUCTION encoding/decoding, error detection, sync generation, memory
MIL-STD-1553 is a military standard used for
communication within air-borne on board data handling sub-
systems. MIL-STD-1553 has been in operation by various
military and commercial aircraft for last four decades due to
its robust performance, high level of reliability and fault
tolerance in harsh environments which make it a perfect
candidate for military, avionics and aerospace systems.
In recent past, the conventional design adopted for MIL-
STD-1553 bus terminal devices involved a host processor, a
MIL-STD-1553 encoder/decoder, a bus transceiver and
transformers. These days, the design is being implemented
using a single MIL-STD-1553 core and a host processor. The
MIL-STD-1553 core has on-chip MIL-STD-1553
encoder/decoder, transceiver and transformers. The single chip
solution proves to be a very costly choice for design
implementation.
Keeping this constraint in view, a design of MIL-STD-
1553 terminal devices is being introduced in this paper
according to which the functionality of MIL-STD-1553
encoder/decoder has been implemented on Digital Signal
Processor (DSP) which also acts as a Host Processor in the Figure 1: BU61580 from DDC
design. The MIL-STD-1553 encoder/decoder functionality has
been implemented using DSP’s Multichannel Buffered Serial management, and transceiver line drive. With host processor,
Port (MCBSP) and Enhanced Direct Memory Access (EDMA) it has a parallel I/O lines interface for data exchange.
Controller. The suggested hardware design involves the host

978-1-4673-4688-7/12/$31.00 ©2012 IEEE

 C. MIL-STD-1553 Transceiver
The design of MIL-STD-1553 devices involves bus drive
interface for which bus transceiver module is used. For this
purpose, Holt Integrated Circuits’ HI-1573 has been used
which is a 3.3V Monolithic Dual Transceiver IC. The
transmitter section takes complementary CMOS/ TTL data
and converts it to differential voltage levels suitable for
driving the bus isolation transformer while the receiver section
converts the 1553 bus data to complementary CMOS/TTL
data.

Figure 2: HI-15530 from Holt Integrated Circuits Inc.

Similarly, another MIL-STD-1553 compliant bus core IC

HI-15530 from Holt Integrated Circuits Inc. shown in Fig 2 is
used to interface host processor with 1553A/B bus. It has a
serial interface with host processor, packet formation, error
detection, an on chip Manchester-II encoder/decoder and sync
generator/detector. It takes single line serial TTL data from
host processor as input on transmit channel and converts it
into a differential output which is fed to a MIL-STD-1553 bus
transceiver. During receive operation, it takes differential data
from line receiver and converts back into single line serial
TTL data on receive channel which is fed to the host
processor.

III. HARDWARE COMPONENTS

Figure 3: Hardware Block Diagram
The proposed hardware design involves a host processor, a
MIL-STD-1553 bus transceiver and a line transceiver for IV. HARDWARE DESIGN
interface between the host processor and bus transceiver.
Fig.3 demonstrates the interface between DSP’s MCBSP
A. Host Processor (DSP) and HI-1573 through a complementary line transceiver. Data
TMS320C6713 DSP (PYP package) from Texas Transmit Pin of MCBSP is connected to data input pin of line
Instruments has been used as a host processor in the design of transceiver which converts it into a 3.3V complementary
bus devices (BC/RT/BM). It’s a 32-bit floating point processor signaling levels on its Data Out+ and Data Out- pins. These
specialized for digital signal processing operations. It has up output pins are connected to the digital data input non-inverted
to 167MHz clock rate, 1336 MIPS operation, 192K bytes and inverted pins of bus transceiver respectively. Similarly
internal Static RAM (IRAM), 16-Bit External Memory receive channel non-inverted and inverted output pins of bus
Interface (EMIF), Enhanced Direct Memory Access (EDMA) transceiver are connected to Receive In+ and Receive In- pins
Controller, Two Multichannel Buffered Serial Ports of line transceiver which converts the differential level back
(MCBSP), Two 32-Bit General-Purpose Timers, Flexible into single line 3.3V data. This data is fed to Data Receive
Phase-Locked-Loop (PLL) based Clock Generator Module, (DR) and Frame Sync Receive (FSR) pins of DSP. FSR pin
3.3-V I/Os and 1.2-V Internal Core. detects the incoming frame synchronization and triggers the
data receive operation through DR pin [1].
B. Line Transceiver
National Semiconductor’s DS90LV019 has been used as a V. SOFTWARE COMPONENTS
line transceiver to interface the DSP with MIL-STD-1553 The software design can be divided into five parts.
transceiver. The DS90LV019 is designed specifically for the
high speed low power point-to-point interconnects A. Hardware Initializations
applications. The device operates from a single 3.3V or 5.0V First part of the software design involves the hardware
power supply and includes one differential line driver and one initializations like PLL setting, configuration of EDMA
receiver. The driver translates between CMOS/TTL levels parameters and setting MCBSP registers.
(single-ended) to low voltage differential signaling levels.
 generate CPU, EMIF, and peripheral clocks. The peripheral
clock is fed to MCBSP for its operations like internal frame
sync and baud rate generation. EDMA parameters are set
according to the requirements of 8-bit transfers from MCBSP
and IRAM. The parameters of EDMA channel 14 and 15 have
been set to entertain MCBSP Transmit and Receive Events
[1]. The settings of MCBSP registers are the key to generate
MIL-STD-1553 bus compliant packets in DSP. The interrupt
mapped on INT_8 in Interrupt Vector Table (IVT) of DSP is
responsible for informing the CPU about EDMA transfer
completion.
The MCBSP takes half phase of each Manchester-II
Encoded bit as an 8-bit data word. So the whole 20 bits packet
of the MIL-STD-1553 can be divided into 40 elements each of
8-bits. Data copied to IRAM during receive operation is
compressed to 1/8 of the size of data received by MCBSP.
Vote logic is used to detect the correct data reception by
checking 4 middle bits out of 8 bits for each element. Data is
then de-packetized and Manchester-II decoding is applied [2].
Finally the parity error is checked and after validation for a
correct MIL-STD-1553 bus packet, 16-bit data word is saved
to IRAM. Similarly before transmission, reverse operation is
performed; after packet formation, each packet bit is expanded
to 8 times and transmission interrupt is enabled which
activates the EDMA channel 14 to transfer this data to
MCBSP transmit channel.
Figure 4: Software Components and Flow

B. Interrupt Service Routine VII. PACKET GENERATION STRATEGY IN DSP

The second part involves an interrupt service routine which The key task to generate MIL-STD-1553 compliant packet
is called when EDMA transfers data from MCBSP to IRAM in DSP involved the MCBSP registers configuration in a
and from IRAM to MCBSP. specialized way. MIL-STD-1553 packets consist of 16-bit
words (command, data, or status) where each word is
C. Packet Formation transmitted using Manchester-II encoding. During 1MHz
The third part consists of MIL-STD-1553 based packet operation, each bit of the data is transmitted as a 0.5 μs high
formation. It includes Manchester-II encoding/decoding, error and 0.5 μs low for a logical 1 and vice versa for a logical 0.
detection/parity generation and sync pulses formation/ Each word has a 3 μs sync pulse where 1.5 μs high and 1.5 μs
detection. low for command or status words and the opposite for data
words, which cannot occur in the Manchester-II encoding.
D. MCBSP Data Compression/Expansion
The fourth part deals with MCBSP data MCBSP can be configured for transmit and receive element
compression/expansion and vote logic for the received data sizes of 8, 12, 16, 20, 24 and 32 bits. Neither of these values
and data to be transmitted. can be used to generate the MIL-STD-1553 compliant packet.
Although 20 bit element size supported the idea but it was not
E. Multiprotocol Logic possible to generate the middle half bit time high or low for
The fifth part of software design is responsible for MIL- the sync pulses as was required. So MCBSP was configured
STD-1553A/B multiprotocol logic. This part is specific to the for a unit element length of 8 bits. So each 8 bit element of
device type (BC/RT/BM). MCBSP represented a single Manchester-II encoded half
phase of a MIL-STD-1553 packet i.e.0.5μs time period. In this
VI. SOFTWARE FUNCTION way for the whole of the MIL-STD-1553 packet the total
number of elements was set to 40.
Fig 4 demonstrates the software components and flow
diagram of the design. First of all PLL registers are set to
 Figure 5: MIL-STD-1553 Packet Generation Timing Diagram

Fig 5 demonstrates the idea behind the MIL-STD-1553

packet formation in DSP using MCBSP. Here it can be X. CONCLUSION
observed that the baud clock of DSP has been set 16 times the This paper has introduced an inexpensive design for MIL-
data rate of MIL-STD-1553. STD-1553 based devices. The design can be modified and
reprogrammed according to the desired terminal device
VIII. EXPERIMENTAL RESULTS (BC/RT/BM). All the components used can be easily
It is very important to mention here that main objective of available. The design can be upgraded to high speed data bus
this work is to design an integrated and a low cost hardware implementations as required.
for MIL-STD-1553. It was observed through testing that the
performance of the proposed design is comparable to the ACKNOWLEDGMENT
conventional design available. Therefore this work proves to We would like to thank our colleagues at Satellite Research
be a low cost and reduced hardware design for MIL-STD- & Development Center Lahore (SRDC-L), Pakistan, for their
1553 implementation. valuable contribution to this paper.
IX. APPLICATION REFERENCES
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simplicity, robust performance, high level of reliability and USA.
fault tolerance in harsh environments. The applications of [2] Application Report SPRA633B - May 2004 by Texas Instruments.
[3] Michael Hegarty, Principal Marketing Engineer Data Device
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(1553-ACE)”, ILC, Data Device Corporation USA.
1553 has been selected for use in Primary Flight Control [7] Department of Defense Interface Standard for Digital Time Division
System of a commercial aircraft [3]. Command/ Response Multiplex Data Bus, MIL-STD-1553B, Notice 4,
The suggested design can be implemented using Texas 1996. Washington, DC: Department of Defense, 1978.
Instruments’ HiRel (High Reliability) class of Digital Signal [8] High Reliability Guide sgzt008 by Texas Instruments.
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