BU-65178/65179*/61588/61688*/61689* Make sure the next

Card you purchase

MINIATURE ADVANCED has...
®

COMMUNICATION ENGINE
(MINI-ACE) AND MINI-ACE PLUS*
FEATURES
• 5 Volt Only
• Fully Integrated MIL-STD-1553 A/B
STANAG 3838 Compliant Terminals
• One-Square-Inch Package
• Smallest BC/RT/MT In The Industry
• Hardware and Software
Compatible with BU-61580 ACE
Series
• Flexible Processor/Memory
Interface
• Bootable RT* Option
• 4K x 16 or 64K x 16* Shared RAM
• Automatic BC Retries
DESCRIPTION
• Programmable BC Gap Times
The BU-61588 Mini-ACE and BU-61688 Mini-ACE Plus* integrates two • Programmable Illegalization
5-volt-only transceivers, protocol, memory management, processor interface
• Simultaneous RT/Monitor Mode
logic, and 4K x 16, or 64K x 16* words of RAM in a choice of pin grid array
(PGA), quad flat pack or gull lead packages. The Mini-ACE is packaged in a • Operates From 10*/12 /16 / 20* MHz
1.0 square inch, low profile, cofired ceramic multi-chip-module (MCM) pack- Clock
age making it the smallest integrated MIL-STD-1553 BC/RT/MT in the indus-
try.

The Mini-ACE provides full compatibility to DDC’s BU-61580 and BU-65170

Advanced Communication Engine (ACE). As such, the Mini-ACE includes all
the hardware and software architectural features of the ACE.

The Mini-ACE contains internal address latches and bidirectional data buffers
to provide a direct interface to a host processor bus. The memory manage-
ment scheme for RT mode provides three data structures for buffering data.
These structures, combined with the Mini-ACE’s extensive interrupt capabili-
ty, serve to ensure data consistency while off-loading the host processor.

The Mini-ACE Plus* can optionally boot-up as a RT with the Busy bit set for
1760 applications. The Mini-ACE BC mode implements several features
aimed at providing an efficient real-time software interface to the host proces-
sor including automatic retries, programmable intermessage gap times, auto-
matic frame repetition, and flexible interrupt generation.

The advanced architectural features of the Mini-ACE, combined with its small size
and high reliability, make it an ideal choice for demanding military and industrial
processor-to-1553 applications.

FOR MORE INFORMATION CONTACT:

Technical Support:
Data Device Corporation
1-800-DDC-5757 ext. 7771
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com All trademarks are the property of their respective owners.
© 1998, 1999 Data Device Corporation
www.ddc-web.com
Data Device Corporation
4K X 16
TX/RX_A OR
64K X 16
*
SHARED
RAM

CH. A TRANSCEIVER
A

DATA PROCESSOR
DATA BUS BUFFERS D15-D0
TX/RX_A DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT ADDRESS PROCESSOR
TX/RX_B ADDRESS BUS BUFFERS A15-A0 ADDRESS BUS

2
CH. B TRANSCEIVER
B

TX/RX_B TRANSPARENT/BUFFERED, STRBD, SELECT,

RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
PROCESSOR MSB/LSB/DTGRT
AND
RT ADDRESS RTAD4-RTAD0, RTADP MEMORY PROCESSOR
INTERFACE IOEN, READYD
AND
LOGIC MEMORY
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
RT_AD_LAT CONTROL
8/16-BIT/DTREQ, POLARITY_SEL/DTACK

INT INTERRUPT
CLK_IN, REQUEST
MISCELLANEOUS MSTCLR,SSFLAG/EXT_TRG

FIGURE 1. BU-65178/65179*/61588/61688*/61689*

K-04/05-0
BU-65178/65179*/61688*/61689*
 TABLE 1. BU-65178/65179*/61588/61688*/61689* TABLE 1. BU-65178/65179*/61588/61688*/61689*
SPECIFICATIONS SPECIFICATIONS (CONT.)
PARAMETER MIN TYP MAX UNITS PARAMETER MIN TYP MAX UNITS
ABSOLUTE MAXIMUM RATING 1553 MESSAGE TIMING
Supply Voltage Completion of CPU Write (BC
„ Logic +5 V -0.3 6.0 V Start)- to-Start of Next Message 2.5 µs
„ Transceiver +5 V (Note 12) -0.3 7.0 V BC Intermessage Gap (Note 8) 9.5 µs
Logic BC/RT/MT Response Timeout
„ Voltage Input Range -0.3 Vcc+0.3 V (Note 9)
RECEIVER „ 18.5 nominal 17.5 18.5 19.5 µs
Differential Input Resistance 2.5 kohm „ 22.5 nominal 21.5 22.5 23.5 µs
(Notes 1-7) „ 50.5 nominal 49.5 50.5 51.5 µs
Differential Input Capacitance 5 pF „ 128.0 nominal 127 129.5 131 µs
(Notes 1-7) T Response Time (Note 11) 4 7 µs
Threshold Voltage, Transformer 0.20 0.860 Vp-p Transmitter Watchdog Timeout 668 µs
Coupled, Measured on Stub 0 POWER SUPPLY REQUIREMENTS
Common Mode Voltage (Note 7) 10 Vpeak Voltages/Tolerances
TRANSMITTER „ BU-65178/61588X3
Differential Output Voltage • +5 V (Logic) 4.5 5.0 5.5 V
„ Direct Coupled Across 35 Ω, 6 7 9 Vp-p • +5 V (Ch. A, Ch. B) 4.75 5.0 5.25 V
Measured on Bus Current Drain (Total Hybrid)
„ Transformer Coupled Across „ BU-65178/65179/61588X0
70 Ω, Measured on Bus: • +5 V (Logic) 23 100 mA
• Standard Product = – XX0 18 21 27 Vp-p „ BU-65178/65179/61588X3
• 1760 Amplitude Compliant 20 22 27 Vp-p • +5 V (Logic, Ch. A, Ch. B)
Product = – XX2 • Idle 116 160 mA
( Note 13 and Ordering • 25% Transmitter Duty Cycle 222 265 mA
Information – Test Criteria) • 50% Transmitter Duty Cycle 328 370 mA
Output Noise, Differential (Direct 10 mVp-p, • 100% Transmitter Duty Cycle 540 580 mA
Coupled) diff „ BU-61688*/61689X0*
Output Offset Voltage, Transformer -250 150 250 mV • +5 V (Logic) 46 200 mA
Coupled Across 70 ohms „ BU-61688*/61689X3*
Rise/Fall Time 100 300 nsec • +5 V (Logic, Ch. A, Ch. B)
• Idle 116 180 mA
LOGIC
• 25% Transmitter Duty Cycle 217 285 mA
VIH 2.0 V
• 50% Transmitter Duty Cycle 318 390 mA
VIL 0.8 V
• 100% Transmitter Duty Cycle 519 600 mA
IIH (Vcc = 5.5 V, VIN = Vcc) -10 10 µA
IIH (Vcc = 5.5 V, VIN = 2.7 V) POWER DISSIPATION
„ SSFLAG/EXT_TRIG -692 -84 µA Total Hybrid
„ All Other Inputs -346 -42 µA „ BU-65178/65179/61588X0
IIL (Vcc = 5.5 V, VIN = 0.4 V) • +5 V (Logic) 0.115 0.5 W
„ SSFLAG/EXT_TRIG -794 -100 µA „ BU-65178/61588/65179X3
„ All Other Inputs -397 -50 µA • Idle 0.64 0.88 W
VOH (Vcc = 4.5 V, VIH = 2.7 V, 2.4 V • 25% Duty Cycle 0.93 1.11 W
VIL = 0.2 V, IOH = max) • 50% Duty Cycle 1.22 1.33 W
VOL (Vcc = 4.5 V, VIH = 2.7 V, 0.4 V • 100% Duty Cycle 1.81 1.97 W
VIL = 0.2 V, IOL = max) „ BU-61688*/61689X0*
IOL • +5 V (Logic) 0.230 1.0 W
„ DB15-DB0 6.4 mA „ BU-61688*/61689X3*
A15-A0 • Idle 0.64 0.99 W
MEMOE/ADDR_LAT • 25% Duty Cycle 0.93 1.22 W
MEMWR/ZEROWAIT • 50% Duty Cycle 1.22 1.45 W
DTREQ/16/8 • 100% Duty Cycle 1.80 1.90 W
DTACK/POLARITY_SEL Hottest Die
„ INT 3.2 mA „ BU-65178/61588X3/65179X3*/
READYD BU-61688*/61689X3*
IOEN • Idle 0.18 0.28 W
IOH • 25% Duty Cycle 0.42 0.51 W
„ DB15-DB0 -6.4 mA • 50% Duty Cycle 0.66 0.75 W
A15-A0 • 100% Duty Cycle 1.14 1.22 W
MEMOE/ADDR_LAT
MEMWR/ZEROWAIT
DTREQ/16/8
DTACK/POLARITY_SEL * Mini-ACE PLUS with 64K Words of RAM. RAM impact to Power
„ INT -3.2 mA Supply is based on Host Processor activity; subtract 140 mA if Host
READYD is idle.
IOEN
CI (Input Capacitance) 50 pF
CIO (Bi-directional signal input 50 pF
capacitance)

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 Table 1 Notes (Cont.):
TABLE 1. BU-65178/65179*/61588/61688*/61689*
SPECIFICATIONS (CONT.) (8) Typical value for minimum intermessage gap time. Under software
control, may be lengthened to (65,535 µs minus message time), in
PARAMETER MIN TYP MAX UNITS increments of 1 µs.
Frequency (9) Software programmable (4 options). Includes RT-to-RT Timeout (Mid-
„ BU-61588/61688*/65178 Parity of Transmit Command to Mid-Sync of Transmitting RT Status).
• Default Mode 16 MHz (10) For both +5 V logic and transceiver. +5 V for channels A and B.
MHz (11) Measured from mid-parity crossing of Command Word to mid-sync
• Software Programmable Option 12
crossing of RT’s Status Word.
„ BU-61689*
(12) External 10 µF Tantalum and 0.1 µF capacitors should be located
• Default Mode 20 MHz
as close as possible to Pins 20 and 72 on the Flat Package
• Software Programmable Option 10 MHz and Pins A9 and J3 on the PGA package, and 0.1 µF at Pin 37/D3.
„ BU-65179* (13) MIL-STD–1760 requires that the Mini-ACE produce a 20 Vp-p min-
• Pin Programmable Option 10/12/16/20 MHz imum output on the stub connection.

„ Long Term Tolerance

• 1553A Mode 0.01 %
• 1553B Mode 0.1 %
„ Short Term Tolerance, 1 second
• 1553A Mode 0.001 %
• 1553B Mode 0.01 %
„ Duty Cycle
• 16 MHz 33 67 %
• 12 MHz 40 60 %
• 10 MHz* 40 60 %
• 20 MHz 40 60 %

THERMAL
Thermal Resistance, Junction-to-
Case, Hottest Die (θJC)
„ BU-65178/61588X3* 6.8 °C/W
Operating Junction Temperature -55 150 °C
Storage Temperature -65 150 °C
Lead Temperature (soldering, 10 +300 °C
sec.)

PHYSICAL CHARACTERISTICS
Size
„ BU-65178/61588 P 1.0 X 1.0 X 0.150 in.
BU-65179*/61688*/61689* (25.4 x 25.4 x 3.81) (mm)
„ BU-65178/61588 F/G 1.0 X 1.0 X 0.155 in.
BU-65179*/61688*/61689* (25.4 x 25.4 x 3.94) (mm)

Weight
„ BU-65178/61588 F/P/G 0.3 oz
BU-65179*/61688*/61689* (9) (g)

Notes: Notes 1 through 6 are applicable to the Receiver Differential

Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together internally).
(2) Measurement of impedance is directly between pins TX/RX A(B)
and TX/RX A(B) of the BU-65178/61588X3 hybrid.
(3) Assuming the connection of all power and ground inputs to the hybrid.
(4) The specifications are applicable for both unpowered and powered conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed, but not tested, over the operating range.
(7) Assumes a common mode voltage within the frequency range of dc to 2
MHz, applied to pins of the isolation transformer on the stub side (either direct
or transformer coupled), referenced to hybrid ground. Use a DDC recom-
mended transformer or other transformer that provides an equivalent CMRR.

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 NOTES
TABLE 2. BU-65178/65179*/61588/61688*/61689* PIN ** Note that the Test Output pins on the flat pack are pads located on
LISTINGS (QFP QUAD FLAT PACK, PGA-PIN GRID the bottom of the package.
ARRAY AND GULL LEAD) 1. BU-65179*, A15/A14 pins are actually CLK SEL 1 / CLK SEL 0 respectively.
2. BU-65179*, A12 pin selects the RT_BOOT_L OPTIONAL MODE.
3. BU-65179*, A13 pin has no connection.
QFP PGA NAME QFP PGA NAME
1 B4 MEM/REG 42 H9 D00
2 B5 MSTCLR 43 F9 D02
3 C2 A11 44 F7 D03
4 C3 A10 45 G5 D05
5 C1 TX/RX-A 46 E7 D08
6 D2 A08 47 E9 D07
7 D1 TX/RX-A 48 D7 D13
8 C4 A14, See NOTE 1 49 B2 D12
9 E3 A04 50 D9 D14
10 F2 A03 51 B9 D09
11 E1 A07 52 A2 D11
12 F3 A02 53 D8 D15
13 G1 TX/RX-B 54 A1 D10
14 G4 MEMOE/ADDR_LAT 55 C9 TRANSPARENT/
BUFFERED
15 G3 A00 56 B8 READYD
16 H1 TX/RX-B 57 C8 INT
17 A7 LOGIC GND 58 A3 IOEN
18 A8 LOGIC GND 59 B7 TX_INH_A
19 J8 LOGIC GND 60 C7 TX_INH_B
20 A9 +5V VCC2 61 C6 SELECT
21 J7 RTAD2 62 A6 STRBD
22 F1 A06 63 A5 RD/WR
23 J2 MEMWR/ 64 J1 DTGRT/MSB/LSB
ZEROWAIT
24 H5 DTREQ/16/8 65 A4 Test Output (RX-A)
25 H3 Test Output (RX-B) 66 C5 A15, See NOTE 1
26 H4 Test Output (RX-B) 67 B6 Test Output (RX-A)
27 G2 A01 68 E2 A05
28 J5 MEMENA_IN/ 69 J4 A09
TRIGGER_SEL
29 J6 DTACK/ 70 B3 A12, See NOTE 2
POLARITY_SEL
30 H6 CLOCK_IN 71 B1 A13, See NOTE 3
31 G7 RT_AD_LAT 72 J3 +5V VCC1
32 H2 SSFLAG/EXT_TRIG ** D4 TestOutput(A_RExt)
33 H7 RTAD0 D5 Test Output
** (A_Test1)
34 G8 RTAD3
35 H8 RTAD4 ** D6 Test Output
(AB_Test4)
36 E8 D06
** E4 TestOutput(B_RExt)
37 D3 +5V VCC
** E6 TestOutput
38 F8 D01 (AB_Tstck)
39 G6 D04 TestOutput
40 G9 RTADP ** F4 (AB_Test2)
41 J9 RTAD1 TestOutput
** F5 (AB_Test3)
TestOutput
** F6 (B_Test1)
N/A E5 No Connect

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 2.000 ±0.015
(50.800 ±0.381)
1.000 SQ ±0.010
(25.400 ±0.254)
0.500 ±0.005
(12.70 ±0.127)

0.200 ±0.005
(5.080 ±0.127)

0.100 DIA.
(2.540) (see note 4)

P8 P7 P6 P5

P4 P3 P2 P1
72
1

INDEX DENOTES
PIN NO. 1
0.018 ±0.002 0.050 ±0.005
(0.457 ±0.051) (1.270 ±0.127)
VIEW "B"
VIEW "B"
VIEW "A" 0.850 ±0.008
(21.590 ±0.203)

BOTTOM VIEW

0.010 ±0.002
(0.254 ±0.051) 0.130 MAX 0.050 ±0.005
(3.31) (1.270 ±0.127)

0.035 ±0.005 0.040 ±0.004

(0.889 ±0.127) 1.024 ±0.014 NOM. (1.016 ±0.102)
(26.010 ±0.356)
VIEW "A" 0.090 ±0.010
(2.286 ±0.254)
SIDE VIEW

Notes:
1) Dimensions are in inches (mm).
2) Package Material: Alumina (AL2O3)
3) Lead Material: Kovar, Plated by 50µ in. minimum nickel under 60µ in. minimum gold.
4) There are 8 test pads located on the bottom of the package. These pads are recessed
so as not to interfere when mounting the hybrid.
FIGURE 2. BU-65178F / 65179F* /61588F /61688F*/61689F* MECHANICAL OUTLINE (QUAD FLAT PACK - QFP)

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 0.800 ±0.005
(20.320 ±0.127) 0.100 ±0.005
(2.540 ±0.127)
9
8
7 0.070 ±0.005
6 (1.778 ±0.127)
5
4
0.070 ±0.005
3 (1.778 ±0.127)
2
1

J H G F E D C B A
0.180 ±0.008
BOTTOM VIEW (4.572 ±0.203)

1.000 SQ ±0.010 0.155 MAX

(25.400 ±0.254) (3.810)

0.018 ±0.002
(0.457 ±0.051)

Indicates
Pin A1

TOP VIEW SIDE VIEW

Notes:
1) Dimensions are in inches (mm).
2) Package Material: Alumina (AL2O3)
3) Lead Material: Kovar, Plated by 50µ in. minimum nickel under 60µ in. minimum gold.

FIGURE 3. BU-65178P / 65179P* /61588P /61688P*/61689P* MECHANICAL OUTLINE (PIN GRID ARRAY - PGA)
1.38 ±0.02
(35.05 ±0.51)

1.00 SQ ±0.01
(25.40 ±0.25)

0.19 Ref
(4.83 Ref)

0.100 DIA.
(2.540) (see note 4)
Notes:
1) Dimensions are in inches (mm).
2) Package Material: Alumina (AL2O3)
3) Lead Material: Kovar, Plated by 50µ in. minimum nickel
P8 P7 P6 P5 under 60µ in. minimum gold.
4) There are 8 test pads located on the bottom of the package.
These pads are recessed so as not to interfere when
P4 P3 P2 P1 mounting the hybrid.
72
1

VIEW "B"
0.850 ±0.008
(21.590 ±0.203)

BOTTOM VIEW 0.018 ±0.002 0.050 ±0.005

(0.457 ±0.051) (1.270 ±0.127)
VIEW "B"

0.08 MIN FLAT INDEX DENOTES 0.012 R. MAX

(2.03) PIN NO. 1 (0.305 R.)
0.130 MAX 0.010 ±0.002
(3.31) (0.254 ±0.051)

1.024 ±0.014 NOM.

(26.010 ±0.356)
VIEW "A"
0.05 MIN FLAT
SIDE VIEW (1.27)
0.075 MAX FLAT
(1.91)
0.050 ±0.005
(1.27 ±0.127)

0.006 -0.004,+0.010
(0.152 -0.100,+ 0.254)
VIEW "A"

FIGURE 4. BU-65178G / 65179G* /61588G /61688G*/61689G* MECHANICAL OUTLINE (GULL LEAD)

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TRANSFORMERS
In selecting isolation transformers to be used with the Mini-ACE, This inductance must be less than 6.0 µH. Similarly, if the other
there is a limitation on the maximum amount of leakage induc- side of the primary is shorted to the primary center-tap, the
tance. If this limit is exceeded, the transmitter rise and fall times inductance measured across the “secondary” (stub side) wind-
may increase, possibly causing the bus amplitude to fall below ing must also be less than 6.0 µH.
the minimum level required by MIL-STD-1553. In addition, an
excessive leakage imbalance may result in a transformer dynam- The difference between these two measurements is the
ic offset that exceeds 1553 specifications. “differential” leakage inductance. This value must be less than
1.0 µH.
The maximum allowable leakage inductance is 6.0 µH, and
is measured as follows: Beta Transformer Technology Corporation (BTTC), a subsidiary
of DDC, manufactures transformers in a variety of mechanical
The side of the transformer that connects to the configurations with the required turns ratios of 1:2.5 direct cou-
Mini-ACE is defined as the “primary” winding. If one side of the pled, and 1:1.79 transformer coupled. TABLE 3 provides a listing
primary is shorted to the primary center-tap, the inductance of many of these transformers. For further information, contact
should be measured across the “secondary” (stub side) winding. BTTC at 631-244-7393 or at www.bttc-beta.com.

TABLE 3. BTTC TRANSFORMERS FOR USE WITH MINI-ACE

TRANSFORMER CONFIGURATION BTTC PART NO.

B-3067
Single epoxy transformer, through-hole, 0.625" X 0.625", 0.250" max height
B-3226

Single epoxy transformer, through-hole, 0.625" X 0.625", 0.220" max height. B-3818

Single epoxy transformer, flat pack, 0.625" X 0.625", 0.275" max height B-3231

Single epoxy transformer, surface mount, 0.625" X 0.625", 0.275" max height B-3227

Single epoxy transformer, surface mount, hi-temp solder, 0.625" X 0.625", 0.220" max height. B-3819

Single epoxy transformer, flat pack, 0.625" X 0.625", 0.150" max height LPB-5014

Single epoxy transformer, surface mount, 0.625" X 0.625", 0.150" max height LPB-5015

Single epoxy transformer, through hole, transformer coupled only, 0.500" X 0.350", 0.250" max height B-3229

Dual epoxy transformer, twin stacked, 0.625" X 0.625", 0.280" max height TST-9007

Dual epoxy transformer, twin stacked, surface mount, 0.625" X 0.625", 0.280" max height TST-9017

Dual epoxy transformer, twin stacked, flat pack, 0.625" X 0.625", 0.280" max height TST-9027

Dual epoxy transformer, side by side, through-hole, 0.930" X 0.630", 0.155" max height TLP-1205

Dual epoxy transformer, side by side, flat pack, 0.930" X 0.630", 0.155" max height TLP-1105

Dual epoxy transformer, side by side, surface mount, 0.930" X 0.630", 0.155" max height TLP-1005

Dual epoxy transformer, side by side, surface mount, 1.410" X 0.750", 0.130" max height DLP-7115 (see note1)

Single metal transformer, hermetically sealed, flat pack, 0.630" X 0.630", 0.175" max height HLP-6014

Single metal transformer, hermetically sealed, surface mount, 0.630" X 0.630", 0.175" max height HLP-6015

DLP-7014
NOT RECOMMENDED SLP-8007
SLP-8024
Notes:
1. DLP-7115 operates to +85°C max. All other transformers listed operate to +130°C max.

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INTERFACE TO MIL-STD-1553 BUS
FIGURE 5 illustrates the interface between the various versions as the nominal peak-to-peak voltage levels at various points
of the Mini-ACE and a MIL-STD-1553 bus. Connections for both (when transmitting), are indicated in the diagram.
direct (short stub) and transformer (long stub) coupling, as well

DATA
BUS
Z0
SHORT STUB
(DIRECT COUPLED)
(1:2.5)

55 Ω 1 FT MAX
TX/RX

11.2 Vpp 28 Vpp 7 Vpp

Mini-ACE
TX/RX 55 Ω
ISOLATION
TRANSFORMER

OR LONG STUB
(TRANSFORMER
(1:1.79) COUPLED) (1:1.41)

20 FT MAX 0.75 Z0

11.2 Vpp 20 Vpp 28 Vpp

7 Vpp
Mini-ACE
0.75 Z0
ISOLATION COUPLING
TRANSFORMER TRANSFORMER

Z0
NOTES: 1. Z 0 = 70 TO 85 OHMS
2. NOMINAL VOLTAGE
LEVELS SHOWN

FIGURE 5. MINIATURE ADVANCED COMMUNICATIONS ENGINE INTERFACE TO MIL-STD-1553 BUS

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ORDERING INFORMATION

BU-61588F3-11XX

Supplemental Process Requirements:

S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Source Inspection
K = One Lot Date Code
W = One Lot Date Code and Pre-Cap Source Inspection
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, Pre-Cap Source Inspection and 100% Pull Test
Blank = None of the Above
Test Criteria:
0 = Standard Testing
2 = MIL-STD-1760 Amplitude Compliant - Applies to +5 Volt Transceiver Option Only
Process Requirements:
0 = Standard DDC processing, no Burn-In (See table on next page)
1 = MIL-PRF-38534 Compliant
2 = B*
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See table on next page)
Temperature Range/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Voltage/Transceiver Option:
0 = No Transceivers
3 = +5 Volts, rise/fall times=100 to 300 ns (-1553B) (See Test Criteria - 1760 Compliant with option -XX2)
Package Type:
F = 72-Pin Quad Flat Pack
P = 81-Pin PGA
G = 72-Pin Gull Lead (Contact factory.)
Product Type:
65178 = RT Only, 16/12 MHz, 4K RAM
61588 = BC/RT/MT, 16/12 MHz, 4K RAM
65179 = RT/RT_BOOT, 10/12/16/20 MHz, 4K RAM
61688 = BC/RT/MT, 12/16 MHz, 64K RAM
61689 = BC/RT/MT, 10/20 MHz, 64K RAM

*Standard DDC Processing with burn-in and full temperature test, see table on next page.

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 STANDARD DDC PROCESSING
FOR HYBRID AND MONOLITHIC HERMETIC PRODUCTS
MIL-STD-883
TEST
METHOD(S) CONDITION(S)
INSPECTION 2009, 2010, 2017, and 2032 —
SEAL 1014 A and C
TEMPERATURE CYCLE 1010 C
CONSTANT ACCELERATION 2001 3000g
BURN-IN 1015 (note 1), 1030 (note 2) TABLE 1
Notes:
1. For Process Requirement "B*" (refer to ordering information), devices may be non-compliant with MIL-
STD-883, Test Method 1015, Paragraph 3.2. Contact factory for details.
2. When applicable.

Data Device Corporation BU-65178/65179*/61688*/61689*

www.ddc-web.com 11 K-04/05-0
 The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.

Please visit our Web site at www.ddc-web.com for the latest information.

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U
REG

RM

®
ST
FI
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ERED
DATA DEVICE CORPORATION
REGISTERED TO ISO 9001:2000
FILE NO. A5976

K-04/05-0 12 PRINTED IN THE U.S.A.

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