DR.
MEGHNAD SAHA INSTITUTE OF TECHNOLOGY, HALDIA
DEBHOG, HALDIA, PURBA MEDINIPORE, PIN-721657
DEPARTMENT OF COMPUTER SCIENCE & TECHNOLOGY
2ND YEAR-3RD SEMESTER
E-CONTENTS: COMPUTER ORGANIZATION AND ARCHITECTURE
UNIT 2: INSTRUCTION STRUCTURE AND ADDRESSING
MODES, NUMBER RERESENTATION
DEVELOPED BY
GITIKA MAITY, LECTURER IN CST
DEPARTMENT OF COMPUTER SCIENCE & TECHNOLOGY
DR. MEGHNAD SAHA INSTITUTE OF TECHNOLOGY, HALDIA
DEBHOG, HALDIA, PURBA MEDINIPORE, PIN-721657
2.1 Instruction Format. 0,1,2,3
address instruction
Instruction Format. 0,1,2,3 address
instruction
Instruction Fields
Op-code field - specifies the operation to be
performed
Address field - designates memory address(s)
or a processor register(s)
Mode field - specifies the way the operand
or the effective address is determined
The number of address fields in the instruction format
depends on the internal organization of CPU
Instruction Format. 0,1,2,3 address
instruction
CPU organizations are of three types on the basis of number of
address fields:
1. Single Accumulator organization:
ADD X /* AC AC + M[X] */
2. General register organization:
ADD R1, R2, R3 /* R1 R2 + R3 */
ADD R1, R2 /* R1 R1 + R2 */
MOV R1, R2 /* R1 R2 */
ADD R1, X /* R1 R1 + M[X] */
3. Stack organization:
PUSH X /* TOS M[X] */
ADD
THREE-ADDRESS INSTRUCTIONS
The program in assembly language that evaluates X = (A +B) * (C
+ D) is shown below, together with comments that explain the
register transfer operation of each instruction.
ADD R1, A, B R1 ← M [A] + M [B]
ADD R2, C, D R2 ← M [C] + M [D]
MUL X, R1, R2 M [X] ← R1 * R2
It is assumed that the computer has two processor registers, R1
and R2. The symbol M [A] denotes the operand at memory
address symbolized by A.
TWO-ADDRESS INSTRUCTIONS
The program to evaluate X = (A + B) * (C + D) is as follows:
MOV R1, A R1 ← M [A]
ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1* R2
MOV X, R1 M [X] ← R1
ONE-ADDRESS INSTRUCTIONS
The program to evaluate X = (A + B) * (C + D) is
LOAD A AC ← M [A]
ADD B AC ← A [C] + M [B]
STORE T M [T] ← AC
LOAD C AC ← M [C]
ADD D AC ← AC + M [D]
MUL T AC ← AC * M [T]
STORE X M [X] ← AC
ZERO-ADDRESS INSTRUCTIONS
The following program shows how X = (A + B) * (C + D) will
be written for a stack organized computer. (TOS stands for
top of stack)
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B)
PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C + D)
MUL TOS ← (C + D) * (A + B)
POP X M [X] ← TOS
REFERENCES:
Books:
1. Computer System Architecture by Rao
2. Computer Organization with Architecture by Basu
3. Computer Organization and Architecture by Stallings
Online materials :
1. https://www.iare.ac.in/sites/default/files/PPT/CO%20Lecture
%20Notes.pdf
2. http://www.c-jump.com/CIS77/CPU/InstrCycle/lecture.html
3. https://www.geeksforgeeks.org/different-instruction-cycles/
4. https://www3.ntu.edu.sg/home/ehchua/programming/java/d
atarepresentation.html#:~:text=Computers%20use%20a%20fi
xed%20number,%2Dbit%20or%2064%2Dbit.&text=Unsigned
%20Integers%3A%20can%20represent%20zero,zero%2C%20p
ositive%20and%20negative%20integers.
THANK YOU
