Noise in Digital Integrated Circuits
Lecture 4
v(t) V DD
The CMOS Inverter
Peter Cheung Department of Electrical & Electronic Engineering Imperial College London
i(t)
(a) Inductive coupling
URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk
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(b) Capacitive coupling
(c) Power and ground noise
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DC Operation: Voltage Transfer Characteristic
DC Transfer Curve: Load line
Consider a simple inverter
When Vin = 0 When Vin = Vdd Vout = Vdd Vout = 0
In between, Vout depends on current through transistors as determined by transistor width and length By KCL, steady state condition is: Idsn = |Idsp| Find transfer function by solving equations, but better insight using graphical method
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DC Transfer Curve
Operating Regions
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Effect of beta ratio on switching thresholds
Extract switching point depends on p/ n If p/ n = 1, switching occurs at around Vdd/2 Otherwise:
Noise Margins
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Maximize Noise Margins
Select logic levels at unity gain point of DC transfer characteristic
Voltage Transfer Characteristic of Real Inverter
5.0 4.0 Vout (V) 3.0 2.0 1.0 NM L
VM NM H
0.0
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1.0
2.0 3.0 V in (V)
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4.0
5.0
Lecture 4 - 10
The Regenerative Property
V in
... v0 v1 v2 v3 v4 v5 v6 (a) A chain of inverters. v 1 , v 3 , ... f(v) v 1 , v 3 , ... finv(v)
Delay Definitions
50% t t V out
f(v)
pHL
pLH 90%
finv(v)
50%
v 0 , v 2 , ... (b) Regenerative gate
PYKC 18-Oct-07 E4.20 Digital IC Design
v 0 , v 2 , ... (c) Non-regenerative gate
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10%
tf
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tr
Lecture 4 - 12
Ring Oscillator
Power Dissipation
v0
v1
v2
v3
v4
v5
v0
v1
v5
T = 2 tp N
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Delay Estimation
Need to estimate delay without circuit simulation e.g. SPICE
Not as accurate as simulation But easier to ask What if?
RC Delay Models
For each MOS transistor
Assume ideal switch + capacitance + ON resistance Unit nMOS has resistance R, gate capacitance C Unit pMOS has resistance 2R, gate capacitance C Capacitance width ON resistance 1/width
The step response usually looks like a 1st order RC response with a decaying exponential Use RC delay models to estimate delay
C = total capacitance on output node Use effective resistance R so that t pd = RC
Characterize transistors by finding their effective R depends on average current as gate switches
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Computing the Capacitances
V DD M2 V in C gd12 C db2 V out C g4 M4 V out2 VD D
Computing the Capacitances
C db1 M1
Cw
C g3
M3
Interconnect
Fanout
Simplified Model
V in
V out
CL
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Impact of Rise Time on Delay
0.35
Delay as a function of VDD
28
0.3 tpHL(nsec)
24 Normalized Delay 20 16 12 8 4 0 1.00 2.00
Assuming Vdd = 5V
0.25
0.2
0.15
0.2
0.4 0.6 tr is e (nsec)
0.8
3.00
4.00
5.00
V DD (V)
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Where Does Power Go in CMOS? Dynamic power
charging and discharging capacitors
Dynamic Power Dissipation
Vdd
Short circuit currents
short circuit path between power rails during switching
Vin
Vout
Leakage power
Leaking diodes and transistors
CL
Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f
Not a function of transistor sizes! Need to reduce C L , V dd , and f to reduce power.
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Short Circuit Currents
Vdd
Leakage
Vdd
Vin CL
Vout
Vout
Drain Junction Leakage
0 .15
IVDD (mA)
0 .10
Sub-Threshold C urrent
0 .05
0. 0
1.0
2.0 3.0 Vin (V)
4.0
5.0
Sub-Threshold Current Dominant Factor
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Sub-Threshold in MOS
How to reduce power? Prime choice: Reduce voltage!
Recent years have seen an acceleration in supply voltage reduction Design at very low voltages (0.6 0.9 V by 2010!) Maintaining performance by threshold scaling leads to increased leakage
Reduce switching activity Reduce physical capacitance
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