UNIT IV

PIC MICROCONTROLLER
APPLICATION
AGENDA
• Introduction to PIC
• Features
• Architecture
• Programming model(memory organization)
• Oscillator options
• BOD, power down modes
• Configuration bit settings
• Peripheral support
• Comparison of 10f,12f,16f and 18f PIC controller
families
• Overview of instruction set
Introduction to PIC
• In 1989, Microchip technology introduced an 8 bit
controller called PIC
• PIC: Peripheral Interface Controller.
• The PIC family:
▫ 10xxx, 12xxx, 14xxx, 16xxx,17xxx and 18xxx
• PIC 18xxx is the highest performing microcontroller
from the PIC family
• It is available in 18-pin to 80-pin packages.
Features of PIC 18fxx
• High speed RISC Architecture
• Operating frequency for PIC18FXXX DC to 40 MHz
• General features include: Timers, Watch dog timers,
ADC, Extended Instruction / Data memory , Serial
communication , Capture/ Compare/ Pulse width
modulation (CCP).
• PIC 18 can have 2MB of program ROM memory. ROM may
be of different types such as (flash, OTP, UV-EPROM etc.)
▫ 21 bit PC available
▫ On chip ROM: Flash :F and OTP:C
• PIC can have maximum of 4KB of data RAM.
▫ The RAM consists of two components:
 GP RAM
 SFRs
• EEPROM 256 Bytes for storing critical data.(optional)
• It uses 16-bit wide instructions, 8-bit wide data path.
• 5 I/O ports available for PIC18f4520
▫ PORT A through PORT E
▫ Each port can be configured as input or output.-Bidirectional port
▫ Each port has some other functions Such as timer , ADC,
interrupts and serial communication
Features: PIC 18Fxxx
• Power Management Features
• Flexible Oscillator Structure
• Wide Operating Voltage Range: 2.0V to 5.5V
• High-Current Sink/Source 25 mA/25 mA
• Many on chip peripherals available.
▫ Up to three Programmable External Interrupts
▫ Counter/Timer modules.
 Modules 0,2 (8-Bits)
 Modules 1,3 (16-Bits)
▫ Up to two CCP Modules/ ECCP module
 The CCP module is a peripheral which allows the user to time and
control different events
▫ ADC 10-bits with 13 input multiplexer.
PIC 18Fxxx : Peripherals
▫ Master Synchronous Serial Port (MSSP) module
supporting 3-Wire SPI (all 4 modes) and I2C Master
and Slave modes
▫ Enhanced Addressable USART module
▫ Dual Analog Comparators with Input Multiplexing
▫ Programmable 16-Level High/Low-Voltage Detection
(HLVD) module:
 Supports interrupt on High/Low-Voltage Detection
1 MCLR/Vpp/RE3 RB7/KBI3/PGD 40
2 RA0/AN0 RB6/KBI2/PGC 39
3 RA1/AN1 RB5/KBI1/PGM 38
4 RA2/AN2/Vref-/CVref RB4/KBI0/AN11/CSSPP 37
5 RA3/AN3/Vref+ RB3/AN9/VPO/CCP2^ 36
6 RA4/T0CKI/C1out/RCV RB2/INT2/AN8/VMO 35
7 RA5/AN4/SS RB1/INT1/AN10/SCK/SCL 34
8 RE0/AN5/CK1SPP RB0/INT0/AN12/SDI/SDA 33
9 RE1/AN6/CK2SPP VDD 32
10 RE2/AN7/OESPP VSS 31
11 VDD RD7/SPP7/P1D 30
12 VSS RD6/SPP6/P1C 29
13 OSC1/CLKI RD5/SPP5/P1B 28
14 OSC2/CLKO/RA6 RD4/SPP4 27
15 RC0/T1OSO/T13CKI RC7/RX/DT/SDO 26
16 RC1/T1OSI/UOE/CCP2^ RC6/TX/CK 25
17 RC2/CCP1/P1A RC5/D+/VP 24
18 VUSB RC4/D-/VM 23
19 RD0/SPP0 RD3/SPP3 22
20 RD1/SPP1 RD2/SPP2 21
Architecture of PIC 18fxxx
WREG(Working Register)
• 8 bit WREG in the PIC.
• Similar to accumulator of other controller
• WREG is used for all arithmetic and logic instructions.
• Ex: MOVLW k ; move literal value k into WREG
MOVLW 25h ; move 25h into WREG
• ADDLW K ; add literal value k to WREG
ADD LW 35h ; add value 35h to W(W=W+35h)
• Moving a value larger than 255(FFh), into the WREG
will truncate the upper byte and cause a warning in .err
file.
The file register
• The data memory space in PIC is a read/write
memory.
• The data memory is also called file registers.
• the file registers are used by the CPU for data
storage, scratch pad and registers for internal use.
• The file register data RAM in PIC is divided into two
sections:
▫ Special Function Registers(SFRs)
▫ General Purpose RAM(GP-RAM)
File Register and access bank in PIC18
• The PIC 18f can have maximum of 4KB (4096 bytes)
of on chip RAM.
• With 4096 bytes ,the file register has an addresses of
000-FFFh.
• The file register is divided into 256 byte memory
banks.
• Therefore maximum 16 (0-F) banks .
• At least one bank for file register is there in every
PIC. This bank is known as access bank.
Data Memory Organization
• Data memory is upto 4KB
• Divided into Banks of 256 bytes
• 4KB/256bytes= 16 Banks
• Half of Bank 0 and half of virtual
Bank 15 is known as access bank
• BSR: Bank Select Register (0 to F)
▫ 4-bit Register
▫ Provides upper 4-bits of 12-bit address of data memory
▫ Direct addressing

• FSR: File Select Registers

▫ FSR0, FSR1, and FSR2
▫ FSR: composed of two 8-bit registers
▫ FSRH and FSRL
▫ Used as pointers for data registers (indirect addressing)
▫ Holds 12-bit address of data register
• Instruction Decoder
▫ 16-bit Instructions
• STATUS: Flag Register
▫ 5 individual bits called flags
• PRODH:PRODL
▫ 16-bit Product of 8-bit by 8-bit Multiply
• Program Counter (PC)
▫ 21-bit register functions as a pointer to program memory during
program execution
• Table Pointer
▫ 21-bit register used as a memory pointer to copy bytes between program
memory and data registers
• Stack Pointer (SP)
▫ 5-bit register used to point to the stack
• Stack
▫ 31 registers used for temporary storage of memory addresses during
execution of a program
Program ROM organization
• PIC18F4550 each have 32 KB of Flash memory and can store
up to 16,384 single-word instructions.
• PIC18 devices have two interrupt vectors.
• The Reset vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
• The Flash program memory is readable, writable and erasable
during normal operation over the entire VDD range.
• A read from program memory is executed on one byte at a
time.
• A write to program memory is executed on blocks of 32 bytes
at a time.
• Program memory is erased in blocks of 64 bytes at a time.
Program Counter(PC)
• The PC is of 21 bits. Divided into three separate 8-bit
registers.
▫ PCL <7:0>
▫ PCH <15:8>
▫ PCU <20:16>
• Lower byte accessible as readable and writable
in data memory.
• Upper bytes indirectly accessible via
PCLATH/PCLATU
• To prevent the PC from becoming misaligned with
word instructions, the Least Significant bit of PCL is
fixed to a value of ‘0’.
• The PC increments by 2 to address sequential
instructions in the program memory.
• 22nd bit used to access configuration memory
Status Register

• C (Carry/Borrow Flag):
▫ set when an addition generates a carry and a subtraction generates a borrow
• DC (Digit Carry Flag):
▫ also called Half Carry flag; set when carry generated from Bit3 to Bit4 in an
arithmetic operation
• Z (Zero Flag):
▫ set when result of an operation is zero
• OV (Overflow Flag):
▫ set when result of an operation of signed numbers goes beyond seven bits
• N (Negative Flag):
▫ set when bit B7 is one of the result of an arithmetic /logic operation
Stack
• The stack operates as a 31-word by 21-bit RAM .
• It is not part of either program or data space.
• 5-bit Pointer, STKPTR.
• The Stack Pointer is readable and writable.
▫ The address on the top of the stack is readable and writable
through the Top-of-Stack (TOS) Special Function Registers.
▫ Data can also be pushed to, or popped from the stack, using these
registers.
• A CALL type instruction causes a push onto the stack.
▫ The Stack Pointer is first incremented and the location pointed to
by the Stack Pointer is written with the contents of the PC
(already pointing to the instruction following the CALL).
• A RETURN type instruction causes a pop from the stack.
▫ The contents of the location pointed to by the STKPTR are
transferred to the PC and then the Stack Pointer is decremented
• For stack access, four registers are provided in the Special
Function Register (SFR) bank. They are:
▫ TOSU
▫ TOSH
▫ TOSL
▫ STKPTR
• The Stack Pointer is initialized to ‘00000’ after all Resets.
• There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this is
only a Reset value.
• Status bits indicate if the stack is full, or has overflown or
underflown.
• Only the top of the return address
stack (TOS) is readable and
writable.
• A set of three registers,
TOSU:TOSH:TOSL, hold the
contents of the stack location
pointed to by the STKPTR
register.
 Stack Pointer (STKPTR)
D7 D6 D5 D4 D3 D2 D1 D0

STKFUL STKUNF X SP4 SP3 SP2 SP1 SP0

D7: STKFUL: Stack full flag:

Set when stack is full or an overflow occurs
D6: STKUNF: Stack underflow flag:
Set when the stack underflow occurred.
D5: Unused
D4 to D0 bits: Stack Pointer
CONFIGURATION REGISTERS
• The Configuration bits can be programmed (read as‘0’)
or left unprogrammed (read as ‘1’) to select various
device configurations.
• The configuration memory space (300000h-3FFFFFh),
can only be accessed using table reads and table writes.
• The Configuration registers are written a byte at a
time.
List of Configuration Register
 CONFIG 4L 85h
D7 D6 D5 D4 D3 D2 D1 D0

/DEBUG XINST X X X LVP X STVREN

• /DEBUG: Background Debugger Enable bit

▫ 1 = Background debugger disabled
▫ 0 = Background debugger enabled
• XINST: Extended Instruction Set Enable bit
▫ 1 = Instruction set extension and Indexed Addressing mode enabled
▫ 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
• LVP: Single-Supply ICSP Enable bit
▫ 1 = Single-Supply ICSP enabled
▫ 0 = Single-Supply ICSP disabled
• STVREN: Stack Full/Underflow Reset Enable bit
▫ 1 = Stack full/underflow will cause Reset
▫ 0 = Stack full/underflow will not cause Reset
ON-CHIP RESET CIRCUIT
Reset facility available
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during power-managed modes
• Watchdog Timer (WDT) Reset (during execution)
• Programmable Brown-out Reset (BOR)
• RESET Instruction
• Stack Full Reset
• Stack Underflow Reset
 RCON: Reset Control
D7 D6 D5 D4 D3 D2 D1 D0

IPEN SBOREN X /RI /TO /PD /POR /BOR

• IPEN: Interrupt Priority Enable bit

• SBOREN: BOR Software Enable bit
• /RI: RESET Instruction Flag bit
• /TO: Watchdog Time-out Flag bit
• /PD: Power-Down Detection Flag bit
• /POR: Power-on Reset Status bit
• /BOR: Brown-out Reset Status bit
Brown out Reset(BOR)
• BOR circuit that provides the user with a number of
configuration and power-saving options.
• The BOR is controlled by the BORV<1:0> and
BOREN<1:0> Configuration bits.
• There are a total of four BOR configurations.
CONFIG 2L 1Fh
D7 D6 D5 D4 D3 D2 D1 D0

X X X BORV1 BORV0 BOREN1 BOREN0 /PWRTEN

• *BORV<1:0>: Brown-out Reset Voltage bits

▫ 11 =VBOR= 2.11V
▫ 10= VBOR = 2.79V
▫ 01= VBOR= 4.33V
▫ 00= VBOR=4.59V
• BOREN<1:0>: Brown-out Reset Enable bits
• /PWRTEN: Power-up Timer Enable bit
• *TPWRT= 65.5ms
• *TBOR=200usec

* Refer data sheet for values.

 BOR CONFIGURATION
BOR Configuration Status of
SBOREN BOR Operation
(RCON<6>)
BOREN1 BOREN0

0 0 Unavailable BOR disabled; must be enabled by

reprogramming the Configuration bits.
0 1 Available BOR enabled in software; operation controlled by
SBOREN.
1 0 Unavailable BOR enabled in hardware in Run and Idle modes,
disabled during Sleep mode.
1 1 Unavailable BOR enabled in hardware; must be disabled by
reprogramming the Configuration bits.
Oscillator Configurations
• PIC18F4550 devices can be operated in twelve different oscillator modes. The
user can program the Configuration bits, FOSC<3:0>, in CONFIG1H to select
one of these ten modes:
1. XT Crystal/Resonator
2. XTPLL Crystal/Resonator with PLL enabled
3. HS High-Speed Crystal/Resonator
4. HSPLL High-Speed Crystal/Resonator with PLL enabled
5. EC External Clock with FOSC/4 output
6. ECIO External Clock with I/O on RA6
7. ECPLL External Clock with PLL enabled and FOSC/4 output on RA6
8. ECPIO External Clock with PLL enabled, I/O on RA6
9. INTHS Internal Oscillator used as microcontroller clock source, HS Oscillator used as
USB clock source
10. INTXT Internal Oscillator used as microcontroller clock source, XT Oscillator used as
USB clock source
11. INTIO Internal Oscillator used as microcontroller clock source, EC Oscillator used as
USB clock source, digital I/O on RA6
12. INTCKO Internal Oscillator used as microcontroller clock source, EC Oscillator used as
USB clock source, FOSC/4 output on RA6
EXTERNAL OSCILLATOR OPTIONS
INTERNAL OSCILLATOR
• The PIC18F4520 devices include an internal oscillator
block.
• This may eliminate the need for external oscillator
circuits on the OSC1 and/or OSC2 pins.
• Two different clock signals INTOSC AND INTRC
• The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock.
• The internal RC oscillator (INTRC),provides a
nominal 31 kHz output.
 OSCCON
D7 D6 D5 D4 D3 D2 D1 D0

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFC SCS1 SCS0

• IDLEN: Idle Enable bit

▫ 1 = Device enters an Idle mode on SLEEP instruction
▫ 0 = Device enters Sleep mode on SLEEP instruction
• IRCF<2:0>: Internal Oscillator Frequency Select bits
▫ 111 = 8 MHz (INTOSC drives clock directly)
▫ 110 = 4 MHz
▫ 101 = 2 MHz
▫ 100 = 1 MHz
▫ 011 = 500 kHz
▫ 010 = 250 kHz
▫ 001 = 125 kHz
▫ 000 = 31 kHz (from either INTOSC/256 or INTRC directly)
• OSTS: Oscillator Start-up Timer Time-out Status bit
▫ 1 = Oscillator Start-up Timer (OST) time-out has expired;
primary oscillator is running
▫ 0 = Oscillator Start-up Timer (OST) time-out is running;
primary oscillator is not ready
• IOFS: INTOSC Frequency Stable bit
▫ 1 = INTOSC frequency is stable
▫ 0 = INTOSC frequency is not stable
• SCS<1:0>: System Clock Select bits
▫ 1x = Internal oscillator block
▫ 01 = Secondary (Timer1) oscillator
▫ 00 = Primary oscillator
 CONFIG 1H 07H
D7 D6 D5 D4 D3 D2 D1 D0

IESO FCMEN - - FOSC3 FOSC2 FOSC1 FOSC0

• IESO: Internal/External Oscillator Switchover bit

▫ 1 = Oscillator Switchover mode enabled
▫ 0 = Oscillator Switchover mode disabled
• FCMEN: Fail-Safe Clock Monitor Enable bit
▫ 1 = Fail-Safe Clock Monitor enabled
▫ 0 = Fail-Safe Clock Monitor disabled
• FOSC<3:0>: Oscillator Selection bits
ex:
▫ 0010 = HS oscillator
▫ 0001 = XT oscillator
▫ 0000 = LP oscillator
Bit/s Belongs to Function
INTSRC OSCTUNE To choose between INTOSC and INTRC
TUN4:TUN0 OSCTUNE Frequency tuning bits for Internal oscillator
IDLEN OSCCON To choose between power down modes when SLEEP
instruction is executed
IRCF2:IRCF0 OSCCON To select output frequency of Internal Oscillator
INTOSC(1MHz by default)
INTRC(31 KHz)
OSTS OSCCON To denote the change over from Oscillator start up timer to
primary osc
IOFS OSCCON Internal oscillator block stabilized and providing device clk
in RC mode
SCS1:SCS0 OSCCON Selects between the clock sources (Primary , secondary and
Internal)
IESO CONFIG1h To switch between internal/ external oscillator
FCMEN CONFIG1h Fail safe clock monitor enable/disable
FOSC3:FOSC0 CONFIG1h Select between the 12 different oscillator configurations
CLOCK DIAGRAM
PIC18F Programming Model
• The representation of
the internal architecture
of a microprocessor,
necessary to write
assembly language
programs

• Divided into two groups

▫ ALU Arithmetic Logic
Unit (ALU)
▫ Special Function
Registers (SFRs) from
data memory
Programming model of PIC18f
Registers
• WREG
▫ 8-bit Working Register (equivalent to an
accumulator)
• BSR: Bank Select Register
▫ 4-bit Register (0 to F)
 Only low-order four bits are used to
provide MSB four bits of a12-bit address
of data memory.
• STATUS: Flag Register
 Flags in Status Register

• C (Carry/Borrow Flag):
▫ set when an addition generates a carry and a subtraction generates a borrow
• DC (Digit Carry Flag):
▫ also called Half Carry flag; set when carry generated from Bit3 to Bit4 in an arithmetic
operation
• Z (Zero Flag):
▫ set when result of an operation is zero
• OV (Overflow Flag):
▫ set when result of an operation of signed numbers goes beyond seven bits
• N (Negative Flag):
▫ set when bit B7 is one of the result of an arithmetic /logic operation
File Select Registers (FSR)
• There are three registers:
 FSR0, FSR1, and FSR2
 Each register composed of two 8-bit
registers (FSRH and FSRL)
• Used as pointers for data registers
• Holds 12-bit address of data register
Instruction set of PIC 18f4520
• The CPU can access data in various ways. The data
could be in any register, memory location, or
provided as an immediate value. These various ways
of accessing data are called addressing modes.
• The addressing modes supported by a up/uc, are
determined when it is designed and cannot be altered
by the programmer.
• The addressing modes supported by PIC18f are:
▫ Immediate
▫ Direct
▫ Register Indirect
▫ Indexed-ROM
Addressing modes in brief
• Immediate:
▫ The operand is literal constant.
▫ Operand comes immediately after the opcode when an
instruction is specified.
▫ This addressing mode is used to load information into
WREG and selected registers but not in any file
registers.
ex: MOVLW 45H
ADDLW D’62’
• Direct:
• The entire data RAM file register can be accessed
using either direct or register indirect addressing
mode.
• In direct addressing mode, the operand data is in a
RAM memory location whose address is known and
this address is given as part of the instruction.
ex: MOVWF 0X40
MOVFF 0X40,0X50
• Register indirect:
• In this addressing mode, a register is used as a pointer to the
data RAM location.
• In PIC18f, three registers are used for this purpose:
▫ FSR0, FSR1,FSR2 (FSR: File select register)
• The FSR is 12-bit register allowing access to entire 4096 bytes
of data RAM.
• Use instruction LFSR (load FSR) to load the RAM location .
ex: LFSR 0,0X30 MOVWF INDF0
LFSR 1,0X20
LFSR 2,0X40
• The FSRs are split into 8 bit registers. As FSRxL and
FSRxH(only lower 4 bits used).
• INDF(Indirect register) is associated with each FSR.
▫ INDF0,INDF1,INDF2
• The data pointed by FSRx is moved into INDFx register.
• Indexed ROM
• This addressing mode is widely used to access data
from the program ROM space of PIC18f
• It is also known as table processing.
• There are a group of instructions for table
processing(both read as well as write).
• TBLPTR(Table pointer) is an 21 bit SFR used to
point byte to be fetched from code memory.
▫ TBLPTR is divided into three 8-bit parts viz.
TBLPTRL, TBLPTRH, TBLPTRU.
• The other SFR register used for table processing is
TABLAT.
▫ The TABLAT is used to keep the byte once it is fetched
into the CPU.
The instruction set is also grouped as:
• Byte oriented
15 OPCODE 9 d 8 a 7 f(FileReg) 0

• Bit oriented
15 OPCODE 9 b 8 a 7 f(FileReg) 0

• Literal
15 OPCODE 8 7 k (Literal) 0

• Control
15 OPCODE 8 7 n (Literal) 0

15 1111 12 11 n <19:8> (Literal) 0

The Bank Select Register again....

• movwf 0x070, 1 also written as: movwf 0x070, BANKED

• The execution of the above instruction depends on the value in the

Bank Select Register.

• If BSR = 0, then location 0x070 is modified.

• If BSR = 1, then location 0x170 is modified.
• If BSR = 2, then location 0x270 is modified....etc.

• movwf 0x070, 0 also written as: movwf 0x070, a(ACCESS)

• The execution of the above instruction does NOT depend on the

value in the Bank Select Register, only the 8 bits in the machine
code is used for the address location.
• Location 0x070 is always modified.
Rules for the ‘access’ bit in instructions
We will use the following rules for the value of the ‘a’ (Access)
bit in machine code produced for instructions that contain a
data memory address (these assumptions used by the
MPLAB® assembler)
a. If the data memory address is between 0x000 –0x07F or
between 0xF80 –0xFFF, assume the ‘a’ bit is a ‘0’ (ignore
the BSR).
b. If the data memory address is between 0x080 –0xF7F,
assume the ‘a’ bit is a ‘1’ (use the BSR).

We will NEVER write: movf 0x070, BANK

Always either “movf 0x070” (assume ACCESS, a = 0)
or “movf 0x170” (assume BANKED, a = 1).
 Changing the Bank Select Register
B B B B B B B B B B B B B B B B
movwf f [,a] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 0 1 1 1 a f f f f f f f f

fileReg (w)

mnemonic Machine code

movwf 0x070 0110 1110 0111 0000 = 0x6e70 (a=0)
movwf 0x170 0110 1111 0111 0000 = 0x6f70 (a=1)
movwf 0x270 0110 1111 0111 0000 = 0x6f70 (a=1)
movwf 0xF90 0110 1111 1001 0000 = 0x6e90 (a=0)

We will not specify the ‘a’ bit on instruction mnemonics.

 Machine code example for movwf
movwf 0x170 The instruction mnemonics are
For this to work, BSR must be 0x1! different, but the machine code
is the same! That is because
movwf 0x270 machine code only uses lower
For this to work, BSR must be 0x2!
8-bits of the address!!!

mnemonic Machine code

movwf 0x070 0110 1110 0111 0000 = 0x6e70 (a=0)
movwf 0x170 0110 1111 0111 0000 = 0x6f70 (a=1)
movwf 0x270 0110 1111 0111 0000 = 0x6f70 (a=1)
movwf 0xF90 0110 1110 1001 0000 = 0x6e90 (a=0)

By default (after processor reset), BSR = 0x0

Classification of the Instruction set

• Includes 77 instructions; 73 one word (16-bit) long and

remaining four two words (32-bit) long
• Divided into seven groups
▫ Move (Data Copy) and Load
▫ Arithmetic
▫ Logic
▫ Program Redirection (Branch/Jump)
▫ Bit Manipulation
▫ Table Read/Write
▫ Machine Control
Data Transfer
• MOVLW k ;copy literal value k(8 bit) into WREG
▫ MOVLW 0x45 ; WREG = 0x45
• MOVWF f,a ; copy the WREG to FileReg
▫ MOVWF PORTB ; PORTB= 0x45
• MOVF f,d,a (=MOVFW) ; Copy FileReg to WREG
▫ MOVF PORTB ; WREG = PORTB
▫ MOVF MyReg, F ; D=1, MyReg=MyReg, Flags affected
• *MOVFF Fs,Fd ; Copy byte from one FileReg to other FileReg
▫ MOVFF PORTB,PORTC ; PORTB copied to PORTC
• MOVLB k ; Copy literal value k (4-bit) to lower 4 bits of BSR
▫ MOVLB 0x2 ; use Bank 2
• *LFSR f,k ; Load into FSR registers a 12 bit value of k
▫ LFSR 0, 0X200 ; FSR0= 200H
• SETF f,a ; Set FileReg
• CLRF f,a ; Clear FileReg
movff Instruction
movff fs , fd B
15
B
14
B
13
B
12
B
11
B
10
B B B B
9 8 7 6
B B
5 4
B
3
B B
2 1
B
0

1 1 0 0 f f f f f f f f f f f f (src)
[fd] [fs] 1 1 1 1 f f f f f f f f f f f f (dest)

Move contents of location fs to location fd

machine code Instructions
0xC1A0 movff reg1,reg2
0xF23F

Requires two instruction words (4 bytes). Only movff, goto,

call, lfsr instructions take two words; all others take one word.
Arithmetic Instructions
• ADDLW k ; WREG=k + WREG
• ADDWF f,d,a ; Dest=WREG+FileReg
• ADDWFC f,d,a ; Dest= WREG+FileREG+C
• DAW ; Decimal adjust WREG
• SUBLW k ; WREG= k-WREG
• SUBWF f,d,a; dest= FileReg-WREG
• SUBWFB f,d,a ; Dest= FileReg-W-/Borrow
• SUBFWB f,d,a ; Dest= W-FileReg-/Borrow
• MULW k ; PRODH:PRODL=k x WREG
• MULWF f,a ; PRODH:PRODL= WREG x FileReg
• INCF f,d,a ; Increment FileReg
▫ INCF 0x20; if 20h loc=00h then after exe. 20h=01h
• INCFSZ f,d,a ; Increment FileReg & skip if zero
• INCFSNZ f,d,a ; Increment FileReg & skip if not zero
• DECF f,d,a ; Decrement FileReg
▫ DECF 0x20; if 20h loc=01h then after exe. 20h=00h
• DECFSZ f,d,a ; Decrement FileReg and skip if zero
• DECFSNZ f,d,a;Decrement FileReg and skip if not zero
Logical Instruction
• ANDLW k ; AND literal value k with WREG
• ANDWF f,d,a ; AND WREG with FileReg
• IORLW k; OR WREG with k
• IORWF f,d,a ; OR WREG with FileReg
• XORLW k ; XOR literal value with WREG
• XORWF f,d,a ; XOR WREG with FileReg
• COMF f,d,a ; Complement FileReg
• NEGF f,a ; 2’s complement of the value stored in
FileReg
▫ Result can’t be placed in WREG.
Rotate Instructions
• RLCF f,d,a ; Rotate Left through Carry
• RLNCF f,d,a ; Rotate Left through no Carry
• RRCF f,d,a ; Rotate Left through Carry
• RRNCF f,d,a ; Rotate Left through no Carry
• SWAPF f,d ; Swap nibbles in FileReg
Compare Instructions
• CPFSGT f,a ;Compare FileReg with WREG and skip if
greater(F>W)
• CPFSEQ f,a ; Compare FileReg with WREG and skip if
equal(F=W)
• CPFSLT f,a ; Compare FileReg with WREG and skip if
less than (F<W)
Branch Instructions
• BC addr8 ; Branch if carry (jump if C=1)
• BNC addr8 ; Branch if no carry (jump if C=0)
• BN addr8 ; Branch if negative(jump if N=1)
• BNN addr8 ; Branch if no negative (jump if N=0)
• BZ addr8; Branch if zero (jump if Z=1)
• BNZ addr8; Branch if no zero (jump if Z=0)
• BOV addr8; Branch if overflow(jump if OV=1)
• BNOV addr8; Branch if no overflow(jump if OV=0)
Conditional Branch
• In this type of instructions the control is transferred to
a target address if the condition is true.
• All conditional branch instructions are short jumps
• The target address can be 8bit address. Therefore the
jump can be targeted within -128 bytes backward
+127 bytes forward of the PC of the following
instruction.
• Branch instructions are 2 byte instructions
Unconditional Jump
• GOTO nn
• Transfers control unconditionally to a new address.
• This is a 4 byte instruction.
• ‘nn’ : 20bit address to address 2M of ROM memory
• The 0th bit of PC is always kept zero.
B B B B B B B B B B B B B B B B
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 0 1 1 11 n n nn n nn n
1 1 1 1 n n nn n n nn n nn n
Call Instruction
• *CALL k,s ; Transfers control to subroutine.
• RCALL addr11; Transfers control to a subroutine
within 1K space
• PUSH ;Push the PC onto the stack
• POP ; Pop from the stack.
• RETLW k ; The k value is placed in WREG and the
top of the stack is placed in PC
• RETURN s; Return from subroutine
• RETFIE s; Return from Interrupt exit
 Operation: (PC)+4 TOS,
n PC<20:1>,
CALL k,s If s=1, (W) (WS)
(Status) (STATUSs),
(BSR) (BSRs)

• CALL is a 4 byte instruction.

• First 12 bits are used for opcode and remaining 20
bits are used for address.
• 20 bits address allows to reach anywhere in 2MB
ROM memory.
• s is used for fast context switching.
B B B B B B B B B B B B B B B B
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 0 1 1 0s n n nn n nn n
1 1 1 1 n n nn n n nn n nn n
Machine Control Instruction
• CLRWDT; Clears Watchdog Timer
• SLEEP; Enter sleep mode
• RESET; Reset by software
• NOP; No operation
Bit oriented Instruction
• BCF f,b,a ; Clear bit of a FileReg
▫ BCF STATUS,C ; C=0
▫ BCF PORTB,5 ; clear PORTB.5(=0)
• BSF f,b,a ; Bit set FileReg
▫ BSF PORTC,4 ; Set bit PORTC.4
• BTFSC f,b,a ; Bit Test FileReg, Skip if Clear
▫ BTFSC PORTB.5; Skip the next instruction if bit 0
• BTFSS f,b,a; Bit test FileReg, skip if set
▫ BTFSS PORTB.5; Skip the next instruction if bit set
• BTG f,b,a ; Toggle bit
▫ BTG PORTB,0
• TSTFSZ f,a ; Test FileReg and skip if zero (Byte)
▫ TSTFSZ PORTB; Test PORTB for zero
TABLE Instructions
• TBLRD: Table Read
• Read the contents of Program memory addressed by
the TBLPTR
• If TBLRD* = (P.M.(TBLPTR)) TABLAT;
▫ TBLPTR =No change.
• If TBLRD*+ = (P.M.(TBLPTR)) TABLAT;
▫ (TBLPTR)+1 (TBLPTR)
• If TBLRD*- = (P.M.(TBLPTR)) TABLAT;
▫ (TBLPTR)-1 (TBLPTR)
• TBLRD+* = (TBLPTR)+1 (TBLPTR)
▫ (P.M.(TBLPTR)) TABLAT
Summary (Table processing)
• * no change
• *+ post- increment
• *- post decrement
• +* pre-increment
• Write:
• TBLWT(*,*+,*-,+*)
• (TABLAT) Holding Register
• Holding registers are used to program the contents of
program memory.
Special Features
• 1,00,000 Erase/Write Cycle Enhanced Flash Program
Memory Typical
• 1,000,000 Erase/Write Cycle Data EEPROM Memory
Typical
• Flash/Data EEPROM Retention: 100 Years Typical
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Programmable period from 4 ms to 131s
• Single-Supply 5V In-Circuit Serial Programming (ICSP) via
Two Pins
• In-Circuit Debug (ICD) via Two Pins
Comparison