COMPUTER ARCHITECTURE ORGANIZATION May be located on CPU chip or module
MIDTERM Hit: when the processor fetch word and find it in the
cache, otherwise Miss occurs.
Enumeration If miss occurs the block of the required word
Logical and Bit Manipulation Instructions (consists of fixed number of words) is read from
main memory and saved in the cache.
Clear Because of the locality principle, it likely to find the
Complement next referenced data or instructions in the cache as
AND result of binging the whole block rather than the
OR required word.
EX-OR Memory of size 2n will have n address lines.
Set Carry The main memory is divided into blocks ,each block
Clear Carry consists of k words (i.e. the number of blocks M =
Complement Carry, Enable Interrupt and Disable 2n/k .
Interrupt The cache consists of lines C , each has the same size
as block and C << M.
Cache Design
At any time the cache will holds some blocks which
Size are involved with processor work at that time.
Mapping Function As the number of C is much less than the number of
Replacement Algorithm blocks, each line will have tag to indicate the block it
Write Policy holds.
Block Size
Addressable unit
Number of Caches
Smallest location which can be uniquely addressed
Hierarchy List
Word internally
Registers Cluster on M$ disks
L1 Cache
Line Size - As the block size increases initially the hit ratio
L2 Cache
will increase until certain point at which the hit ratio is
Main memory
decreasing.
Disk cache
Disk Larger block reduces the number of blocks that fit into cache
Optical contents. A small number of blocks results data to be written
Tape shortly after they are fetched.
Arithmetic Instruction Each additional work in large block will be less likely to be
used.
Increment
Decrement Single cache is found initially and with increasing chip
Add density became available some space for on-chip cache.
Subtract
Multiply and
Divide
Multiple Choice
Sequential- Start at the beginning and read through in Order
Access time depends on location of data and previous location
e.g. tape
Direct- Individual blocks have unique address, Access is by
jumping to vicinity plus sequential search, Access time
depends on location and previous location, e.g. disk
Cache
Small amount of fast memory to improve the
performance with cheap price.
Sits between normal main memory and CPU to keep
part of the data and instructions in the main memory.
