  



 
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005

D Extremely Low Offset Voltage . . . 1 µV Max D008, JG, OR P PACKAGE

(TOP VIEW)
D Extremely Low Change on Offset Voltage
With Temperature . . . 0.003 µV/°C Typ CXA CXB
1 8
D Low Input Offset Current IN − 2 7 VDD +
500 pA Max at TA = − 55°C to 125°C IN + 3 6 OUT
D AVD . . . 135 dB Min VDD − 4 5 CLAMP
D CMRR . . . 120 dB Min
D kSVR . . . 110 dB Min D014, J, OR N PACKAGE
(TOP VIEW)
D Single-Supply Operation
D Common-Mode Input Voltage Range CXB 1 14 INT/EXT
Includes the Negative Rail CXA 2 13 CLK IN
D No Noise Degradation With External NC 3 12 CLK OUT
Capacitors Connected to VDD − IN − 4 11 VDD +
IN + 5 10 OUT
description NC 6 9 CLAMP
8 VDD − 7 C RETURN
The TLC2652 and TLC2652A are high-precision
chopper-stabilized operational amplifiers using
Texas Instruments Advanced LinCMOS pro- FK PACKAGE
cess. This process, in conjunction with unique (TOP VIEW)

INT/EXT
chopper-stabilization circuitry, produces opera-

CLK IN
V XA
V XB
tional amplifiers whose performance matches or

NC
exceeds that of similar devices available today.
Chopper-stabilization techniques make possible 3 2 1 20 19
extremely high dc precision by continuously NC 4 18 CLK OUT
nulling input offset voltage even during variations NC 5 17 NC
in temperature, time, common-mode voltage, and IN − 6 16 VDD +
power supply voltage. In addition, low-frequency NC 7 15 NC
noise voltage is significantly reduced. This high IN + 8 14 OUT
9 10 11 12 13
precision, coupled with the extremely high input
VDD−

impedance of the CMOS input stage, makes the C RETURN

NC

NC

TLC2652 and TLC2652A an ideal choice for CLAMP

low-level signal processing applications such as
strain gauges, thermocouples, and other
transducer amplifiers. For applications that NC − No internal connection
require extremely low noise and higher usable
bandwidth, use the TLC2654 or TLC2654A
device, which has a chopping frequency of
10 kHz.
The TLC2652 and TLC2652A input common-mode range includes the negative rail, thereby providing superior
performance in either single-supply or split-supply applications, even at power supply voltage levels as low as
± 1.9 V.
Two external capacitors are required for operation of the device; however, the on-chip chopper-control circuitry
is transparent to the user. On devices in the 14-pin and 20-pin packages, the control circuitry is made accessible
to allow the user the option of controlling the clock frequency with an external frequency source. In addition, the
clock threshold level of the TLC2652 and TLC2652A requires no level shifting when used in the single-supply
configuration with a normal CMOS or TTL clock input.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Advanced LinCMOS is a trademark of Texas Instruments.


 
  !"#$ %" & '## % & "! (')* %" %+ Copyright  1988−2005, Texas Instruments Incorporated
#" '%& " !"#$ %" &(! %" & (# %, %#$& "!
- &  &%#'$ %&
&% # . ## %/+ #" '%" (#"&& 0 "& "% && #*/  *'   (#" '%& "$(* % %" 121 ** ( # $%#& # %&%
%&% 0 "! ** ( # $%#&+ ' *&& "%,#.& "% +  ** "%,# (#" '%& (#" '%"
(#"&& 0 "& "% && #*/  *'  %&% 0 "! ** ( # $%#&+

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1





     


 
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005

description (continued)
Innovative circuit techniques are used on the TLC2652 and TLC2652A to allow exceptionally fast overload
recovery time. If desired, an output clamp pin is available to reduce the recovery time even further.
The device inputs and output are designed to withstand ± 100-mA surge currents without sustaining latch-up.
Additionally the TLC2652 and TLC2652A incorporate internal ESD-protection circuits that prevent functional
failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be
exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric
performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from − 40°C to 85°C. The Q-suffix devices are characterized for operation from − 40°C to125°C.
The M-suffix devices are characterized for operation over the full military temperature range of −55°C to125°C.
AVAILABLE OPTIONS(1)
PACKAGED DEVICES
8 PIN 14 PIN 20 PIN CHIP
VIOmax
TA SMALL CERAMIC PLASTIC SMALL CERAMIC PLASTIC CHIP FORM
AT 25°C
OUTLINE DIP DIP OUTLINE DIP DIP CARRIER (Y)
(D008) (JG) (P) (D014) (J) (N) (FK)
0°C
0 C
1 µV TLC2652AC-8D — TLC2652ACP TLC2652AC-14D — TLC2652ACN —
to TLC2652Y
3 µV TLC2652C-8D — TLC2652CP TLC2652C - 14D — TLC2652CN —
70 C
70°C
40°C
− 40 C
1 µV TLC2652AI-8D — TLC2652AIP TLC2652AI-14D — TLC2652AIN —
to —
3 µV TLC2652A-8D — TLC2652IP TLC2652I-14D — TLC2652IN —
85 C
85°C
40°C
− 40 C
to 3.5 µV TLC2652Q-8D — — — — — — —
125 C
125°C
− 55°C
3 µV TLC2652AM-8D TLC2652AMJG TLC2652AMP TLC2652AM-14D TLC2652AMJ TLC2652AMN TLC2652AMFK
to —
3.5 µV TLC2652M-8D TLC2652MJG TLC2652MP TLC2652M-14D TLC2652MJ TLC2652MN TLC2652MFK
125°C
The D008 and D014 packages are available taped and reeled. Add R suffix to the device type (e.g., TLC2652AC-8DR). Chips are tested at 25°C.
NOTE (1): For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.

functional block diagram

DISTRIBUTION OF TLC2652
INPUT OFFSET VOLTAGE
VDD +
7 36
150 Units Tested From 1 Wafer Lot
Clamp 5 32 VDD ± = ± 5 V
CLAMP
Circuit TA = 25°C
3 6
IN + + OUT 28 N Package
IN − −
Percentage of Units − %

2 CIC A 24
B B Main

A 20
+ Compensation-
− Biasing 16
Null A B Circuit
12
External Components
CXA CXB
8

4
4 8
0
VDD − C RETURN
−3 −2 −1 0 1 2 3
Pin numbers shown are for the D (14 pin), JG, and N packages. VIO − Input Offset Voltage − µV

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





     


 
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005

TLC2652Y chip information

This chip, when properly assembled, displays characteristics similar to the TLC2652C. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with
conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

(13) (12) (11) (10) (9)

(14)

(8)
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
80 TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
(1)
PIN (7) IS INTERNALLY CONNECTED
TO BACK SIDE OF CHIP.
FOR THE PINOUT, SEE THE FUNCTIONAL
BLOCK DIAGRAM.

(2) (4) (5) (7)

90

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     


 
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage VDD + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Supply voltage VDD − (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V
Input voltage, VI (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 8 V
Voltage range on CLK IN and INT/EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD − to VDD − + 5.2 V
Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Current into CLK IN and INT/EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 °C to 150 °C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or P package . . . . . . . . . . . . . 260 °C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or JG package . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD + and VDD − .
2. Differential voltages are at IN+ with respect to IN −.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.

DISSIPATION RATING TABLE

TA ≤ 25°C
25 C DERATING FACTOR TA = 70
70°C
C TA = 85
85°C
C TA = 125
125°C
C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
D008 725 mV 5.8 mW/°C 464 mW 377 mW 145 mW
D014 950 mV 7.6 mW/°C 608 mW 494 mW 190 mW
FK 1375 mV 11.0 mW/°C 880 mW 715 mW 275 mW
J 1375 mV 11.0 mW/°C 880 mW 715 mW 275 mW
JG 1050 mV 8.4 mW/°C 672 mW 546 mW 210 mW
N 1575 mV 12.6 mW/°C 1008 mW 819 mW 315 mW
P 1000 mV 8.0 mW/°C 640 mW 520 mW 200 mW

recommended operating conditions

C SUFFIX I SUFFIX Q SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
Supply voltage, VDD ± ± 1.9 ±8 ± 1.9 ±8 ± 1.9 ±8 ± 1.9 ±8 V
Common-mode input voltage, VIC VDD − VDD + − 1.9 VDD − VDD + − 1.9 VDD − VDD + − 1.9 VDD − VDD + − 1.9 V
Clock input voltage VDD − VDD − + 5 VDD − VDD − + 5 VDD − VDD − + 5 VDD − VDD − + 5 V
Operating free-air temperature, TA 0 70 −40 85 −40 125 −55 125 °C

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electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted)

TLC2652C TLC2652AC
PARAMETER TEST CONDITIONS TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 0.6 3 0.5 1
VIO Input offset voltage µV
V
Full range 4.35 2.35
Temperature coefficient of
αVIO Full range 0.003 0.03 0.003 0.03 µV/°C
V/°C
input offset voltage
Input offset voltage long-term
VIC = 0, RS = 50 Ω 25°C 0.003 0.06 0.003 0.02 µV/mo
drift (see Note 4)
25°C 2 60 2 60
IIO Input offset current pA
Full range 100 100
25°C 4 60 4 60
IIB Input bias current pA
Full range 100 100
−5 −5
Common-mode input voltage
VICR RS = 50 Ω Full range to to V
range
3.1 3.1
Maximum positive peak 25°C 4.7 4.8 4.7 4.8
VOM + RL = 10 kΩ
kΩ, See Note 5 V
output voltage swing Full range 4.7 4.7
Maximum negative peak 25°C −4.7 −4.9 −4.7 −4.9
VOM − RL = 10 kΩ
kΩ, See Note 5 V
output voltage swing Full range −4.7 −4.7
Large-signal differential 25°C 120 150 135 150
AVD VO = ± 4 V, RL = 10 kΩ dB
voltage amplification Full range 120 130
fch Internal chopping frequency 25°C 450 450 Hz
25°C 25 25
Clamp on-state current RL = 100 kΩ µA
A
Full range 25 25
25°C 100 100
Clamp off-state current VO = − 4 V to 4 V pA
Full range 100 100
Common-mode rejection VO = 0, VIC = VICRmin, 25°C 120 140 120 140
CMRR dB
ratio RS = 50 Ω Full range 120 120
Supply-voltage rejection ratio VDD ± = ± 1.9 V to ± 8 V, 25°C 110 135 110 135
kSVR dB
(∆VDD ± /∆VIO) VO = 0, RS = 50 Ω Full range 110 110
25°C 1.5 2.4 1.5 2.4
IDD Supply current mA
Full range 2.5 2.5
† Full range is 0° to 70°C.
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.

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operating characteristics specified free-air temperature, VDD± = ±5 V

TEST TLC2652C TLC2652AC
PARAMETER TA† UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX
25°C 2 2.8 2 2.8
SR + Positive slew rate at unity gain VO = ± 2.3 V, V/ s
V/µs
Full range 1.5 1.5
RL = 10 kΩ,
CL = 100 pF 25°C 2.3 3.1 2.3 3.1
SR − Negative slew rate at unity gain V/ s
V/µs
Full range 1.8 1.8
Equivalent input noise voltage f = 10 Hz 25°C 94 94 140
Vn nV/√Hz
(see Note 6) f = 1 kHz 25°C 23 23 35
Peak-to-peak equivalent input f = 0 to 1 Hz 25°C 0.8 0.8
VN(PP) µV
V
noise voltage f = 0 to 10 Hz 25°C 2.8 2.8
In Equivalent input noise current f = 10 kHz 25°C 0.004 0.004 fA/√Hz
f = 10 kHz,
Gain-bandwidth product RL = 10 kΩ, 25°C
25 C 1.9 1.9 MHz
CL = 100 pF
RL = 10 kΩ,
φm Phase margin at unity gain 25°C 48° 48°
CL = 100 pF
† Full range is 0° to 70°C.
NOTE 6: This parameter is tested on a sample basis for the TLC2652A. For other test requirements, please contact the factory. This statement
has no bearing on testing or nontesting of other parameters.

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





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electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted)

TLC2652I TLC2652AI
PARAMETER TEST CONDITIONS TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 0.6 3 0.5 1
VIO Input offset voltage µV
V
Full range 4.95 2.95
Temperature coefficient of
αVIO Full range 0.003 0.03 0.003 0.03 µV/°C
V/°C
input offset voltage
Input offset voltage
VIC = 0, RS = 50 Ω 25°C 0.003 0.06 0.003 0.02 µV/mo
long-term drift (see Note 4)
25°C 2 60 2 60
IIO Input offset current pA
Full range 150 150
25°C 4 60 4 60
IIB Input bias current pA
Full range 150 150
−5 −5
Common-mode input
VICR RS = 50 Ω Full range to to V
voltage range
3.1 3.1
Maximum positive peak 25°C 4.7 4.8 4.7 4.8
VOM + kΩ
RL = 10 kΩ, See Note 5 V
output voltage swing Full range 4.7 4.7
Maximum negative peak 25°C −4.7 −4.9 −4.7 −4.9
VOM − kΩ
RL = 10 kΩ, See Note 5 V
output voltage swing Full range −4.7 −4.7
Large-signal differential 25°C 120 150 135 150
AVD VO = ± 4 V, RL = 10 kΩ dB
voltage amplification Full range 120 125
Internal chopping frequency 25°C 450 450 Hz
25°C 25 25
Clamp on-state current RL = 100 kΩ µA
A
Full range 25 25
25°C 100 100
Clamp off-state current VO = − 4 V to 4 V pA
Full range 100 100
Common-mode rejection VO = 0, VIC = VICRmin, 25°C 120 140 120 140
CMRR dB
ratio RS = 50 Ω Full range 120 120
Supply-voltage rejection VDD ± = ± 1.9 V to ± 8 V, 25°C 110 135 110 135
kSVR dB
ratio (∆VDD ± /∆VIO) VO = 0, RS = 50 Ω Full range 110 110
25°C 1.5 2.4 1.5 2.4
IDD Supply current VO = 0, No load mA
Full range 2.5 2.5
† Full range is − 40° to 85°C.
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.

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operating characteristics at specified free-air temperature, VDD ± = ±5 V

TEST TLC2652I TLC2652AI
PARAMETER TA† UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX
25°C 2 2.8 2 2.8
SR + Positive slew rate at unity gain VO = ± 2.3 V, V/ s
V/µs
Full range 1.4 1.4
RL = 10 kΩ,
CL = 100 pF 25°C 2.3 3.1 2.3 3.1
SR − Negative slew rate at unity gain V/ s
V/µs
Full range 1.7 1.7
Equivalent input noise voltage f = 10 Hz 25°C 94 94 140
Vn nV/√Hz
(see Note 6) f = 1 kHz 25°C 23 23 35
Peak-to-peak equivalent input f = 0 to 1 Hz 25°C 0.8 0.8
VN(PP) µV
V
noise voltage f = 0 to 10 Hz 25°C 2.8 2.8
In Equivalent input noise current f = 1 kHz 25°C 0.004 0.004 pA/√Hz
f = 10 kHz,
Gain-bandwidth product RL = 10 kΩ, 25°C
25 C 1.9 1.9 MHz
CL = 100 pF
RL = 10 kΩ,
φm Phase margin at unity gain 25°C 48° 48°
CL = 100 pF
† Full range is − 40° to 85°C.
NOTE 6: This parameter is tested on a sample basis for the TLC2652A. For other test requirements, please contact the factory. This statement
has no bearing on testing or nontesting of other parameters.

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electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted)

TLC2652Q
TLC2652AM
PARAMETER TEST CONDITIONS TA† TLC2652M UNIT
MIN TYP MAX MIN TYP MAX
Input offset voltage 25°C 0.6 3.5 0.5 3
VIO µV
V
(see Note 7) Full range 10 8
Temperature coefficient of
αVIO Full range 0.003 0.03∗ 0.003 0.03∗ µV/°C
V/°C
input offset voltage
Input offset voltage
VIC = 0, RS = 50 Ω 25°C 0.003 0.06∗ 0.003 0.02∗ µV/mo
long-term drift (see Note 4)
25°C 2 60 2 60
IIO Input offset current pA
Full range 500 500
25°C 4 60 4 60
IIB Input bias current pA
Full range 500 500
−5 −5
Common-mode input
VICR RS = 50 Ω Full range to to V
voltage range
3.1 3.1
Maximum positive peak 25°C 4.7 4.8 4.7 4.8
VOM + kΩ
RL = 10 kΩ, See Note 5 V
output voltage swing Full range 4.7 4.7
Maximum negative peak 25°C −4.7 −4.9 −4.7 −4.9
VOM − kΩ
RL = 10 kΩ, See Note 5 V
output voltage swing Full range −4.7 −4.7
Large-signal differential 25°C 120 150 135 150
AVD VO = ± 4 V, RL = 10 kΩ dB
voltage amplification Full range 120 120
fch Internal chopping frequency 25°C 450 450 Hz
25°C 25 25
Clamp on-state current VO = − 5 V to 5 V µA
A
Full range 25 25
25°C 100 100
Clamp off-state current RL = 100 kΩ pA
Full range 500 500
Common-mode rejection VO = 0, VIC = VICRmin, 25°C 120 140 120 140
CMRR dB
ratio RS = 50 Ω Full range 120 120
Supply-voltage rejection VDD ± = ± 1.9 V to ± 8 V, 25°C 110 135 110 135
kSVR dB
ratio (∆VDD ± /∆VIO) VO = 0, RS = 50 Ω Full range 110 110
25°C 1.5 2.4 1.5 2.4
IDD Supply current VO = 0, No load mA
Full range 2.5 2.5
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
† Full range is − 40° to 125°C for Q suffix, − 55° to 125°C for M suffix.
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.
7. This parameter is not production tested. Thermocouple effects preclude measurement of the actual VIO of these devices in high
speed automated testing. VIO is measured to a limit determined by the test equipment capability at the temperature extremes. The
test ensures that the stabilization circuitry is performing properly.

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operating characteristics at specified free-air temperature, VDD ± = ±5 V

TLC2652Q
TLC2652M
PARAMETER TEST CONDITIONS TA† TLC2652AM UNIT
MIN TYP MAX
25°C 2 2.8
SR + Positive slew rate at unity gain VO = ± 2.3 V, V/ s
V/µs
Full range 1.3
RL = 10 kΩ,
CL = 100 pF 25°C 2.3 3.1
SR − Negative slew rate at unity gain V/ s
V/µs
Full range 1.6
f = 10 Hz 25°C 94
Vn Equivalent input noise voltage nV/√Hz
f = 1 kHz 25°C 23
f = 0 to 1 Hz 25°C 0.8
VN(PP) Peak-to-peak equivalent input noise voltage µV
V
f = 0 to 10 Hz 25°C 2.8
In Equivalent input noise current f = 1 kHz 25°C 0.004 pA/√Hz
f = 10 kHz,
Gain-bandwidth product RL = 10 kΩ, 25°C 1.9 MHz
CL = 100 pF
RL = 10 kΩ,
φm Phase margin at unity gain 25°C 48°
CL = 100 pF
† Full range is − 40° to 125°C for the Q suffix, − 55° to 125°C for the M suffix.

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electrical characteristics at VDD± = ±5 V, TA = 25°C (unless otherwise noted)

TLC2652Y
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
VIO Input offset voltage 0.6 3 µV
Input offset voltage long-term drift (see Note 4) 0.003 0.006 µV/mo
VIC = 0, RS = 50 Ω
IIO Input offset current 2 60 pA
IIB Input bias current 4 60 pA
−5
VICR Common-mode input voltage range RS = 50 Ω to V
3.1
VOM + Maximum positive peak output voltage swing RL = 10 kΩ, See Note 5 4.7 4.8 V
VOM − Maximum negative peak output voltage swing RL = 10 kΩ, See Note 5 −4.7 −4.9 V
AVD Large-signal differential voltage amplification VO = ± 4 V, RL = 10 kΩ 120 150 dB
fch Internal chopping frequency 450 Hz
Clamp on-state current RL = 100 kΩ 25 µA
Clamp off-state current VO = − 4 V to 4 V 100 pA
VO = 0, VIC = VICRmin,
CMRR Common-mode rejection ratio 120 140 dB
RS = 50 Ω
VDD ± = ± 1.9 V to ± 8 V,
kSVR Supply-voltage rejection ratio (∆VDD ± /∆VIO) 110 135 dB
RS = 50 Ω VO = 0,
IDD Supply current VO = 0, No load 1.5 2.4 mA
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.

operating characteristics at VDD± = ±5 V, TA = 25°C

TLC2652Y
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
SR + Positive slew rate at unity gain VO = ± 2.3 V, RL = 10 kΩ, 2 2.8 V/µs
SR − Negative slew rate at unity gain CL = 100 pF 2.3 3.1 V/µs
f = 10 Hz 94
Vn Equivalent input noise voltage nV/√Hz
f = 1 kHz 23
f = 0 to 1 Hz 0.8
VN(PP) Peak-to-peak equivalent input noise voltage µV
V
f = 0 to 10 Hz 2.8
In Equivalent input noise current f = 1 kHz pA/√Hz
f = 10 kHz, RL = 10 kΩ,
Gain-bandwidth product 1.9 MHz
CL = 100 pF
φm Phase margin at unity gain RL = 10 kΩ, CL = 100 pF 48°

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TYPICAL CHARACTERISTICS

Table of Graphs
FIGURE
VIO Normalized input offset voltage vs Chopping frequency 1
vs Common-mode input voltage 2
IIB Input bias current vs Chopping frequency 3
vs Free-air temperature 4
vs Chopping frequency 5
IIO Input offset current
vs Free-air temperature 6
Clamp current vs Output voltage 7
V(OPP) Maximum peak-to-peak output voltage vs Frequency 8
vs Output current 9, 10
VOM Maximum peak output voltage
vs Free-air temperature 11, 12
vs Frequency 13
AVD Large-signal differential voltage amplification
vs Free-air temperature 14
vs Supply voltage 15
Chopping frequency
vs Free-air temperature 16
vs Supply voltage 17
IDD Supply current
vs Free-air temperature 18
vs Supply voltage 19
IOS Short-circuit output current
vs Free-air temperature 20
vs Supply voltage 21
SR Slew rate
vs Free-air temperature 22
Small-signal 23
Voltage-follower pulse response
Large-signal 24
VN(PP) Peak-to-peak equivalent input noise voltage vs Chopping frequency 25, 26
Vn Equivalent input noise voltage vs Frequency 27
vs Supply voltage 28
Gain-bandwidth product
vs Free-air temperature 29
vs Supply voltage 30
φm Phase margin vs Free-air temperature 31
vs Load capacitance 32
Phase shift vs Frequency 13

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SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005

TYPICAL CHARACTERISTICS†

NORMALIZED INPUT OFFSET VOLTAGE INPUT BIAS CURRENT

vs vs
CHOPPING FREQUENCY COMMON-MODE INPUT VOLTAGE
70 25
VDD ± = ± 5 V VDD ± = ± 5 V
60 VIC = 0 TA = 25°C
TA = 25°C
uV
VIO − Normalized Input Offset − µV

20

I IB − Input Bias Current − pA

50

40
15
30

20 10

IIB
10
VIO

5
0

−10 0
100 1k 10 k 100 k −5 −4 −3 −2 −1 0 1 2 3 4 5
Chopping Frequency − Hz VIC − Common-Mode Input Voltage − V

Figure 1 Figure 2

INPUT BIAS CURRENT INPUT BIAS CURRENT

vs vs
CHOPPING FREQUENCY FREE-AIR TEMPERATURE
70 100
VDD ± = ± 5 V
VDD ± = ± 5 V VO = 0
VIC = 0 VIC = 0
60
TA = 25°C
I IB − Input Bias Current − pA
I IB − Input Bias Current − pA

50

40
10
30

20
IIB
IIB

10

0 1
100 1k 10 k 100 k 25 45 65 85 105 125
Chopping Frequency − Hz TA − Free-Air Temperature − °C

Figure 3 Figure 4

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TYPICAL CHARACTERISTICS†

INPUT OFFSET CURRENT INPUT OFFSET CURRENT

vs vs
CHOPPING FREQUENCY FREE-AIR TEMPERATURE
25 10
VDD ± = ± 5 V VDD ± = ± 5 V
VIC = 0 VIC = 0
TA = 25°C
20 8
IO − Input Offset Current − pA

IO − Input Offset Current − pA

15 6

10 4
IIIO

IIIO
5 2

0 0
100 1k 10 k 100 k 25 45 65 85 105 125
Chopping Frequency − Hz TA − Free-Air Temperature − °C

Figure 5 Figure 6

MAXIMUM PEAK-TO-PEAK OUTPUT

CLAMP CURRENT VOLTAGE
vs vs
OUTPUT VOLTAGE FREQUENCY
V O(PP)− Maximum Peak-to-Peak Output Voltage − V

100 µA 10
VDD ± = ± 5 V
10 µA TA = 25°C

8
1 µA
Positive Clamp Current TA = − 55°C
|Clamp Current|

100 nA
6

10 nA
TA = 125°C

1 nA 4

100 pA
2
Negative Clamp Current
10 pA
VDD ± = ± 5 V
VO(PP)

RL = 10 kΩ
1 pA 0
4 4.2 4.4 4.6 4.8 5 100 1k 10 k 1M
|VO| − Output Voltage − V f − Frequency − Hz

Figure 7 Figure 8

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TYPICAL CHARACTERISTICS†

MAXIMUM PEAK OUTPUT VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE

vs vs
OUTPUT CURRENT OUTPUT CURRENT
5 7.5
VDD ± = ± 5 V VDD ± = ± 7.5 V
|VOM − Maximum Peak Output Voltage − V

|VOM − Maximum Peak Output Voltage − V

TA = 25°C TA = 25°C
4.8
VOM + 7.3
VOM −
VOM + VOM −
4.6

7.1

4.4

6.9
4.2
|VOM|

|VOM|
4 6.7
0 0.4 0.8 1.2 1.6 2 0 0.4 0.8 1.2 1.6 2
|IO| − Output Current − mA |IO| − Output Current − mA

Figure 9 Figure 10

MAXIMUM PEAK OUTPUT VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE

vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
5 8
VOM − Maximum Peak Output Voltage − V

VOM − Maximum Peak Output Voltage − V

2.5 4

VDD ± = ± 5 V VDD ± = ± 7.5 V

0 RL = 10 kΩ 0 RL = 10 kΩ

−2.5
−4
VOM

VOM

−5 −8
−75 −50 −25 0 25 50 75 100 125 −75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C

Figure 11 Figure 12

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TYPICAL CHARACTERISTICS†
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
120 60°

AVD− Large-Signal Differential 100 Phase Shift 80°

Voltage Amplification − dB

80 100°
AVD
60 120°

Phase Shift
40 140°

ÁÁ
20 160°

ÁÁ
AVD

0 180°

ÁÁ
VDD ± = ± 5 V
−20 RL = 10 kΩ
CL = 100 pF 200°
TA = 25°C
−40 220°
10 100 1k 10 k 100 k 1M 10 M
f − Frequency − Hz

Figure 13

LARGE-SIGNAL DIFFERENTIAL VOLTAGE

AMPLIFICATION
vs
FREE-AIR TEMPERATURE
155
VDD ± = ± 7.5 V
RL = 10 kΩ
VO = ± 4 V
AVD− Large-Signal Differential
Voltage Amplification − dB

150

145

ÁÁ
ÁÁ
AVD

140

ÁÁ
135
−75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C

Figure 14

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TYPICAL CHARACTERISTICS†

CHOPPING FREQUENCY CHOPPING FREQUENCY

vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
540 460
VDD ± = ± 5 V
TA = 25°C

520 450

Chopping Frequency − kHz

Chopping Frequency − kHz

500 440

480 430

460 420

440 410

420 400
0 1 2 3 4 5 6 7 8 −75 −50 −25 0 25 50 75 100 125
|VDD ±| − Supply Voltage − V TA − Free-Air Temperature − °C

Figure 15 Figure 16

SUPPLY CURRENT SUPPLY CURRENT

vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
2 2
VO = 0
VDD ± = ± 7.5 V
No Load
1.6 1.6 VDD ± = ± 5 V
DD − Supply Current − mA
DD − Supply Current − mA

1.2 TA = 25°C 1.2 VDD ± = ± 2.5 V

TA = − 55°C
0.8 0.8
IIDD

TA = 125°C
IIDD

0.4 0.4

VO = 0
No Load
0 0
0 1 2 3 4 5 6 7 8 −75 −50 −25 0 25 50 75 100 125
|VDD ±| − Supply Voltage − V TA − Free-Air Temperature − °C

Figure 17 Figure 18

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TYPICAL CHARACTERISTICS†

SHORT-CIRCUIT OUTPUT CURRENT SHORT-CIRCUIT OUTPUT CURRENT

vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
12 15
VO = 0 VDD ± = ± 5 V
TA = 25°C VO = 0
I OS − Short-Circuit Output Current − mA

I OS − Short-Circuit Output Current − mA

8 10

4 5
VID = − 100 mV
VID = − 100 mV
0 0

−4 −5
VID = 100 mV

−8 −10
IOS

VID = 100 mV IOS

−12 −15
0 1 2 3 4 5 6 7 8 −75 −50 −25 0 25 50 75 100 125
|VDD ±| − Supply Voltage − V TA − Free-Air Temperature − °C

Figure 19 Figure 20

SLEW RATE SLEW RATE

vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
4 4
VDD ± = ± 5 V
SR − RL = 10 kΩ
SR − CL = 100 pF

3 3
SR − Slew Rate − V?us
SR − Slew Rate − V?us

V/ µ s
V/ µ s

SR +
SR +

2 2

1 1

RL = 10 kΩ
CL = 100 pF
TA = 25°C
0 0
0 1 2 3 4 5 6 7 8 −75 −50 −25 0 25 50 75 100 125
|VDD ±| − Supply Voltage − V TA − Free-Air Temperature − °C

Figure 21 Figure 22

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TYPICAL CHARACTERISTICS

VOLTAGE-FOLLOWER VOLTAGE-FOLLOWER
SMALL-SIGNAL LARGE-SIGNAL
PULSE RESPONSE PULSE RESPONSE
100 4
VDD ± = ± 5 V
RL = 10 kΩ
75 3
CL = 100 pF
TA = 25°C
50 2
VO − Output Voltage − mV

VO − Output Voltage − V
25 VDD ± = ± 5 V 1
RL = 10 kΩ
CL = 100 pF
0 TA = 25°C 0

−25 −1

VO
VO

−50 −2

−75 −3

−100 −4
0 1 2 3 4 5 6 7 0 5 10 15 20 25 30 35 40
t − Time − µs t − Time − µs

Figure 23 Figure 24

PEAK-TO-PEAK INPUT NOISE VOLTAGE PEAK-TO-PEAK INPUT NOISE VOLTAGE

vs vs
CHOPPING FREQUENCY CHOPPING FREQUENCY
1.8 5
µV

uV
VN(PP) − Peak-to-Peak Input Noise Voltage − µV
VN(PP) − Peak-to-Peak Input Noise Voltage −uV

VDD ± = ± 5 V VDD ± = ± 5 V
1.6 RS = 20 Ω RS = 20 Ω
f = 0 to 1 Hz f = 0 to 10 Hz
1.4 TA = 25°C 4
TA = 25°C

1.2
3
1

0.8
2
0.6

0.4
1
VN(PP)
VN(PP)

0.2

0 0
0 2 4 6 8 10 0 2 4 6 8 10
fch − Chopping Frequency − kHz fch − Chopping Frequency − kHz

Figure 25 Figure 26

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TYPICAL CHARACTERISTICS†

EQUIVALENT INPUT NOISE VOLTAGE GAIN-BANDWIDTH PRODUCT

vs vs
FREQUENCY SUPPLY VOLTAGE
100 2.1
nV/HzHz

RL = 10 kΩ
CL = 100 pF
n − Equivalent Input Noise Voltage − nV/

80 TA = 25°C

Gain-Bandwidth Product − MHz

2
60

40
1.9

20
VDD ± = ± 5 V
RS = 20 Ω
Vn
V

TA = 25°C
0 1.8
1 10 100 1k 0 1 2 3 4 5 6 7 8
f − Frequency − Hz |VCC ±| − Supply Voltage − V
Figure 27 Figure 28

GAIN-BANDWIDTH PRODUCT PHASE MARGIN

vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
2.6 50°
VDD ± = ± 5 V RL = 10 kΩ
RL = 10 kΩ CL = 100 pF
2.4 CL = 100 pF TA = 25°C
48°
Gain-Bandwidth Product − MHz

φ m − Phase Margin

2.2
46°

44°
om

1.8

42°
1.4

1.2 40°
−75 −50 −25 0 25 50 75 100 125 0 1 2 3 4 5 6 7 8
TA − Free-Air Temperature − °C |VCC ±| − Supply Voltage − V

Figure 29 Figure 30

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TYPICAL CHARACTERISTICS†

PHASE MARGIN PHASE MARGIN

vs vs
FREE-AIR TEMPERATURE LOAD CAPACITANCE
50° 60°
VDD ± = ± 5 V
RL = 10 kΩ
50° TA = 25°C
48°

40°

φ m − Phase Margin
φ m − Phase Margin

46°

30°

44°

om
om

20°

42°
VDD ± = ± 5 V 10°
RL = 10 kΩ
CL = 100 pF
40° 0°
−75 −50 −25 0 25 50 75 100 125 0 200 400 600 800 1000
TA − Free-Air Temperature − °C CL − Load Capacitance − pF

Figure 31 Figure 32
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

APPLICATION INFORMATION

capacitor selection and placement

The two important factors to consider when selecting external capacitors CXA and CXB are leakage and
dielectric absorption. Both factors can cause system degradation, negating the performance advantages
realized by using the TLC2652.
Degradation from capacitor leakage becomes more apparent with the increasing temperatures. Low-leakage
capacitors and standoffs are recommended for operation at TA = 125°C. In addition, guard bands are
recommended around the capacitor connections on both sides of the printed circuit board to alleviate problems
caused by surface leakage on circuit boards.
Capacitors with high dielectric absorption tend to take several seconds to settle upon application of power, which
directly affects input offset voltage. In applications where fast settling of input offset voltage is needed, it is
recommended that high-quality film capacitors, such as mylar, polystyrene, or polypropylene, be used. In other
applications, however, a ceramic or other low-grade capacitor can suffice.
Unlike many choppers available today, the TLC2652 is designed to function with values of CXA and CXB in the
range of 0.1 µF to 1 µF without degradation to input offset voltage or input noise voltage. These capacitors
should be located as close as possible to the CXA and CXB pins and returned to either VDD − or C RETURN. On
many choppers, connecting these capacitors to VDD − causes degradation in noise performance. This problem
is eliminated on the TLC2652.

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APPLICATION INFORMATION

internal/external clock
The TLC2652 has an internal clock that sets the chopping frequency to a nominal value of 450 Hz. On 8-pin
packages, the chopping frequency can only be controlled by the internal clock; however, on all 14-pin packages
and the 20-pin FK package, the device chopping frequency can be set by the internal clock or controlled
externally by use of the INT/EXT and CLK IN pins. To use the internal 450-Hz clock, no connection is necessary.
If external clocking is desired, connect INT/EXT to VDD − and the external clock to CLK IN. The external clock
trip point is 2.5 V above the negative rail; however, CLK IN can be driven from the negative rail to 5 V above
the negative rail. If this level is exceeded, damage could occur to the device unless the current into CLK IN is
limited to ± 5 mA. When operating in the single-supply configuration, this feature allows the TLC2652 to be driven
directly by 5-V TTL and CMOS logic. A divide-by-
two frequency divider interfaces with CLK IN and 0

V O − Output Voltage − V
VDD ± = ± 5 V
sets the clock chopping frequency. The duty cycle
TA = 25° C
of the external clock is not critical but should be
kept between 30% and 60%.

overload recovery/output clamp

−5
VO
When large differential input voltage conditions
are applied to the TLC2652, the nulling loop
VII − Input Voltage − mV

attempts to prevent the output from saturating by

0
driving CXA and CXB to internally-clamped voltage
levels. Once the overdrive condition is removed,
a period of time is required to allow the built-up
charge to dissipate. This time period is defined as
overload recovery time (see Figure 33). Typical
overload recovery time for the TLC2652 is
−50
V

significantly faster than competitive products;

0 10 20 30 40 50 60 70 80
however, if required, this time can be reduced
t − Time − ms
further by use of internal clamp circuitry
accessible through CLAMP if required. Figure 33. Overload Recovery

The clamp is a switch that is automatically activated when the output is approximately 1 V from either supply
rail. When connected to the inverting input (in parallel with the closed-loop feedback resistor), the closed-loop
gain is reduced, and the TLC2652 output is prevented from going into saturation. Since the output must source
or sink current through the switch (see Figure 7), the maximum output voltage swing is slightly reduced.

thermoelectric effects
To take advantage of the extremely low offset voltage drift of the TLC2652, care must be taken to compensate
for the thermoelectric effects present when two dissimilar metals are brought into contact with each other (such
as device leads being soldered to a printed circuit board). Dissimilar metal junctions can produce thermoelectric
voltages in the range of several microvolts per degree Celsius (orders of magnitude greater than the 0.01-µV/°C
typical of the TLC2652).
To help minimize thermoelectric effects, careful attention should be paid to component selection and
circuit-board layout. Avoid the use of nonsoldered connections (such as sockets, relays, switches, etc.) in the
input signal path. Cancel thermoelectric effects by duplicating the number of components and junctions in each
device input. The use of low-thermoelectric-coefficient components, such as wire-wound resistors, is also
beneficial.

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APPLICATION INFORMATION

latch-up avoidance
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2652 inputs
and output are designed to withstand −100-mA surge currents without sustaining latch-up; however, techniques
to reduce the chance of latch-up should be used whenever possible. Internal protection diodes should not, by
design, be forward biased. Applied input and output voltages should not exceed the supply voltage by more than
300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients
should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close
to the device as possible.
The current path established if latch-up occurs is usually between the supply rails and is limited only by the
impedance of the power supply and the forward resistance of the parasitic thyristor. The chance of latch-up
occurring increases with increasing temperature and supply voltage.

electrostatic discharge protection

The TLC2652 incorporates internal ESD-protection circuits that prevent functional failures at voltages at or
below 2000 V. Care should be exercised in handling these devices, as exposure to ESD may result in
degradation of the device parametric performance.

theory of operation
Chopper-stabilized operational amplifiers offer the best dc performance of any monolithic operational amplifier.
This superior performance is the result of using two operational amplifiers, a main amplifier and a nulling
amplifier, plus oscillator-controlled logic and two external capacitors to create a system that behaves as a single
amplifier. With this approach, the TLC2652 achieves submicrovolt input offset voltage, submicrovolt noise
voltage, and offset voltage variations with temperature in the nV/°C range.
The TLC2652 on-chip control logic produces two dominant clock phases: a nulling phase and an amplifying
phase. The term chopper-stabilized derives from the process of switching between these two clock phases.
Figure 34 shows a simplified block diagram of the TLC2652. Switches A and B are make-before-break types.
During the nulling phase, switch A is closed shorting the nulling amplifier inputs together and allowing the nulling
amplifier to reduce its own input offset voltage by feeding its output signal back to an inverting input node.
Simultaneously, external capacitor CXA stores the nulling potential to allow the offset voltage of the amplifier to
remain nulled during the amplifying phase.
Main Amplifier

IN + +
VO
IN − −
B
CXB
B
A
+
VDD −
−
Null
Amplifier A
CXA

Figure 34. TLC2652 Simplified Block Diagram

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APPLICATION INFORMATION

theory of operation (continued)

During the amplifying phase, switch B is closed connecting the output of the nulling amplifier to a noninverting
input of the main amplifier. In this configuration, the input offset voltage of the main amplifier is nulled. Also,
external capacitor CXB stores the nulling potential to allow the offset voltage of the main amplifier to remain
nulled during the next nulling phase.
This continuous chopping process allows offset voltage nulling during variations in time and temperature over
the common-mode input voltage range and power supply range. In addition, because the low-frequency signal
path is through both the null and main amplifiers, extremely high gain is achieved.
The low-frequency noise of a chopper amplifier depends on the magnitude of the component noise prior to
chopping and the capability of the circuit to reduce this noise while chopping. The use of the Advanced LinCMOS
process, with its low-noise analog MOS transistors and patent-pending input stage design, significantly reduces
the input noise voltage.
The primary source of nonideal operation in chopper-stabilized amplifiers is error charge from the switches. As
charge imbalance accumulates on critical nodes, input offset voltage can increase, especially with increasing
chopping frequency. This problem has been significantly reduced in the TLC2652 by use of a patent-pending
compensation circuit and the Advanced LinCMOS process.
The TLC2652 incorporates a feed-forward design that ensures continuous frequency response. Essentially, the
gain magnitude of the nulling amplifier and compensation network crosses unity at the break frequency of the
main amplifier. As a result, the high-frequency response of the system is the same as the frequency response
of the main amplifier. This approach also ensures that the slewing characteristics remain the same during both
the nulling and amplifying phases.

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 6-Apr-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9089501MPA ACTIVE CDIP JG 8 50 Non-RoHS SNPB N / A for Pkg Type -55 to 125 9089501MPA Samples
& Green TLC2652M
5962-9089503MCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9089503MC Samples
& Green A
TLC2652AMJB
5962-9089503MPA ACTIVE CDIP JG 8 50 Non-RoHS SNPB N / A for Pkg Type -55 to 125 9089503MPA Samples
& Green TLC2652AM
TLC2652AC-14D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 2652AC Samples

TLC2652AC-8D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 2652AC Samples

TLC2652ACN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC2652ACN Samples

TLC2652ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC2652AC Samples

TLC2652AI-14D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2652AI Samples

TLC2652AI-8D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2652AI Samples

TLC2652AI-8DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2652AI Samples

TLC2652AIN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC2652AIN Samples

TLC2652AIP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC2652AI Samples

TLC2652AMJB ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9089503MC Samples
& Green A
TLC2652AMJB
TLC2652AMJGB ACTIVE CDIP JG 8 50 Non-RoHS SNPB N / A for Pkg Type -55 to 125 9089503MPA Samples
& Green TLC2652AM
TLC2652C-8D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 2652C Samples

TLC2652C-8DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 2652C Samples

TLC2652CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type TLC2652CN Samples

TLC2652CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type TLC2652CP Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Apr-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TLC2652I-8D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 2652I Samples

TLC2652I-8DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 2652I Samples

TLC2652MJG ACTIVE CDIP JG 8 50 Non-RoHS SNPB N / A for Pkg Type -55 to 125 TLC2652MJG Samples
& Green
TLC2652MJGB ACTIVE CDIP JG 8 50 Non-RoHS SNPB N / A for Pkg Type -55 to 125 9089501MPA Samples
& Green TLC2652M
TLC2652Q-8D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T2652Q Samples

TLC2652Q-8DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM T2652Q Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Apr-2024

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC2652A, TLC2652AM :

• Catalog : TLC2652A
• Military : TLC2652AM

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC2652AI-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC2652C-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC2652I-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC2652AI-8DR SOIC D 8 2500 353.0 353.0 32.0
TLC2652C-8DR SOIC D 8 2500 353.0 353.0 32.0
TLC2652I-8DR SOIC D 8 2500 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TLC2652AC-14D D SOIC 14 50 505.46 6.76 3810 4
TLC2652AC-8D D SOIC 8 75 505.46 6.76 3810 4
TLC2652AC-8D D SOIC 8 75 507 8 3940 4.32
TLC2652ACN N PDIP 14 25 506 13.97 11230 4.32
TLC2652ACP P PDIP 8 50 506 13.97 11230 4.32
TLC2652AI-14D D SOIC 14 50 505.46 6.76 3810 4
TLC2652AI-8D D SOIC 8 75 505.46 6.76 3810 4
TLC2652AI-8D D SOIC 8 75 507 8 3940 4.32
TLC2652AIN N PDIP 14 25 506 13.97 11230 4.32
TLC2652AIP P PDIP 8 50 506 13.97 11230 4.32
TLC2652C-8D D SOIC 8 75 505.46 6.76 3810 4
TLC2652C-8D D SOIC 8 75 507 8 3940 4.32
TLC2652CN N PDIP 14 25 506 13.97 11230 4.32
TLC2652CP P PDIP 8 50 506 13.97 11230 4.32
TLC2652I-8D D SOIC 8 75 507 8 3940 4.32
TLC2652I-8D D SOIC 8 75 505.46 6.76 3810 4
TLC2652Q-8D D SOIC 8 75 505.46 6.76 3810 4
TLC2652Q-8DG4 D SOIC 8 75 505.46 6.76 3810 4

Pack Materials-Page 3
 PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
JG0008A CDIP - 5.08 mm max height
CERAMIC DUAL IN-LINE PACKAGE

7.11
B 1.60
A 6.22
0.38

6X 2.54

1.65
10.16 4X
1.14
9.00

4X (0.94)

0.58
8X
0.51 3.30 0.38
MIN MIN 0.25 C A B

5.08 MAX
7.87 SEATING PLANE
7.37 C

0.36 0 -15 TYP

TYP
0.20

4230036/A 09/2023
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package can be hermetically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification.
5. Falls within MIL STD 1835 GDIP1-T8

www.ti.com
 EXAMPLE BOARD LAYOUT
JG0008A CDIP - 5.08 mm max height
CERAMIC DUAL IN-LINE PACKAGE

(7.62)

0.05 MAX
ALL AROUND
TYP
1 8
(1.6)

6X (2.54) (R0.05) TYP

SYMM

7X ( 1.6)

8X ( 1)
THRU

METAL
TYP 5
4

SOLDER MASK
OPENING SYMM
TYP

LAND PATTERN EXAMPLE

NON SOLDER MASK DEFINED
SCALE: 9X

4230036/A 09/2023

www.ti.com
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