SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

D Easily Interfaced to Microprocessors D, N, OR PW PACKAGE

(TOP VIEW)
D On-Chip Data Latches
D Monotonic Over the Entire A/D Conversion OUT1 1 16 RFB
Range OUT2 2 15 REF
D Segmented High-Order Bits Ensure GND 3 14 VDD
Low-Glitch Output DB7 4 13 WR
D Interchangeable With Analog Devices DB6 5 12 CS
AD7524, PMI PM-7524, and Micro Power DB5 6 11 DB0
Systems MP7524 DB4 7 10 DB1
DB3 DB2
D Fast Control Signaling for Digital
8 9

Signal-Processor Applications Including

Interface With TMS320 FN PACKAGE
D CMOS Technology (TOP VIEW)

OUT2
OUT1

RFB
REF
NC
KEY PERFORMANCE SPECIFICATIONS
Resolution 8 Bits
Linearity error 1/2LSB Max 3 2 1 20 19
Power dissipation at VDD = 5V 5mW Max GND 4 18 VDD
Setting time 100ns Max DB7 5 17 WR
Propagation delay time 80ns Max NC 6 16 NC
DB6 7 15 CS
description DB5 8 14 DB0
9 10 11 12 13
The TLC7524C, TLC7524E, and TLC7524I are

DB4
DB3

DB2
DB1
NC
CMOS, 8-bit, digital-to-analog converters (DACs)
designed for easy interface to most popular
NC−No internal connection
microprocessors.
The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random
access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,
which produce the highest glitch impulse. The devices provide accuracy to 1/2LSB without the need for thin-film
resistors or laser trimming, while dissipating less than 5mW typically.
Featuring operation from a 5V to 15V single supply, these devices interface easily to most microprocessor buses
or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The TLC7524C is characterized for operation from 0°C to 70°C. The TLC7524I is characterized for operation
from −25°C to +85°C. The TLC7524E is characterized for operation from − 40°C to +85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.


 
 !" # $%&" !#  '%()$!" *!"&+ Copyright  1998−2007, Texas Instruments Incorporated
*%$"# $ " #'&$$!"# '& ",& "&# 
&-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0  !)) '!!&"&#+

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1



 



   

   

SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

functional block diagram

15 R R R
REF
2R 2R 2R 2R 2R
16
RFB
S-1 S-2 S-3 S-8 R
1
OUT1
2
OUT2

12
CS 3
13 Data Latches GND
WR

4 5 6 11
DB7 DB6 DB5 DB0
(MSB) (LSB)

Data Inputs
Terminal numbers shown are for the D or N package.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 16.5V
Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to VDD + 0.3V
Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25V
Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA
Operating free-air temperature range, TA: TLC7524C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
TLC7524I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to +85°C
TLC7524E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C
Lead temperature 1,6mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . +260°C

package/ordering information
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265



 



   

   

SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

recommended operating conditions

VDD = 5V VDD = 15V
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VDD 4.75 5 5.25 14.5 15 15.5 V
Reference voltage, Vref ± 10 ± 10 V
High-level input voltage, VIH 2.4 13.5 V
Low-level input voltage, VIL 0.8 1.5 V
CS setup time, tsu(CS) 40 40 ns
CS hold time, th(CS) 0 0 ns
Data bus input setup time, tsu(D) 25 25 ns
Data bus input hold time, th(D) 10 10 ns
Pulse duration, WR low, tw(WR) 40 40 ns
TLC7524C 0 +70 0 +70
Operating free-air temperature, TA TLC7524I −25 +85 −25 +85 °C
C
TLC7524E −40 +85 −40 +85

electrical characteristics over recommended operating free-air temperature range, Vref = ±10V,
OUT1 and OUT2 at GND (unless otherwise noted)
VDD = 5V VDD = 15V
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
IIH High-level input current VI = VDD 10 10 µA
IIL Low-level input current VI = 0 −10 −10 µA
DB0−DB7 at 0V, WR, CS at 0V,
OUT1 ± 400 ± 200
Output leakage Vref = ± 10V
IIkg nA
current DB0−DB7 at VDD, WR, CS at 0V,
OUT2 ± 400 ± 200
Vref = ± 10V
Quiescent DB0−DB7 at VIHmin or VILmax 1 2 mA
IDD Supply current
Standby DB0−DB7 at 0V or VDD 500 500 µA
Supply voltage sensitivity,
kSVS ∆VDD = ± 10% 0.01 0.16 0.005 0.04 %FSR/%
∆gain/∆VDD
Input capacitance,
Ci VI = 0 5 5 pF
DB0−DB7, WR, CS
OUT1 30 30
DB0−DB7 at 0V, WR, CS at 0V
OUT2 120 120
Co Output capacitance pF
OUT1 120 120
DB0−DB7 at VDD, WR, CS at 0V
OUT2 30 30
Reference input impedance
5 20 5 20 kΩ
(REF to GND)

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

operating characteristics over recommended operating free-air temperature range, Vref = ±10V,
OUT1 and OUT2 at GND (unless otherwise noted)
VDD = 5V VDD = 15V
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
Linearity error ± 0.5 ± 0.5 LSB
Gain error See Note 1 ± 2.5 ± 2.5 LSB
Settling time (to 1/2 LSB) See Note 2 100 100 ns
Propagation delay from digital input
See Note 2 80 80 ns
to 90% of final analog output current
Vref = ±10V (100kHz sinewave)
Feedthrough at OUT1 or OUT2 0.5 0.5 %FSR
WR and CS at 0V, DB0−DB7 at 0V
Temperature coefficient of gain TA = +25°C to MAX ± 0.004 ± 0.001 %FSR/°C
NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = Vref − 1LSB.
2. OUT1 load = 100Ω, Cext = 13pF, WR at 0V, CS at 0V, DB0 − DB7 at 0V to VDD or VDD to 0V.

operating sequence
tsu(CS)
th(CS)
CS

tw(WR)

WR

ÎÎÎ
ÎÎÎ tsu(D)
th(D)

DB0−DB7

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265



 



   

   

SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

PRINCIPLES OF OPERATION

voltage-mode operation
It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode,
a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the
reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage
mode.
R R R
REF (Analog Output Voltage)
2R 2R 2R 2R

0 1 R

OUT1 (Fixed Input Voltage)

OUT2

Figure 1. Voltage Mode Operation

The relationship between the fixed-input voltage and the analog-output voltage is given by the following
equation:
VO = VI (D/256)
where
VO = analog output voltage
VI = fixed input voltage
D = digital input code converted to decimal
In voltage-mode operation, these devices meet the following specification:

PARAMETER TEST CONDITIONS MIN MAX UNIT

Linearity error at REF VDD = 5V, OUT1 = 2.5V, OUT2 at GND, TA = +25°C 1 LSB

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

PRINCIPLES OF OPERATION

The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder,
analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2
bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.
The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference
current, Iref, is switched to OUT2. The current source I/256 represents the constant current flowing through the
termination resistor of the R-2R ladder, while the current source IIkg represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30pF maximum) appears at OUT2 and the on-state switch
capacitance (120pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, Iref would
be switched to OUT1.
The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control
signals. When CS and WR are both low, analog output on these devices responds to the data activity on the
DB0−DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the
analog output. When either the CS signal or WR signal goes high, the data on the DB0−DB7 inputs are latched
until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state
of the WR signal.
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize input
coding for unipolar and bipolar operation respectively.

RFB
R
OUT1

IIkg 30 pF

Iref
REF OUT2

I/256 120 pF
IIkg

Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

PRINCIPLES OF OPERATION

Vref VDD

RA = 2 kΩ RB
(see Note A)

C (see Note B)
RFB
DB0−DB7 OUT1 −
Output
CS +
OUT2
WR
GND

NOTES: A. RA and RB used only if gain adjustment is required.

B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent
ringing or oscillation.

Figure 3. Unipolar Operation (2-Quadrant Multiplication)

Vref VDD
20 kΩ

RA = 2 kΩ RB
(see Note A) 20 kΩ

C (see Note B) −
RFB
Output
DB0−DB7 OUT1 10 kΩ +
−
CS + 5 kΩ
OUT2
WR
GND

NOTES: A. RA and RB used only if gain adjustment is required.

B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

Figure 4. Bipolar Operation (4-Quadrant Operation)

Table 1. Unipolar Binary Code Table 2. Bipolar (Offset Binary) Code

DIGITAL INPUT DIGITAL INPUT
(see Note 3) ANALOG OUTPUT (see Note 4) ANALOG OUTPUT
MSB LSB MSB LSB
11111111 −Vref (255/256) 11111111 Vref (127/128)
10000001 −Vref (129/256) 10000001 Vref (1/128)
10000000 −Vref (128/256) = − Vref/2 10000000 0
01111111 −Vref (127/256) 01111111 −Vref (1/128)
00000001 −Vref (1/256) 00000001 −Vref (127/128)
00000000 0 00000000 −Vref

NOTE 3: LSB = 1/256 (Vref) NOTE 4: LSB = 1/128 (Vref)

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

PRINCIPLES OF OPERATION

microprocessor interfaces

D0−D7 Data Bus

Z−80A

DB0−DB7
WR OUT1
WR TLC7524
OUT2
CS

Decode
IORQ Logic

A0−A15 Address Bus

Figure 5. TLC7524: Z-80A Interface

D0−D7 Data Bus

6800

DB0−DB7
φ2 OUT1
WR TLC7524
OUT2
CS

Decode
VMA
Logic

A0−A15 Address Bus

Figure 6. TLC7524: 6800 Interface

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265



 



   

   

SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

PRINCIPLES OF OPERATION

microprocessor interfaces (continued)

A8−A15 Address Bus

8051
Decode
Logic
8-Bit
Latch

CS
OUT1
WR TLC7524
OUT2
ALE DB0−DB7
WR

AD0−AD7 Adress/Data Bus

Figure 7. TLC7524: 8051 Interface

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

 Revision History

DATE REV PAGE SECTION DESCRIPTION

Front Page — Deleted Available Options table.

6/07 D
2 — Inserted Package/Ordering information.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
 PACKAGE OPTION ADDENDUM

www.ti.com 28-May-2009

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TLC7524CD ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CDG4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CDR ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CFN ACTIVE PLCC FN 20 46 Green (RoHS & CU SN Level-1-260C-UNLIM
no Sb/Br)
TLC7524CFNG3 ACTIVE PLCC FN 20 46 Green (RoHS & CU SN Level-1-260C-UNLIM
no Sb/Br)
TLC7524CFNR ACTIVE PLCC FN 20 1000 Green (RoHS & CU SN Level-1-260C-UNLIM
no Sb/Br)
TLC7524CFNRG3 ACTIVE PLCC FN 20 1000 Green (RoHS & CU SN Level-1-260C-UNLIM
no Sb/Br)
TLC7524CN ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC7524CNE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC7524CNS ACTIVE SO NS 16 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CNSG4 ACTIVE SO NS 16 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CNSR ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CNSRG4 ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CPW ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524ED ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524EDG4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524EDR ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524EDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524EN ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC7524ENE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC7524ID ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 28-May-2009

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TLC7524IDG4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524IDR ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524IFN ACTIVE PLCC FN 20 46 Green (RoHS & CU SN Level-1-260C-UNLIM
no Sb/Br)
TLC7524IFNG3 ACTIVE PLCC FN 20 46 Green (RoHS & CU SN Level-1-260C-UNLIM
no Sb/Br)
TLC7524IN ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC7524INE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
TLC7524IPW ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC7524IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC7524CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLC7524CNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
TLC7524CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLC7524EDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLC7524IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLC7524IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC7524CDR SOIC D 16 2500 367.0 367.0 38.0
TLC7524CNSR SO NS 16 2000 367.0 367.0 38.0
TLC7524CPWR TSSOP PW 16 2000 367.0 367.0 35.0
TLC7524EDR SOIC D 16 2500 367.0 367.0 38.0
TLC7524IDR SOIC D 16 2500 367.0 367.0 38.0
TLC7524IPWR TSSOP PW 16 2000 367.0 367.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane
0.004 (0,10)

0.180 (4,57) MAX

D
0.120 (3,05)
D1 0.090 (2,29)
0.020 (0,51) MIN
3 1 19

0.032 (0,81)
0.026 (0,66)
4 18
D2 / E2

E E1

D2 / E2

8 14

0.050 (1,27) 0.021 (0,53)

9 13 0.013 (0,33)
0.008 (0,20) NOM 0.007 (0,18) M

NO. OF D/E D1 / E1 D2 / E2
PINS
** MIN MAX MIN MAX MIN MAX

20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29)

28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56)

44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10)

52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37)

68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005 / B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

 IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
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