typedef enum logic [1:0]{eq -> 0
neq -> 1
LT 2
GE 3
LTU 4
GEU 5
ADD 6
XOR 7
OR 8
AND 9
SLL10
SRA 11
SRL 12}
typedef enum logic [1:0]{EQ,
NEQ,
LT,
GE,
LTU,
GEU,
ADD,
XOR,
OR,
AND,
SLL,
SRA,
SRL}
module register(parameter size = 32 )( input wire [size-1:0] in;
output wire [size-1:0] out;
);
always@(psoedge clk)
in <= out;
register reg_32(size=32)(.());
register reg_64(size=64)(.());
Fetch Unit
input clk, posedge
input wire reset_n // Active low; synchrnous
input wire [xlen-1: 0] next_instruction; // Received from instruction memory
input wire branch_taken; // Recieved from EX
output wire [xlen-1:0)] current_instruction; // Sent to the decode unit
output wire [xlen-1:0] next_pc; // Sent to the Instrucction Memory
output wire [xlen-1:0] current_pc; // sent to the decode unit
Decode Unit
input clk, posedge
input wire reset_n // Active low; synchrnous
input wire [xlen-1:0)] current_instruction; // Received from Fetch unit
input wire [xlen-1:0] current_pc; // Received from Fetch unit
output wire [3:0] operation; // sent to the EX
output wire [$clog2(xlen)-1:0] src1_addr; // Sent to the Register file
output wire [$clog2(xlen)-1:0] src2_addr; // Sent to the Register file
output wire [$clog2(xlen)-1:0] dest_addr; // Sent to the Register file
output wire [xlen-1:0] imm; // sent to the EX
output wire use_imm; // sent to the EX
output wire is_load_store; // Sent to the memory and writeback unit
Execute unit;
input clk, posedge
input wire reset_n // Active low; synchronous
input wire [3:0] operation; // Recieved from decoder
input wire [xlen-1:0] imm; // Recieved from decoder
input wire use_imm; // Recieved from decoder
input wire [xlen-1:0] operand_a; // rs1; Received from register file
input wire [xlen-1:0] operand_b; // rs2; Received from register file
output wire branch_taken; // Sent to the fetch
output wire [xlen-1:0] result; // Sent to the memory unint and writeback
