Comprehensive Verilog HDL Cheat Sheet

1. Lexical Elements
1.1 Number Representations

1 // Format : < size > ’ < base > < number >
2 8 ’ b10101111 // 8 - bit binary
3 8 ’ hAF // 8 - bit hexadecimal ( same as above )
4 8 ’ d175 // 8 - bit decimal ( same as above )
5 8 ’ o257 // 8 - bit octal ( same as above )
6 16 ’ hFACE // 16 - bit hexadecimal
7 ’ h116 // Unsized hexadecimal
8 4 ’ b1010 // 4 - bit binary
9 32 ’ h0000_00FF // Underscores for readability

1.2 Data Types

Net Types

1 wire // Basic net type , continuously driven

2 wire [7:0] data_bus ; // 8 - bit wide wire
3 wand // Wired AND
4 wor // Wired OR
5 tri // Same as wire but explicitly shows multiple drivers
6 triand // Same as wand but explicitly shows multiple drivers
7 trior // Same as wor but explicitly shows multiple drivers
8 tri0 // Pulled down when undriven
9 tri1 // Pulled up when undriven

Variable Types

1 reg // Holds value until next assignment

2 reg [31:0] counter ; // 32 - bit register
3 integer // 32 - bit signed integer
4 real // Double - precision floating point
5 time // 64 - bit unsigned integer ( for simulation time )
6 realtime // Same as real but for time values

Arrays and Vectors

1 // Vector : multi - bit scalar

2 reg [7:0] byte ; // 8 - bit vector ( byte [7] is MSB , byte [0] is LSB )
3 wire [3:0] nibble ; // 4 - bit vector
4

5 // Arrays : collection of elements

6 reg [7:0] memory [0:1023]; // Memory with 1024 8 - bit elements
7 // Accessed as memory [ address ]
8 reg [7:0] table [0:3][0:3]; // 2 D array (4 x4 table of bytes )

1
 2. Module Structure
2.1 Module Declaration

1 // Basic module structure

2 module module_name ( port1 , port2 , port3 ) ;
3 input port1 ; // Input port declaration
4 input [7:0] port2 ; // 8 - bit input bus
5 output port3 ; // Output port declaration
6

7 // Module internals go here

8

9 endmodule
10

11 // ANSI C style port declaration ( Verilog -2001)

12 module module_name (
13 input port1 ,
14 input [7:0] port2 ,
15 output port3
16 );
17 // Module internals go here
18 endmodule

2.2 Module Instantiation

1 // Named port connections ( recommended )

2 module_name instance_name (
3 . port1 ( signal1 ) ,
4 . port2 ( signal2 ) ,
5 . port3 ( signal3 )
6 );
7

8 // Positional port connections ( order matters )

9 module_name instance_name ( signal1 , signal2 , signal3 ) ;
10

11 // With parameter overrides

12 module_name #(
13 . PARAM1 (8) ,
14 . PARAM2 (16)
15 ) instance_name (
16 . port1 ( signal1 ) ,
17 . port2 ( signal2 ) ,
18 . port3 ( signal3 )
19 );

3. Parameters and Constants

1 // Module parameters
2 module counter #(
3 parameter WIDTH = 8 ,
4 parameter MAX_VALUE = 255
5 )(
6 // port list
7 );
8

9 // Local parameters ( cannot be overridden )

10 localparam HALF_WIDTH = WIDTH / 2;
11

12 // Defparam ( older method , less preferred )

2
13 counter my_counter ( clk , rst , count ) ;
14 defparam my_counter . WIDTH = 16;
15

16 // Parameter override during instantiation

17 counter #(. WIDTH (16) , . MAX_VALUE (65535) ) my_counter ( clk , rst , count ) ;

4. Operators
4.1 Arithmetic Operators

1 + // Addition
2 - // Subtraction
3 * // Multiplication
4 / // Division
5 % // Modulus
6 ** // Exponentiation ( power )

4.2 Relational Operators

1 > // Greater than

2 < // Less than
3 >= // Greater than or equal
4 <= // Less than or equal

4.3 Equality Operators

1 == // Equality ( considering x and z )

2 != // Inequality ( considering x and z )
3 === // Case equality ( exact comparison )
4 !== // Case inequality ( exact comparison )

4.4 Logical Operators

1 ! // Logical NOT
2 && // Logical AND
3 || // Logical OR

4.5 Bitwise Operators

1 ~ // Bitwise NOT
2 & // Bitwise AND
3 | // Bitwise OR
4 ^ // Bitwise XOR
5 ^~ or ~^ // Bitwise XNOR

4.6 Reduction Operators

1 &A // AND reduction ( all bits of A ANDed together )

2 |A // OR reduction ( all bits of A ORed together )
3 ^A // XOR reduction ( all bits of A XORed together )
4 ~& A // NAND reduction
5 ~| A // NOR reduction
6 ~^ A or ^~ A // XNOR reduction

3
 4.7 Shift Operators

1 << // Left shift

2 >> // Right shift ( logical for unsigned , arithmetic for signed )

4.8 Concatenation and Replication

1 // Concatenation
2 {A , B , C } // Join bits together
3 {4 ’ b1010 , 4 ’ b0101 } // Results in 8 ’ b10100101
4

5 // Replication
6 {4{1 ’ b1 }} // Replicates 1 ’ b1 four times : 4 ’ b1111
7 {3{2 ’ b10 }} // Replicates 2 ’ b10 three times : 6 ’ b101010
8 {2{ a , b }} // Same as {a , b , a , b }

5. Procedural Blocks
5.1 Initial Block

1 // Executes once at the beginning of simulation

2 initial begin
3 a = 0;
4 #10 b = 1; // Delay 10 time units , then set b to 1
5 end

5.2 Always Block

1 // Combinational logic ( Verilog -2001)

2 always @ ( a or b or sel ) begin
3 if ( sel )
4 y = a;
5 else
6 y = b;
7 end
8

9 // Combinational logic with implicit sensitivity list ( Verilog -2001)

10 always @ (*) begin
11 // Statements
12 end
13

14 // Sequential logic ( positive edge triggered )

15 always @ ( posedge clk ) begin
16 q <= d ; // Non - blocking assignment
17 end
18

19 // Sequential logic with asynchronous reset

20 always @ ( posedge clk or negedge rst_n ) begin
21 if (! rst_n )
22 q <= 0;
23 else
24 q <= d ;
25 end

4
 6. Assignments
6.1 Continuous Assignment

1 // For wire types ( combinational logic )

2 assign sum = a + b ;
3 assign { carry , sum } = a + b + cin ;

6.2 Procedural Assignments

1 // Blocking assignment ( executes sequentially )

2 always @ ( posedge clk ) begin
3 temp = a + b ; // This executes first
4 c = temp ; // This executes second
5 end
6

7 // Non - blocking assignment ( executes concurrently )

8 always @ ( posedge clk ) begin
9 a <= b ; // All non - blocking assignments update
10 b <= a ; // simultaneously at the end of time step
11 end

7. Conditional Statements
7.1 If-Else Statement

1 if ( condition ) begin
2 // Statements if condition is true
3 end
4 else if ( another_condition ) begin
5 // Statements if another_condition is true
6 end
7 else begin
8 // Statements if all conditions are false
9 end

7.2 Case Statement

1 case ( expression )
2 value1 : begin
3 // Statements for value1
4 end
5 value2 , value3 : begin
6 // Statements for value2 or value3
7 end
8 default : begin
9 // Default statements
10 end
11 endcase
12

13 // Case with don ’t care ( x ) values

14 casex ( expression )
15 4 ’ b1xxx : statements ; // Matches any value starting with 1
16 4 ’ bx1xx : statements ;
17 default : statements ;
18 endcasex
19

20 // Case with high - impedance ( z ) values

5
21 casez ( expression )
22 4 ’ b1 ???: statements ; // ? represents don ’t care
23 4 ’b ?1??: statements ;
24 default : statements ;
25 endcasez

7.3 Conditional Operator

1 // Format : condition ? if_true_expr : if_false_expr

2 assign out = sel ? a : b ;
3

4 // Nested conditional
5 assign out = sel1 ? a : ( sel2 ? b : c ) ;

8. Loops
8.1 For Loop

1 for ( i = 0; i < 8; i = i + 1) begin

2 sum = sum + data [ i ];
3 end

8.2 While Loop

1 while ( count < max ) begin

2 count = count + 1;
3 end

8.3 Repeat Loop

1 repeat (8) begin

2 shift_reg = { shift_reg [6:0] , data_in };
3 end

8.4 Forever Loop

1 forever begin
2 #10 clk = ~ clk ; // Toggle clock every 10 time units
3 end

9. Tasks and Functions

9.1 Task Definition

1 // Tasks can have input , output , and inout arguments

2 task process_data ;
3 input [7:0] data_in ;
4 output [7:0] data_out ;
5 begin
6 #2 data_out = data_in + 8 ’ h5A ;
7 end
8 endtask
9

6
10 // Task with direction specifiers ( Verilog -2001)
11 task automatic process_data (
12 input [7:0] data_in ,
13 output [7:0] data_out
14 );
15 #2 data_out = data_in + 8 ’ h5A ;
16 endtask

9.2 Function Definition

1 // Functions must have at least one input

2 // Functions cannot include timing controls
3 // Functions must return a value
4 function [7:0] add_offset ;
5 input [7:0] data_in ;
6 begin
7 add_offset = data_in + 8 ’ h5A ;
8 end
9 endfunction
10

11 // Function with direction specifiers ( Verilog -2001)

12 function automatic [7:0] add_offset (
13 input [7:0] data_in
14 );
15 return data_in + 8 ’ h5A ;
16 endfunction

9.3 Calling Tasks and Functions

1 // Calling a task
2 process_data ( in_data , out_data ) ;
3

4 // Calling a function
5 result = add_offset ( in_data ) ;

10. Gate-Level Modeling

10.1 Built-in Gate Primitives

1 and ( out , in1 , in2 , ...) ;

2 nand ( out , in1 , in2 , ...) ;
3 or ( out , in1 , in2 , ...) ;
4 nor ( out , in1 , in2 , ...) ;
5 xor ( out , in1 , in2 , ...) ;
6 xnor ( out , in1 , in2 , ...) ;
7 buf ( out1 , out2 , ... , in ) ;
8 not ( out1 , out2 , ... , in ) ;
9

10 // Tri - state buffers

11 bufif0 ( out , in , control ) ; // Active when control is 0
12 bufif1 ( out , in , control ) ; // Active when control is 1
13 notif0 ( out , in , control ) ; // Active when control is 0
14 notif1 ( out , in , control ) ; // Active when control is 1
15

16 // Pull - up and pull - down resistors

17 pullup ( out ) ; // Pulls output to 1 when undriven
18 pulldown ( out ) ; // Pulls output to 0 when undriven

7
 10.2 Gate Delays

1 // Single delay value

2 and #5 a1 ( out , in1 , in2 ) ;
3

4 // Rise , fall delays

5 and #(5 , 7) a1 ( out , in1 , in2 ) ;
6

7 // Rise , fall , turn - off delays

8 bufif1 #(10 , 15 , 5) b1 ( out , in , control ) ;
9

10 // Min : typ : max delays

11 or #(4:5:6 , 6:7:8) o1 ( out , in1 , in2 ) ;

11. Sequential Logic

11.1 D Flip-Flop

1 // Positive edge - triggered without reset

2 always @ ( posedge clk ) begin
3 q <= d ;
4 end
5

6 // Positive edge - triggered with asynchronous reset

7 always @ ( posedge clk or posedge rst ) begin
8 if ( rst )
9 q <= 0;
10 else
11 q <= d ;
12 end
13

14 // Positive edge - triggered with synchronous reset

15 always @ ( posedge clk ) begin
16 if ( rst )
17 q <= 0;
18 else
19 q <= d ;
20 end

11.2 Latches (avoid in synthesis when possible)

1 // D latch ( transparent when enable is high )

2 always @ ( enable or d ) begin
3 if ( enable )
4 q <= d ;
5 end
6

7 // D latch with asynchronous reset

8 always @ ( enable or d or rst ) begin
9 if ( rst )
10 q <= 0;
11 else if ( enable )
12 q <= d ;
13 end

12. Generate Statements

8
 1 // Conditional generate
2 generate
3 if ( WIDTH == 8) begin : gen_8bit
4 adder_8bit adder_inst (a , b , sum ) ;
5 end
6 else begin : gen_generic
7 adder_generic #( WIDTH ) adder_inst (a , b , sum ) ;
8 end
9 endgenerate
10

11 // For loop generate

12 generate
13 genvar i ;
14 for ( i = 0; i < WIDTH ; i = i + 1) begin : gen_loop
15 full_adder fa_inst ( a [ i ] , b [ i ] , c [ i ] , sum [ i ] , c [ i +1]) ;
16 end
17 endgenerate
18

19 // Case generate
20 generate
21 case ( MODE )
22 0: begin : gen_mode0
23 // Mode 0 logic
24 end
25 1: begin : gen_mode1
26 // Mode 1 logic
27 end
28 default : begin : gen_default
29 // Default mode logic
30 end
31 endcase
32 endgenerate

13. Compiler Directives

1 ‘ define CONSTANT_NAME value // Define a macro
2 ‘ undef CONSTANT_NAME // Undefine a macro
3

4 ‘ ifdef CONSTANT_NAME // Conditional compilation

5 // Code if CONSTANT_NAME is defined
6 ‘ elsif ANOTHER_CONSTANT
7 // Code if ANOTHER_CONSTANT is defined
8 ‘ else
9 // Code if none are defined
10 ‘ endif
11

12 ‘ include " filename . v " // Include another file

13

14 ‘ timescale 1 ns /1 ps // Set time unit / precision

15

16 ‘ resetall // Reset all compiler directives

17

18 ‘ celldefine // Mark module as cell for back - annotation

19 ‘ endcelldefine // End cell definition

14. System Tasks and Functions

14.1 Simulation Control

9
 1 $finish ; // End simulation
2 $stop ; // Pause simulation
3

4 $time ; // Current simulation time

5 $realtime ; // Current simulation time as a real number
6

7 $random ; // Random 32 - bit integer

8 $random ( seed ) ; // Random 32 - bit integer with seed

14.2 Display and File I/O

1 $display ( " Text % h % d " , hex_val , dec_val ) ; // Print with newline

2 $write ( " Text % h % d " , hex_val , dec_val ) ; // Print without newline
3 $strobe ( " Text % h % d " , hex_val , dec_val ) ; // Print after all assignments for
current time
4 $monitor ( " Time =% t a =% d " , $time , a ) ; // Print whenever any monitored
variable changes
5

6 // Format specifiers
7 // % h - hex , % d - decimal , % b - binary , % o - octal
8 // % c - character , % s - string , % t - time , % m - hierarchical name
9

10 // File operations
11 $fopen ( " filename . txt " ) ; // Open file
12 $fclose ( file_handle ) ; // Close file
13 $fdisplay ( file_handle , " Text % d " , value ) ; // Display to file
14 $fwrite ( file_handle , " Text % d " , value ) ; // Write to file
15 $fstrobe ( file_handle , " Text % d " , value ) ; // Strobe to file
16 $fmonitor ( file_handle , " Text % d " , value ) ; // Monitor to file

14.3 Value Change Dump (VCD)

1 $dumpfile ( " waveform . vcd " ) ; // Set dump file name

2 $dumpvars ; // Dump all variables
3 $dumpvars (0 , top ) ; // Dump all variables in top module
4 $dumpvars (1 , top ) ; // Dump variables in top module , not in submodules
5 $dumpoff ; // Pause dumping
6 $dumpon ; // Resume dumping
7 $dumpall ; // Dump current values

15. Common Design Patterns

15.1 Clock Generator (for testbenches)

1 // Simple clock generator

2 initial begin
3 clk = 0;
4 forever #5 clk = ~ clk ; // 10 time units per cycle
5 end

15.2 Counter

1 // Simple binary counter

2 always @ ( posedge clk or posedge rst ) begin
3 if ( rst )
4 count <= 0;

10
 5 else if ( enable )
6 count <= count + 1;
7 end

15.3 Shift Register

1 // Serial - in , serial - out shift register

2 always @ ( posedge clk or posedge rst ) begin
3 if ( rst )
4 shift_reg <= 0;
5 else if ( enable )
6 shift_reg <= { shift_reg [6:0] , data_in };
7 end

15.4 State Machine

1 // Two - process state machine ( state and output )

2 // State register
3 always @ ( posedge clk or posedge rst ) begin
4 if ( rst )
5 state <= IDLE ;
6 else
7 state <= next_state ;
8 end
9

10 // Next state and output logic

11 always @ (*) begin
12 // Default values
13 next_state = state ;
14 output_reg = 0;
15

16 case ( state )
17 IDLE : begin
18 if ( start )
19 next_state = STATE1 ;
20 end
21 STATE1 : begin
22 output_reg = 1;
23 if ( condition )
24 next_state = STATE2 ;
25 end
26 STATE2 : begin
27 output_reg = 2;
28 if ( done )
29 next_state = IDLE ;
30 end
31 default : next_state = IDLE ;
32 endcase
33 end

16. Synthesis Guidelines

16.1 Combinational Logic

1 // Use continuous assignment

2 assign out = a & b | c ;
3

4 // Or use always block with full sensitivity list

11
 5 always @ (*) begin
6 out = a & b | c ;
7 end

16.2 Sequential Logic

1 // Use always block with clock edge

2 always @ ( posedge clk ) begin
3 q <= d ; // Use non - blocking assignments
4 end

16.3 Avoiding Latches

1 // Always specify all possible conditions

2 always @ (*) begin
3 if ( condition )
4 out = a ;
5 else
6 out = b ; // Default case prevents latch
7 end
8

9 // In case statements , always include default

10 case ( sel )
11 2 ’ b00 : out = a ;
12 2 ’ b01 : out = b ;
13 2 ’ b10 : out = c ;
14 default : out = d ; // Prevents latch
15 endcase

16.4 Reset Strategies

1 // Asynchronous reset ( preferred for ASIC )

2 always @ ( posedge clk or posedge rst ) begin
3 if ( rst )
4 q <= 0;
5 else
6 q <= d ;
7 end
8

9 // Synchronous reset ( sometimes preferred for FPGA )

10 always @ ( posedge clk ) begin
11 if ( rst )
12 q <= 0;
13 else
14 q <= d ;
15 end

17. Simulation and Testbench Techniques

17.1 Basic Testbench Structure

1 module testbench ;
2 // Declare signals
3 reg clk , rst , in ;
4 wire out ;
5

12
 6 // Instantiate design under test ( DUT )
7 my_module dut (
8 . clk ( clk ) ,
9 . rst ( rst ) ,
10 . in ( in ) ,
11 . out ( out )
12 );
13

14 // Clock generation
15 initial begin
16 clk = 0;
17 forever #5 clk = ~ clk ;
18 end
19

20 // Test stimulus
21 initial begin
22 // Initialize
23 rst = 1;
24 in = 0;
25

26 // Release reset
27 #20 rst = 0;
28

29 // Apply stimulus
30 #10 in = 1;
31 #10 in = 0;
32

33 // Monitor results
34 $display ( " Time =% t , out =% b " , $time , out ) ;
35

36 // End simulation
37 #100 $finish ;
38 end
39 endmodule

17.2 Self-Checking Testbench

1 // Check expected output

2 initial begin
3 // Wait for output to stabilize
4 #30;
5

6 // Check result
7 if ( out !== 1 ’ b1 ) begin
8 $display (" ERROR : Expected out =1 , got out =% b " , out ) ;
9 $finish ;
10 end
11 else begin
12 $display (" Test passed !") ;
13 end
14 end

18. Advanced Topics

18.1 Memory Modeling

1 // Dual - port RAM model

2 reg [ DATA_WIDTH -1:0] mem [0: DEPTH -1];
3

4 // Write port

13
 5 always @ ( posedge clk ) begin
6 if ( we )
7 mem [ wr_addr ] <= wr_data ;
8 end
9

10 // Read port
11 always @ ( posedge clk ) begin
12 if ( re )
13 rd_data <= mem [ rd_addr ];
14 end

18.2 Clock Domain Crossing

1 // Two - flop synchronizer

2 reg sync_ff1 , sync_ff2 ;
3

4 always @ ( posedge clk_dest or posedge rst ) begin

5 if ( rst ) begin
6 sync_ff1 <= 0;
7 sync_ff2 <= 0;
8 end
9 else begin
10 sync_ff1 <= signal_src ;
11 sync_ff2 <= sync_ff1 ;
12 end
13 end
14

15 assign signal_synced = sync_ff2 ;

14