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Sri Sai Vidya Vikas Shikshana Samithi ®

SAI VIDYA INSTITUTE OF TECHNOLOGY
(Approved by AICTE, New Delhi, Affiliated to VTU, Recognized by Govt. of Karnataka)
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
RAJANUKUNTE, BANGALORE 560 064, KARNATAKA
Phone: 080-28468191/96/97/98 * E-mail: info@saividya.ac.in * URL www.saividya.ac.in

MODULE WISE QUESTION BANK

Course: VERILOG HDL

Course Code: 18EC56

CO1. Demonstrate understanding of IC Design flow, basic constructs and module structure of
Verilog HDL.
CO2. Model digital systems in Verilog HDL at gate-level, dataflow (RTL) and behavioral levels of
Abstraction.
CO3. Write programs effectively using Verilog tasks, functions and various modeling techniques.
CO4. Interpret the Verilog HDL constructs used in Logic Synthesis.
CO5. Design and verify the functionality of digital circuit/system using test benches.

Complied By:
NAYANA K
Assistant Professor, Dept. of ECE
Sai Vidya Institute of technology
2020-21

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MODULE 1a: Overview of Digital Design with Verilog HDL:

Sl. QUESTIONS CO BT
No Marks-Year
level
1. Explain a typical design flow for designing VLSI IC circuit using the block 06M- Jan 2018
diagram 08M-July 2018
CO1 L2 10M-Jan 2019
Explain the typical design flow with verilog HDL for designing VLSI IC. 08M-Jan 2020
2. Explain the trends in Hardware Description Languages (HDLs). 06M-Jan 2018
Discuss the trends in HDLs. CO1 L2 06M-Jan 2020
3. Explain the advantages of HDLs over schematic based design 06M-Jan 2020
What are the advantages of HDLs compared to traditional schematic based CO1 L2 05M-Jan 2020
design?
4. Mention the features of Verilog HDL. CO1 L2 05M-Jan 2020
5. Explain the factors that have made Verilog HDL popular. CO1 L2 06M-Model QP
6. List the importance of HDL. Mention the two popular HDLs. CO1 L2 06M-Model QP
7. How is Verilog different from High level language. CO1 L2 06M-Model QP

MODULE 1b: Hierarchical Modeling Concepts

Sl. QUESTIONS CO BT
No Marks-Year
level
1. Explain top down design methodology and bottom up design methodology 10M-Jan 2018
8M-July 2018
CO1 L2 10M-Jan 2020
Describe the digital system design using hierarchical design methodologies.
4M- Model QP
2. With a block diagram of 4-bit ripple carry counter, explain the design 10M-Jan 2018
hierarchy. CO1 L2 8M-July 2018
10M-Jan 2020
3. What is an instance? Explain module instantiation with an example. 8M-July 2018
CO1 L2

4. Explain top-down design methodology with an example. CO1 L2

06M-Jan 2019
08M-Jan 2020
5. Explain bottom-up design methodology with an example. CO1 L2 06M-Jan 2019
6. Explain the different levels of abstraction used for programming in Verilog. 10M-Jan 2019
Discuss the different levels of abstraction used in Verilog modelling. CO1 L2 8M- Model QP

7. Discuss different type of module level with an example. CO1 L2 08M-July 2019
8. List the basic type of design methodology. Differentiate between them. CO1 L2 08M-July 2019
9. What do you mean by instantiation and instances? Write a verilog code for L2, 08M-July 2019
4-bit ripple carry counter to show instantiation and instances. CO1
L3
10. What is the need of stimulus block in simulation, discuss with an example. CO1 L3 08M-July 2019
11. Write the verilog code for 4-bit ripple carry counter. CO1 L3 07M-Jan 2020
12. What are the 2 styles of stimulus application? Explain each method in brief. 07M-Jan 2020
What is stimulus? Explain different types of stimulus block instantiation. CO1 L2 (1+7M)-Model
QP

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MODULE 2a: Basic Concepts

Sl. QUESTIONS CO BT
No Marks-Year
level
1. Explain the following data types with an example in Verilog: 10M-Jan 2018
i) Nets ii) Register iii) Integers iv) real v) Time register CO1 L2

2. Explain the following data types with an example in Verilog: 8M-July 2018
i) Nets ii) Register iii) Memories iv) Parameters CO1 L2

3. Explain monitoring, stopping and finishing in a simulation and also compiler 8M-July 2018
directives. CO1 L2

4. Write a note on following lexical conventions used in verilog: 8M-July 2018

i) Operators ii) Identifiers & Keywords iii) Escaped identifiers iv) Strings CO1 L2

5. Explain system tasks and compiler directives in Verilog. 6M-Jan 2019

List and explain different system tasks and compiler directives of verilog. CO1 L2 10M-July 2019
6. Write a note on
i) Registers ii) Nets iii) Arrays iv) Parameters v)Vectors vi) Memories CO1 L2 12M-Jan 2019
7. Explain how integer, real and time register data types used in verilog. CO1 L2
08M-July 2019

8. Explain the following data types with an example in Verilog: 08M-Jan 2020
i) Vectors ii) Register iii) Time iv) real CO1 L2

9. Explain the following data types with an example in Verilog: 10M-Jan 2020
i) Nets ii) Register iii) Integers iv) Parameters v) Arrays CO1 L2

10. How to write comments in Verilog HDL, explain with examples. CO1 L2 04M-Jan 2020

11. Explain $display, $monitor , $finish and $ stop system tasks with examples CO1 L2 08M-Jan 2020
12. List all the data types available in Verilog HDL. Explain any three data types (2+6M)-Model
with examples. CO1 L2 QP

13. Explain the port connection rules of Verilog HDL with examples. 6M-Model QP
CO1 L2
14. Bring out the difference between $display and $monitor with an example. 6M-Model QP
CO1 L2

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MODULE 2b: Modules and Ports

Sl.
QUESTIONS CO BT
No Marks-Year
level
1. With a neat block diagram, explain the components of verilog module. 06M-Jan 2018
CO1 L2 08M-Jan 2020

2. Explain the port connection rules.

CO1 L2 06M-Jan 2018

3. Explain the two methods of connecting ports to external signals with an 10M-Jan 2018
example 08M-July 2018
CO1 L2
Describe different methods of connecting ports to external signals. 06M-Model QP
4. What are the basic components of a module? Explain all the components 06M-Jan 2019
of a verilog module with a neat block diagram. CO1 L2

5. 04M-Jan 2019
Write verilog description of SR latch. Also write stimulus code. CO1 L2 06M-Jan 2020
6. Declare a top-level module “Stimulus”. Define Reg_in(4 bits) and clk(1 bit)
as regiter variables and Reg_out( 4 bits) as wire. Instantiate the module
“shift-reg” in “stimulus block” and connect the ports by ordered list. Declare CO1 L2 04M-Jan 2019
A(4 bit) and clock (1 bit) as inputs and B (4 bit) as output in “shift-reg”
module(no need to show internals). Write a verilog code for the above.
7. List the components of a verilog module. Write a verilog code to list the 06M-July 2019
components of SR latch.
CO1 L2
What are the components of SR latch? Write Verilog HDL module of SR latch (2+3+3M)
and test bench to verify the SR Latch Model QP
8. Show how connections between signals are specified in the module
instantiation and the parts in a module definition. CO1 L2 08M-July 2019
9. What are the components of SR-latch? Write verilog HDL module of SR-
latch. CO1 L2 08M-Jan 2020
10. With an example , explain hierarchical names. 08M-Jan 2020
CO1 L2
11. Declare the following variables in verilog:
i) An 8-bit vector called a_in. 04M-Jan 2020
ii) An integer called count. CO1 L2
iii) A memory MEM containing 256 words of 64 bits each
iv) A parameter cache_size equal to 512.
12. Explain with example how sized and unsized numbers are represented in
Verilog. CO1 L2 06M-Model QP

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MODULE 3a: Gate-Level Modeling:

Sl.
QUESTIONS CO BT
No Marks-Year
level
1. What are rise, fall and turn-off delays? How they are specified in verilog 06M-Jan 2018
06M-Jan 2020-
CO2 L2
08M-Jan 2020
17sch
2. Design a 2-to-1 multiplexer using bufif0 & bufif1 gates. The delay
specification for these gates are as follows:
Delay Min Typ Max
Rise 1 2 3
CO2 L3 10M-Jan 2018
Fall 3 4 5
Turn-off 5 6 7
Write gate level description and stimulus in verilog

3. Write the verilog code & stimulus for gate level 4:1 multiplexer with their
08M-July 2018
logical diagram. CO2 L3 08M-Jan 2019

4. Write the gate level description for 4-bit ripple carry adder.
CO2 L3 6M-July 2018

5. Define bufif/notif and write gate instantiation of bufif, notif gates. CO2 L2 4M-July 2018

6. Write the verilog description of 4 bit ripple carry adder at gate level
CO2 L3 08M-Jan 2019
abstraction, with a neat block diagram. Also, write the stimulus block.
7. Discuss on And/Or gates with respect to logic symbols, gate instantiation
CO2 L2 08M-July 2019
and truth tables.
8. Design AOI based 4:1 Multiplexer, write verilog description for the same
CO2 L3 08M-July 2019
and its stimulus.
9. Discuss briefly available gate delays in verilog CO2 L2 06M-July 2019
10. With the help of logic diagram, write a verilog code for 4 to 1 multiplexer
CO2 L3 08M-Jan 2020
using gate-level modeling.
11. Discuss And , Or and Not gates with respect to logic symbols, gate
CO2 L2 08M-Jan 2020
instantiation and truth tables.
12. Mention the symbol, truth table and an example for following primitives
CO2 L2 06M-Model QP
i. BUFIF1 ii. NOTIF0 iii. AND

13. Write a Verilog code to realize 2-bit comparator (A1A0 & B1B0) in gate
level to give the outputs AequalB, AgreaterthanB, AlesserthanB. Verify CO2 L3 06M-Model QP
the code with an appropriate test bench.

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MODULE 3b : Dataflow Modeling:

Sl. QUESTIONS CO BT
No Marks-Year
level
1. Write a verilog dataflow level of abstraction for 4-to-1 multiplexer using
conditional operator. CO2 L3 6M-Jan 2018

2. Write a verilog dataflow description for 4-bit full adder with carry look
CO2 L3 10M-Jan 2018
ahead.
3. Explain the following operators used in Verilog with an example
CO2 L2 8M-July 2018
i) Logical ii) Replication iii) Shift iv) Conditional
4. Define implicit continuous assignment delay and net declaration delay
CO2 L2 6M-July 2018
with an example.
5. What would be the output of the following: a =4’b1010 b= 4’b1111
i) a & b ii) a && b iii) & a iv) a >> 1 v) a>>>1 CO2 L4 08M-Jan 2019
vi) y = {2{a}} vii) a^b viii) z = {a , b}
6. A full subtractor has three 1-bit inputs x, y and z (previous borrow) & two
1-bit outputs D (Difference) & B (Borrow). The logic equations are
D = x’y’z + x’y z’+x y’z’ +xyz B = x’y + x’z + yz
CO2 L3 08M-Jan 2019
Write verilog description using dataflow modeling. Instantiate the
subtractor module inside a stimulus block and test all possible combinations
of inputs x, y& z.
7. List the characteristics of continuous assignments. 04M-July 2019
What is continuous assignment? Discuss the rules of continuous CO2 L2
assignment. 06M-Model QP
8. Write the verilog description of 4 bit full adder dataflow operators and 06M-July 2019
with carry look ahead mechanism. 10M-Jan 2020
CO2 L3 08M-Jan 2020
Explain Carry Look Ahead adder. Write a Verilog code with data flow
style program for carry look ahead adder 10M-Model QP
9. Explain conditional and concatenation operator with an example. CO2 L2 06M-Jan 2020
10. What would be the output of the following: a =4’b0111 b= 4’b101
CO2 L4 06M-Jan 2020
i) & b ii) a <<< 2 iii) {a , b} iv) {2{b}} v) a^b vi) a | b
11. Write the verilog code for 4-to-1 multiplexer using, 06M-Jan 2020
i) Conditional operator ii) Logic equation CO2 L3
Write a Verilog code for 4X1 MUX using conditional operators. 04M-Model QP
12. Explain assignment delay, implicit assignment delay and net declaration
delay for continuous assignment statements. CO2 L2 06M-Jan 2020

13. A=5’b10101, B=5’b11111, C=5’b11000, D= 5’b10001.

Evaluate
CO2 L4 08M-Model QP
i.A&B ii. C^^D iii B % D iv. B<<2 v. !(&A)
vi. Y=( A>=B) vii. Y= {A[2], B[0], C} viii. y=( A > B)? 1:0

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MODULE 4a: Behavioral Modeling:

Sl. QUESTIONS CO BT
Marks-Year
No level
1. Explain the blocking assignment statements and non-blocking assignment 8M-Jan 2018
statements with relevant examples. 8M-July 2018
08M-Jan 2020
OR
CO2 L2
Differentiate between blocking and non-blocking assignments. 07M-July 2019
Differentiate i. always and initial procedural statements
ii. blocking and non-blocking statements. 08M-Model QP
2. Write a note on the following loop statements:
CO2 L2 08M-Jan 2018
i) While loop ii) forever loop
3. Explain sequential and parallel blocks with examples 08M-Jan 2018
06M-Jan 2019
or 08M-Jan 2020
CO2 L2
Compare Parallel or sequential blocks. 06M-Model QP
4. Write a verilog program for 8-to-1 multiplexer using case statement. 08M-Jan 2018
CO2 L3 06M-Jan 2019
06M-Jan 2020
5. Explain structured procedures in behavioral description with example. 08M-July 2018
CO2 L2
Explain structured procedures in verilog. 06M-Jan 2019
6. Explain different types of event based timing control in verilog. 08M-July 2018
CO2 L2 08M-Jan 2020
06M-Jan 2020
7. Explain with an example the two types of blocks in verilog behavioral
CO2 L2 8M-July 2018
description.
8. Explain casex and casez statements in verilog. CO2 L2 04M-Jan 2019
9. Explain procedural assignment statements in verilog. CO2 L2 06M-Jan 2019
10. Write a verilog code to find the first bit with a value 1 in
CO2 L3 04M-Jan 2019
Flag =16’b0010_0000_0000_0000
11. Explain multiway branchings loops with examples. CO2 L2 14M-July 2019
12. Outline the characteristics of parallel blocks.
CO2 L2 02M-July 2019

13. List and discuss different delay based timing control.

CO2 L2 09M-July 2019

14. Write a verilog HDL code for JK flip flop using case statement
CO2 L3 08M-Jan 2020

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15. With syntax, explain conditional & branching loop statements in verilog
HDL. CO2 L2 08M-Jan 2020

16. Write the verilog behavioral description of 4-bit binary counter.

CO2 L3 06M-Jan 2020

17. Illustrate the use of while loop and repeat loop with suitable examples
CO2 L2 06M-Jan 2020

18. Explain the following control statement with an example.

CO2 L2 06M-Model QP
i) if …else statement ii) For loop.

19. Write a Verilog code to generate the following sequence 1,2,4,6,7,1,2….

Verify the code with an appropriate test bench. CO2 L3 06M-Model QP

MODULE 4b: Tasks and Functions

Sl.
No QUESTIONS BT
CO Marks-Year
level
1.
List out the differences between tasks and functions. CO3 L2 06M-Model QP

2. Write Verilog program to call a function called calc_parity which computes the
parity of a 32-bit data, [31-0]Data and display odd or even parity message. CO3 L3 08M-Model QP

3. Explain task declaration and invocation with an example Expected

CO3 L2 question
4. Describe automatic tasks with an example CO3 L2 “
5. Explain function declaration and invocation with an example CO3 L2 “
6. With an example describe automatic functions. CO3 L2 “
7. Explain constant and signed functions in Verilog. CO3 L2 “

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MODULE 5a: Useful Modeling Techniques

Sl. QUESTIONS CO BT
No Marks-Year
level
1. What is parameter overriding and why it is needed? Discuss different
techniques of parameter overriding with an example for each. CO3 L2 8M-Model QP

2. Explain the “force and release” statement with an example. How is it

different from assign? CO3 L2 8M-Model QP
3. Discuss the system tasks related to files.
CO3 L2 4M-Model QP
4. Describe the “assign and deassign” statement with an example. CO3 L2
Expected
question
5. Describe the conditional compilation and conditional execution with an “
CO3 L2
example.
6. Explain Debugging and analysis of simulation with VCD file CO3 L2 “

7. Discuss the useful system tasks with an example. CO3 L2 “

8. With an example, explain how to initialize memory from a file. CO3 L2 “

9. With examples, explain file output system task. CO3 L2 “

10. Describe Strobing, hierarchy and random number generation system task “
CO3 L2
with an example.

MODULE 5b: Logic Synthesis with Verilog

Sl. QUESTIONS CO BT
Marks-Year
No level
1.
Define the term logic synthesis. CO4 L2 2M- Model QP

2. With a neat flow chart explain Computer-Aided logic synthesis process. CO4 L2 10M-Model QP

What will the following statement translate to when run on a logic

synthesis tool.
i) assign y= (a&b) | (c&d) where out, a, b, c, d are 3 bit vectors
3. ii) if (s) CO4 L3 8M- Model QP
out=i1;
else
out=i0;
What is logic synthesis? Describe the designers mind used as the logic Expected
4. CO4 L2
synthesis tool questions
5. Explain the impact of logic synthesis. CO4 L2 “
6. With a neat flow diagram explain the synthesis design flow. CO4 L2 “
7. Explain the functional verification of gate-level netlist with an example. CO4 L2 “
8. With an example, explain each step in the synthesis flow. CO4 L2 “

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Illustrate how logic synthesis tools interpret the assign statement in

9. CO4 L3 “
verilog.
With an example for each, explain how interpretation of verilog constructs
10. CO4 L2 “
is done in verilog.
Illustrate how logic synthesis tools interpret the conditional and case
11. CO4 L3 “
statement in verilog.
12. List out the verilog HDL constructs that are acceptable for logic synthesis. CO4 L2 “

Nayana K
Course Coordinator

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